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| author | David Blaikie <dblaikie@gmail.com> | 2015-02-27 21:17:42 +0000 |
|---|---|---|
| committer | David Blaikie <dblaikie@gmail.com> | 2015-02-27 21:17:42 +0000 |
| commit | a79ac14fa68297f9888bc70a10df5ed9b8864e38 (patch) | |
| tree | 8d8217a8928e3ee599bdde405e2e178b3a55b645 /llvm/test/Transforms/LoopVectorize/PowerPC | |
| parent | 83687fb9e654c9d0086e7f6b728c26fa0b729e71 (diff) | |
| download | bcm5719-llvm-a79ac14fa68297f9888bc70a10df5ed9b8864e38.tar.gz bcm5719-llvm-a79ac14fa68297f9888bc70a10df5ed9b8864e38.zip | |
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction
Essentially the same as the GEP change in r230786.
A similar migration script can be used to update test cases, though a few more
test case improvements/changes were required this time around: (r229269-r229278)
import fileinput
import sys
import re
pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)")
for line in sys.stdin:
sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line))
Reviewers: rafael, dexonsmith, grosser
Differential Revision: http://reviews.llvm.org/D7649
llvm-svn: 230794
Diffstat (limited to 'llvm/test/Transforms/LoopVectorize/PowerPC')
| -rw-r--r-- | llvm/test/Transforms/LoopVectorize/PowerPC/small-loop-rdx.ll | 2 | ||||
| -rw-r--r-- | llvm/test/Transforms/LoopVectorize/PowerPC/vsx-tsvc-s173.ll | 10 |
2 files changed, 6 insertions, 6 deletions
diff --git a/llvm/test/Transforms/LoopVectorize/PowerPC/small-loop-rdx.ll b/llvm/test/Transforms/LoopVectorize/PowerPC/small-loop-rdx.ll index bc043475a64..2898af2986d 100644 --- a/llvm/test/Transforms/LoopVectorize/PowerPC/small-loop-rdx.ll +++ b/llvm/test/Transforms/LoopVectorize/PowerPC/small-loop-rdx.ll @@ -30,7 +30,7 @@ for.body: ; preds = %for.body, %for.body %indvars.iv = phi i64 [ 0, %for.body.lr.ph ], [ %indvars.iv.next, %for.body ] %redx.05 = phi double [ 0.000000e+00, %for.body.lr.ph ], [ %add, %for.body ] %arrayidx = getelementptr inbounds double, double* %arr, i64 %indvars.iv - %1 = load double* %arrayidx, align 8 + %1 = load double, double* %arrayidx, align 8 %add = fadd fast double %1, %redx.05 %indvars.iv.next = add i64 %indvars.iv, 1 %lftr.wideiv = trunc i64 %indvars.iv to i32 diff --git a/llvm/test/Transforms/LoopVectorize/PowerPC/vsx-tsvc-s173.ll b/llvm/test/Transforms/LoopVectorize/PowerPC/vsx-tsvc-s173.ll index 27a11028b5b..65b3919585e 100644 --- a/llvm/test/Transforms/LoopVectorize/PowerPC/vsx-tsvc-s173.ll +++ b/llvm/test/Transforms/LoopVectorize/PowerPC/vsx-tsvc-s173.ll @@ -9,7 +9,7 @@ target triple = "powerpc64-unknown-linux-gnu" define signext i32 @s173() #0 { entry: - %0 = load i32* @ntimes, align 4 + %0 = load i32, i32* @ntimes, align 4 %cmp21 = icmp sgt i32 %0, 0 br i1 %cmp21, label %for.cond1.preheader, label %for.end12 @@ -20,9 +20,9 @@ for.cond1.preheader: ; preds = %for.end, %entry for.body3: ; preds = %for.body3, %for.cond1.preheader %indvars.iv = phi i64 [ 0, %for.cond1.preheader ], [ %indvars.iv.next, %for.body3 ] %arrayidx = getelementptr inbounds %struct.GlobalData, %struct.GlobalData* @global_data, i64 0, i32 0, i64 %indvars.iv - %1 = load float* %arrayidx, align 4 + %1 = load float, float* %arrayidx, align 4 %arrayidx5 = getelementptr inbounds %struct.GlobalData, %struct.GlobalData* @global_data, i64 0, i32 3, i64 %indvars.iv - %2 = load float* %arrayidx5, align 4 + %2 = load float, float* %arrayidx5, align 4 %add = fadd float %1, %2 %3 = add nsw i64 %indvars.iv, 16000 %arrayidx8 = getelementptr inbounds %struct.GlobalData, %struct.GlobalData* @global_data, i64 0, i32 0, i64 %3 @@ -33,7 +33,7 @@ for.body3: ; preds = %for.body3, %for.con for.end: ; preds = %for.body3 %inc11 = add nsw i32 %nl.022, 1 - %4 = load i32* @ntimes, align 4 + %4 = load i32, i32* @ntimes, align 4 %mul = mul nsw i32 %4, 10 %cmp = icmp slt i32 %inc11, %mul br i1 %cmp, label %for.cond1.preheader, label %for.end12 @@ -42,7 +42,7 @@ for.end12: ; preds = %for.end, %entry ret i32 0 ; CHECK-LABEL: @s173 -; CHECK: load <4 x float>* +; CHECK: load <4 x float>, <4 x float>* ; CHECK: add i64 %index, 16000 ; CHECK: ret i32 0 } |

