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| author | Eric Christopher <echristo@gmail.com> | 2019-04-17 04:52:47 +0000 |
|---|---|---|
| committer | Eric Christopher <echristo@gmail.com> | 2019-04-17 04:52:47 +0000 |
| commit | cee313d288a4faf0355d76fb6e0e927e211d08a5 (patch) | |
| tree | d386075318d761197779a96e5d8fc0dc7b06342b /llvm/test/Transforms/LoopUnswitch | |
| parent | c3d6a929fdd92fd06d4304675ade8d7210ee711a (diff) | |
| download | bcm5719-llvm-cee313d288a4faf0355d76fb6e0e927e211d08a5.tar.gz bcm5719-llvm-cee313d288a4faf0355d76fb6e0e927e211d08a5.zip | |
Revert "Temporarily Revert "Add basic loop fusion pass.""
The reversion apparently deleted the test/Transforms directory.
Will be re-reverting again.
llvm-svn: 358552
Diffstat (limited to 'llvm/test/Transforms/LoopUnswitch')
43 files changed, 2732 insertions, 0 deletions
diff --git a/llvm/test/Transforms/LoopUnswitch/2006-06-13-SingleEntryPHI.ll b/llvm/test/Transforms/LoopUnswitch/2006-06-13-SingleEntryPHI.ll new file mode 100644 index 00000000000..c586323b4b8 --- /dev/null +++ b/llvm/test/Transforms/LoopUnswitch/2006-06-13-SingleEntryPHI.ll @@ -0,0 +1,36 @@ +; RUN: opt < %s -loop-unswitch -disable-output +; RUN: opt < %s -loop-unswitch -enable-mssa-loop-dependency=true -verify-memoryssa -disable-output + + %struct.BLEND_MAP = type { i16, i16, i16, i32, %struct.BLEND_MAP_ENTRY* } + %struct.BLEND_MAP_ENTRY = type { float, i8, { [5 x float], [4 x i8] } } + %struct.TPATTERN = type { i16, i16, i16, i32, float, float, float, %struct.WARP*, %struct.TPATTERN*, %struct.BLEND_MAP*, { %struct.anon, [4 x i8] } } + %struct.TURB = type { i16, %struct.WARP*, [3 x double], i32, float, float } + %struct.WARP = type { i16, %struct.WARP* } + %struct.anon = type { float, [3 x double] } + +define void @Parse_Pattern() { +entry: + br label %bb1096.outer20 +bb671: ; preds = %cond_true1099 + br label %bb1096.outer23 +bb1096.outer20.loopexit: ; preds = %cond_true1099 + %Local_Turb.0.ph24.lcssa = phi %struct.TURB* [ %Local_Turb.0.ph24, %cond_true1099 ] ; <%struct.TURB*> [#uses=1] + br label %bb1096.outer20 +bb1096.outer20: ; preds = %bb1096.outer20.loopexit, %entry + %Local_Turb.0.ph22 = phi %struct.TURB* [ undef, %entry ], [ %Local_Turb.0.ph24.lcssa, %bb1096.outer20.loopexit ] ; <%struct.TURB*> [#uses=1] + %tmp1098 = icmp eq i32 0, 0 ; <i1> [#uses=1] + br label %bb1096.outer23 +bb1096.outer23: ; preds = %bb1096.outer20, %bb671 + %Local_Turb.0.ph24 = phi %struct.TURB* [ %Local_Turb.0.ph22, %bb1096.outer20 ], [ null, %bb671 ] ; <%struct.TURB*> [#uses=2] + br label %bb1096 +bb1096: ; preds = %cond_true1099, %bb1096.outer23 + br i1 %tmp1098, label %cond_true1099, label %bb1102 +cond_true1099: ; preds = %bb1096 + switch i32 0, label %bb1096.outer20.loopexit [ + i32 161, label %bb671 + i32 359, label %bb1096 + ] +bb1102: ; preds = %bb1096 + %Local_Turb.0.ph24.lcssa1 = phi %struct.TURB* [ %Local_Turb.0.ph24, %bb1096 ] ; <%struct.TURB*> [#uses=0] + ret void +} diff --git a/llvm/test/Transforms/LoopUnswitch/2006-06-27-DeadSwitchCase.ll b/llvm/test/Transforms/LoopUnswitch/2006-06-27-DeadSwitchCase.ll new file mode 100644 index 00000000000..65170b5957b --- /dev/null +++ b/llvm/test/Transforms/LoopUnswitch/2006-06-27-DeadSwitchCase.ll @@ -0,0 +1,26 @@ +; RUN: opt < %s -loop-unswitch -disable-output +; RUN: opt < %s -loop-unswitch -enable-mssa-loop-dependency=true -verify-memoryssa -disable-output + +define void @init_caller_save() { +entry: + br label %cond_true78 +cond_next20: ; preds = %cond_true64 + br label %bb31 +bb31: ; preds = %cond_true64, %cond_true64, %cond_next20 + %iftmp.29.1 = phi i32 [ 0, %cond_next20 ], [ 0, %cond_true64 ], [ 0, %cond_true64 ] ; <i32> [#uses=0] + br label %bb54 +bb54: ; preds = %cond_true78, %bb31 + br i1 false, label %bb75, label %cond_true64 +cond_true64: ; preds = %bb54 + switch i32 %i.0.0, label %cond_next20 [ + i32 17, label %bb31 + i32 18, label %bb31 + ] +bb75: ; preds = %bb54 + %tmp74.0 = add i32 %i.0.0, 1 ; <i32> [#uses=1] + br label %cond_true78 +cond_true78: ; preds = %bb75, %entry + %i.0.0 = phi i32 [ 0, %entry ], [ %tmp74.0, %bb75 ] ; <i32> [#uses=2] + br label %bb54 +} + diff --git a/llvm/test/Transforms/LoopUnswitch/2007-05-09-Unreachable.ll b/llvm/test/Transforms/LoopUnswitch/2007-05-09-Unreachable.ll new file mode 100644 index 00000000000..05f6b8075e1 --- /dev/null +++ b/llvm/test/Transforms/LoopUnswitch/2007-05-09-Unreachable.ll @@ -0,0 +1,29 @@ +; PR1333 +; RUN: opt < %s -loop-unswitch -disable-output +; RUN: opt < %s -loop-unswitch -enable-mssa-loop-dependency=true -verify-memoryssa -disable-output + +target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64" +target triple = "i686-pc-linux-gnu" + %struct.ada__streams__root_stream_type = type { %struct.ada__tags__dispatch_table* } + %struct.ada__tags__dispatch_table = type { [1 x i8*] } + %struct.quotes__T173s = type { i8, %struct.quotes__T173s__T174s, [2 x [1 x double]], [2 x i16], i64, i8 } + %struct.quotes__T173s__T174s = type { i8, i8, i8, i16, i16, [2 x [1 x double]] } + +define void @quotes__write_quote() { +entry: + %tmp606.i = icmp eq i32 0, 0 ; <i1> [#uses=1] + br label %bb +bb: ; preds = %cond_next73, %bb, %entry + br i1 false, label %bb51, label %bb +bb51: ; preds = %cond_next73, %bb + br i1 %tmp606.i, label %quotes__bid_ask_depth_offset_matrices__get_price.exit, label %cond_true.i +cond_true.i: ; preds = %bb51 + unreachable +quotes__bid_ask_depth_offset_matrices__get_price.exit: ; preds = %bb51 + br i1 false, label %cond_next73, label %cond_true72 +cond_true72: ; preds = %quotes__bid_ask_depth_offset_matrices__get_price.exit + unreachable +cond_next73: ; preds = %quotes__bid_ask_depth_offset_matrices__get_price.exit + br i1 false, label %bb, label %bb51 +} + diff --git a/llvm/test/Transforms/LoopUnswitch/2007-05-09-tl.ll b/llvm/test/Transforms/LoopUnswitch/2007-05-09-tl.ll new file mode 100644 index 00000000000..75171d43a93 --- /dev/null +++ b/llvm/test/Transforms/LoopUnswitch/2007-05-09-tl.ll @@ -0,0 +1,96 @@ +; RUN: opt < %s -loop-unswitch -disable-output +; RUN: opt < %s -loop-unswitch -enable-mssa-loop-dependency=true -verify-memoryssa -disable-output +; PR1333 + +define void @pp_cxx_expression() { +entry: + %tmp6 = lshr i32 0, 24 ; <i32> [#uses=1] + br label %tailrecurse + +tailrecurse: ; preds = %tailrecurse, %tailrecurse, %entry + switch i32 %tmp6, label %bb96 [ + i32 24, label %bb10 + i32 25, label %bb10 + i32 28, label %bb10 + i32 29, label %bb48 + i32 31, label %bb48 + i32 32, label %bb48 + i32 33, label %bb48 + i32 34, label %bb48 + i32 36, label %bb15 + i32 51, label %bb89 + i32 52, label %bb89 + i32 54, label %bb83 + i32 57, label %bb59 + i32 63, label %bb80 + i32 64, label %bb80 + i32 68, label %bb80 + i32 169, label %bb75 + i32 170, label %bb19 + i32 171, label %bb63 + i32 172, label %bb63 + i32 173, label %bb67 + i32 174, label %bb67 + i32 175, label %bb19 + i32 176, label %bb75 + i32 178, label %bb59 + i32 179, label %bb89 + i32 180, label %bb59 + i32 182, label %bb48 + i32 183, label %bb48 + i32 184, label %bb48 + i32 185, label %bb48 + i32 186, label %bb48 + i32 195, label %bb48 + i32 196, label %bb59 + i32 197, label %bb89 + i32 198, label %bb70 + i32 199, label %bb59 + i32 200, label %bb59 + i32 201, label %bb59 + i32 202, label %bb59 + i32 203, label %bb75 + i32 204, label %bb59 + i32 205, label %tailrecurse + i32 210, label %tailrecurse + ] + +bb10: ; preds = %tailrecurse, %tailrecurse, %tailrecurse + ret void + +bb15: ; preds = %tailrecurse + ret void + +bb19: ; preds = %tailrecurse, %tailrecurse + ret void + +bb48: ; preds = %tailrecurse, %tailrecurse, %tailrecurse, %tailrecurse, %tailrecurse, %tailrecurse, %tailrecurse, %tailrecurse, %tailrecurse, %tailrecurse, %tailrecurse + ret void + +bb59: ; preds = %tailrecurse, %tailrecurse, %tailrecurse, %tailrecurse, %tailrecurse, %tailrecurse, %tailrecurse, %tailrecurse, %tailrecurse + ret void + +bb63: ; preds = %tailrecurse, %tailrecurse + ret void + +bb67: ; preds = %tailrecurse, %tailrecurse + ret void + +bb70: ; preds = %tailrecurse + ret void + +bb75: ; preds = %tailrecurse, %tailrecurse, %tailrecurse + ret void + +bb80: ; preds = %tailrecurse, %tailrecurse, %tailrecurse + ret void + +bb83: ; preds = %tailrecurse + ret void + +bb89: ; preds = %tailrecurse, %tailrecurse, %tailrecurse, %tailrecurse + ret void + +bb96: ; preds = %tailrecurse + ret void +} diff --git a/llvm/test/Transforms/LoopUnswitch/2007-07-12-ExitDomInfo.ll b/llvm/test/Transforms/LoopUnswitch/2007-07-12-ExitDomInfo.ll new file mode 100644 index 00000000000..a2da514727b --- /dev/null +++ b/llvm/test/Transforms/LoopUnswitch/2007-07-12-ExitDomInfo.ll @@ -0,0 +1,46 @@ +; RUN: opt < %s -loop-unswitch -instcombine -disable-output +; RUN: opt < %s -loop-unswitch -enable-mssa-loop-dependency=true -verify-memoryssa -instcombine -disable-output + +@str3 = external constant [3 x i8] ; <[3 x i8]*> [#uses=1] + +define i32 @stringSearch_Clib(i32 %count) { +entry: + %ttmp25 = icmp sgt i32 %count, 0 ; <i1> [#uses=1] + br i1 %ttmp25, label %bb36.preheader, label %bb44 + +bb36.preheader: ; preds = %entry + %ttmp33 = icmp slt i32 0, 250 ; <i1> [#uses=1] + br label %bb36.outer + +bb36.outer: ; preds = %bb41, %bb36.preheader + br i1 %ttmp33, label %bb.nph, label %bb41 + +bb.nph: ; preds = %bb36.outer + %ttmp8 = icmp eq i8* null, null ; <i1> [#uses=1] + %ttmp6 = icmp eq i8* null, null ; <i1> [#uses=1] + %tmp31 = call i32 @strcspn( i8* null, i8* getelementptr ([3 x i8], [3 x i8]* @str3, i64 0, i64 0) ) ; <i32> [#uses=1] + br i1 %ttmp8, label %cond_next, label %cond_true + +cond_true: ; preds = %bb.nph + ret i32 0 + +cond_next: ; preds = %bb.nph + br i1 %ttmp6, label %cond_next28, label %cond_true20 + +cond_true20: ; preds = %cond_next + ret i32 0 + +cond_next28: ; preds = %cond_next + %tmp33 = add i32 %tmp31, 0 ; <i32> [#uses=1] + br label %bb41 + +bb41: ; preds = %cond_next28, %bb36.outer + %c.2.lcssa = phi i32 [ 0, %bb36.outer ], [ %tmp33, %cond_next28 ] ; <i32> [#uses=1] + br i1 false, label %bb36.outer, label %bb44 + +bb44: ; preds = %bb41, %entry + %c.01.1 = phi i32 [ 0, %entry ], [ %c.2.lcssa, %bb41 ] ; <i32> [#uses=1] + ret i32 %c.01.1 +} + +declare i32 @strcspn(i8*, i8*) diff --git a/llvm/test/Transforms/LoopUnswitch/2007-07-13-DomInfo.ll b/llvm/test/Transforms/LoopUnswitch/2007-07-13-DomInfo.ll new file mode 100644 index 00000000000..6b837d8ee06 --- /dev/null +++ b/llvm/test/Transforms/LoopUnswitch/2007-07-13-DomInfo.ll @@ -0,0 +1,28 @@ +; RUN: opt < %s -loop-unswitch -disable-output +; RUN: opt < %s -loop-unswitch -enable-mssa-loop-dependency=true -verify-memoryssa -disable-output + +define i32 @main(i32 %argc, i8** %argv) { +entry: + %tmp1785365 = icmp ult i32 0, 100 ; <i1> [#uses=1] + br label %bb + +bb: ; preds = %cond_true, %entry + br i1 false, label %cond_true, label %cond_next + +cond_true: ; preds = %bb + br i1 %tmp1785365, label %bb, label %bb1788 + +cond_next: ; preds = %bb + %iftmp.1.0 = select i1 false, i32 0, i32 0 ; <i32> [#uses=1] + br i1 false, label %cond_true47, label %cond_next74 + +cond_true47: ; preds = %cond_next + %tmp53 = urem i32 %iftmp.1.0, 0 ; <i32> [#uses=0] + ret i32 0 + +cond_next74: ; preds = %cond_next + ret i32 0 + +bb1788: ; preds = %cond_true + ret i32 0 +} diff --git a/llvm/test/Transforms/LoopUnswitch/2007-07-18-DomInfo.ll b/llvm/test/Transforms/LoopUnswitch/2007-07-18-DomInfo.ll new file mode 100644 index 00000000000..6414ef1eb57 --- /dev/null +++ b/llvm/test/Transforms/LoopUnswitch/2007-07-18-DomInfo.ll @@ -0,0 +1,67 @@ +; RUN: opt < %s -loop-unswitch -disable-output +; RUN: opt < %s -loop-unswitch -enable-mssa-loop-dependency=true -verify-memoryssa -disable-output +; PR1559 + +target triple = "i686-pc-linux-gnu" + %struct.re_pattern_buffer = type { i8*, i32, i32, i32, i8*, i8*, i32, i8 } + +define fastcc i32 @byte_regex_compile(i8* %pattern, i32 %size, i32 %syntax, %struct.re_pattern_buffer* %bufp) { +entry: + br i1 false, label %bb147, label %cond_next123 + +cond_next123: ; preds = %entry + ret i32 0 + +bb147: ; preds = %entry + switch i32 0, label %normal_char [ + i32 91, label %bb1734 + i32 92, label %bb5700 + ] + +bb1734: ; preds = %bb147 + br label %bb1855.outer.outer + +cond_true1831: ; preds = %bb1855.outer + br i1 %tmp1837, label %cond_next1844, label %cond_true1840 + +cond_true1840: ; preds = %cond_true1831 + ret i32 0 + +cond_next1844: ; preds = %cond_true1831 + br i1 false, label %bb1855.outer, label %cond_true1849 + +cond_true1849: ; preds = %cond_next1844 + br label %bb1855.outer.outer + +bb1855.outer.outer: ; preds = %cond_true1849, %bb1734 + %b.10.ph.ph = phi i8* [ null, %cond_true1849 ], [ null, %bb1734 ] ; <i8*> [#uses=1] + br label %bb1855.outer + +bb1855.outer: ; preds = %bb1855.outer.outer, %cond_next1844 + %b.10.ph = phi i8* [ null, %cond_next1844 ], [ %b.10.ph.ph, %bb1855.outer.outer ] ; <i8*> [#uses=1] + %tmp1837 = icmp eq i8* null, null ; <i1> [#uses=2] + br i1 false, label %cond_true1831, label %cond_next1915 + +cond_next1915: ; preds = %cond_next1961, %bb1855.outer + store i8* null, i8** null + br i1 %tmp1837, label %cond_next1929, label %cond_true1923 + +cond_true1923: ; preds = %cond_next1915 + ret i32 0 + +cond_next1929: ; preds = %cond_next1915 + br i1 false, label %cond_next1961, label %cond_next2009 + +cond_next1961: ; preds = %cond_next1929 + %tmp1992 = getelementptr i8, i8* %b.10.ph, i32 0 ; <i8*> [#uses=0] + br label %cond_next1915 + +cond_next2009: ; preds = %cond_next1929 + ret i32 0 + +bb5700: ; preds = %bb147 + ret i32 0 + +normal_char: ; preds = %bb147 + ret i32 0 +} diff --git a/llvm/test/Transforms/LoopUnswitch/2007-08-01-Dom.ll b/llvm/test/Transforms/LoopUnswitch/2007-08-01-Dom.ll new file mode 100644 index 00000000000..fc92579933b --- /dev/null +++ b/llvm/test/Transforms/LoopUnswitch/2007-08-01-Dom.ll @@ -0,0 +1,30 @@ +; RUN: opt < %s -licm -loop-unswitch -disable-output +; PR 1589 + + %struct.QBasicAtomic = type { i32 } + +define void @_ZNK5QDate9addMonthsEi(%struct.QBasicAtomic* sret %agg.result, %struct.QBasicAtomic* %this, i32 %nmonths) { +entry: + br label %cond_true90 + +bb16: ; preds = %cond_true90 + br i1 false, label %bb93, label %cond_true90 + +bb45: ; preds = %cond_true90 + br i1 false, label %bb53, label %bb58 + +bb53: ; preds = %bb45 + br i1 false, label %bb93, label %cond_true90 + +bb58: ; preds = %bb45 + store i32 0, i32* null, align 4 + br i1 false, label %cond_true90, label %bb93 + +cond_true90: ; preds = %bb58, %bb53, %bb16, %entry + %nmonths_addr.016.1 = phi i32 [ %nmonths, %entry ], [ 0, %bb16 ], [ 0, %bb53 ], [ %nmonths_addr.016.1, %bb58 ] ; <i32> [#uses=2] + %tmp14 = icmp slt i32 %nmonths_addr.016.1, -11 ; <i1> [#uses=1] + br i1 %tmp14, label %bb16, label %bb45 + +bb93: ; preds = %bb58, %bb53, %bb16 + ret void +} diff --git a/llvm/test/Transforms/LoopUnswitch/2007-08-01-LCSSA.ll b/llvm/test/Transforms/LoopUnswitch/2007-08-01-LCSSA.ll new file mode 100644 index 00000000000..547c633f9da --- /dev/null +++ b/llvm/test/Transforms/LoopUnswitch/2007-08-01-LCSSA.ll @@ -0,0 +1,56 @@ +; RUN: opt < %s -loop-unswitch -instcombine -disable-output +; RUN: opt < %s -loop-unswitch -enable-mssa-loop-dependency=true -verify-memoryssa -instcombine -disable-output + %struct.ClassDef = type { %struct.QByteArray, %struct.QByteArray, %"struct.QList<ArgumentDef>", %"struct.QList<ArgumentDef>", i8, i8, %"struct.QList<ArgumentDef>", %"struct.QList<ArgumentDef>", %"struct.QList<ArgumentDef>", %"struct.QList<ArgumentDef>", %"struct.QList<ArgumentDef>", %"struct.QList<ArgumentDef>", %"struct.QMap<QByteArray,QByteArray>", %"struct.QList<ArgumentDef>", %"struct.QMap<QByteArray,QByteArray>", i32, i32 } + %struct.FILE = type { i32, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, %struct._IO_marker*, %struct.FILE*, i32, i32, i32, i16, i8, [1 x i8], i8*, i64, i8*, i8*, i8*, i8*, i32, i32, [40 x i8] } + %struct.Generator = type { %struct.FILE*, %struct.ClassDef*, %"struct.QList<ArgumentDef>", %struct.QByteArray, %"struct.QList<ArgumentDef>" } + %struct.QBasicAtomic = type { i32 } + %struct.QByteArray = type { %"struct.QByteArray::Data"* } + %"struct.QByteArray::Data" = type { %struct.QBasicAtomic, i32, i32, i8*, [1 x i8] } + %"struct.QList<ArgumentDef>" = type { %"struct.QList<ArgumentDef>::._19" } + %"struct.QList<ArgumentDef>::._19" = type { %struct.QListData } + %struct.QListData = type { %"struct.QListData::Data"* } + %"struct.QListData::Data" = type { %struct.QBasicAtomic, i32, i32, i32, i8, [1 x i8*] } + %"struct.QMap<QByteArray,QByteArray>" = type { %"struct.QMap<QByteArray,QByteArray>::._56" } + %"struct.QMap<QByteArray,QByteArray>::._56" = type { %struct.QMapData* } + %struct.QMapData = type { %struct.QMapData*, [12 x %struct.QMapData*], %struct.QBasicAtomic, i32, i32, i32, i8 } + %struct._IO_marker = type { %struct._IO_marker*, %struct.FILE*, i32 } +@.str9 = external constant [1 x i8] ; <[1 x i8]*> [#uses=1] + +declare i32 @strcmp(i8*, i8*) + +define i32 @_ZN9Generator6strregEPKc(%struct.Generator* %this, i8* %s) { +entry: + %s_addr.0 = select i1 false, i8* getelementptr ([1 x i8], [1 x i8]* @.str9, i32 0, i32 0), i8* %s ; <i8*> [#uses=2] + %tmp122 = icmp eq i8* %s_addr.0, null ; <i1> [#uses=1] + br label %bb184 + +bb55: ; preds = %bb184 + ret i32 0 + +bb88: ; preds = %bb184 + br i1 %tmp122, label %bb154, label %bb128 + +bb128: ; preds = %bb88 + %tmp138 = call i32 @strcmp( i8* null, i8* %s_addr.0 ) ; <i32> [#uses=1] + %iftmp.37.0.in4 = icmp eq i32 %tmp138, 0 ; <i1> [#uses=1] + br i1 %iftmp.37.0.in4, label %bb250, label %bb166 + +bb154: ; preds = %bb88 + br i1 false, label %bb250, label %bb166 + +bb166: ; preds = %bb154, %bb128 + %tmp175 = add i32 %idx.0, 1 ; <i32> [#uses=1] + %tmp177 = add i32 %tmp175, 0 ; <i32> [#uses=1] + %tmp181 = add i32 %tmp177, 0 ; <i32> [#uses=1] + %tmp183 = add i32 %i33.0, 1 ; <i32> [#uses=1] + br label %bb184 + +bb184: ; preds = %bb166, %entry + %i33.0 = phi i32 [ 0, %entry ], [ %tmp183, %bb166 ] ; <i32> [#uses=2] + %idx.0 = phi i32 [ 0, %entry ], [ %tmp181, %bb166 ] ; <i32> [#uses=2] + %tmp49 = icmp slt i32 %i33.0, 0 ; <i1> [#uses=1] + br i1 %tmp49, label %bb88, label %bb55 + +bb250: ; preds = %bb154, %bb128 + ret i32 %idx.0 +} diff --git a/llvm/test/Transforms/LoopUnswitch/2007-10-04-DomFrontier.ll b/llvm/test/Transforms/LoopUnswitch/2007-10-04-DomFrontier.ll new file mode 100644 index 00000000000..efbb7619591 --- /dev/null +++ b/llvm/test/Transforms/LoopUnswitch/2007-10-04-DomFrontier.ll @@ -0,0 +1,29 @@ +; RUN: opt < %s -licm -loop-unroll -disable-output + +@resonant = external global i32 ; <i32*> [#uses=2] + +define void @weightadj() { +entry: + br label %bb + +bb: ; preds = %bb158, %entry + store i32 0, i32* @resonant, align 4 + br i1 false, label %g.exit, label %bb158 + +g.exit: ; preds = %bb68, %bb + br i1 false, label %bb68, label %cond_true + +cond_true: ; preds = %g.exit + store i32 1, i32* @resonant, align 4 + br label %bb68 + +bb68: ; preds = %cond_true, %g.exit + %tmp71 = icmp slt i32 0, 0 ; <i1> [#uses=1] + br i1 %tmp71, label %g.exit, label %bb158 + +bb158: ; preds = %bb68, %bb + br i1 false, label %bb, label %return + +return: ; preds = %bb158 + ret void +} diff --git a/llvm/test/Transforms/LoopUnswitch/2008-06-02-DomInfo.ll b/llvm/test/Transforms/LoopUnswitch/2008-06-02-DomInfo.ll new file mode 100644 index 00000000000..165156657d7 --- /dev/null +++ b/llvm/test/Transforms/LoopUnswitch/2008-06-02-DomInfo.ll @@ -0,0 +1,27 @@ +; RUN: opt < %s -loop-unswitch -instcombine -gvn -disable-output +; RUN: opt < %s -loop-unswitch -instcombine -gvn -enable-mssa-loop-dependency=true -verify-memoryssa -disable-output +; PR2372 +target triple = "i386-pc-linux-gnu" + +define i32 @func_3(i16 signext %p_5, i16 signext %p_6) nounwind { +entry: + %tmp3 = icmp eq i16 %p_5, 0 ; <i1> [#uses=1] + %tmp1314 = sext i16 %p_6 to i32 ; <i32> [#uses=1] + %tmp28 = icmp ugt i32 %tmp1314, 3 ; <i1> [#uses=1] + %bothcond = or i1 %tmp28, false ; <i1> [#uses=1] + br label %bb +bb: ; preds = %bb54, %entry + br i1 %tmp3, label %bb54, label %bb5 +bb5: ; preds = %bb + br i1 %bothcond, label %bb54, label %bb31 +bb31: ; preds = %bb5 + br label %bb54 +bb54: ; preds = %bb31, %bb5, %bb + br i1 false, label %bb64, label %bb +bb64: ; preds = %bb54 + %tmp6566 = sext i16 %p_6 to i32 ; <i32> [#uses=1] + %tmp68 = tail call i32 (...) @func_18( i32 1, i32 %tmp6566, i32 1 ) nounwind ; <i32> [#uses=0] + ret i32 undef +} + +declare i32 @func_18(...) diff --git a/llvm/test/Transforms/LoopUnswitch/2008-06-17-DomFrontier.ll b/llvm/test/Transforms/LoopUnswitch/2008-06-17-DomFrontier.ll new file mode 100644 index 00000000000..d606ea9c6d2 --- /dev/null +++ b/llvm/test/Transforms/LoopUnswitch/2008-06-17-DomFrontier.ll @@ -0,0 +1,22 @@ +; RUN: opt < %s -licm -loop-unswitch -disable-output +@g_56 = external global i16 ; <i16*> [#uses=2] + +define i32 @func_67(i32 %p_68, i8 signext %p_69, i8 signext %p_71) nounwind { +entry: + br label %bb +bb: ; preds = %bb44, %entry + br label %bb3 +bb3: ; preds = %bb36, %bb + %bothcond = or i1 false, false ; <i1> [#uses=1] + br i1 %bothcond, label %bb29, label %bb19 +bb19: ; preds = %bb3 + br i1 false, label %bb36, label %bb29 +bb29: ; preds = %bb19, %bb3 + ret i32 0 +bb36: ; preds = %bb19 + store i16 0, i16* @g_56, align 2 + br i1 false, label %bb44, label %bb3 +bb44: ; preds = %bb44, %bb36 + %tmp46 = load i16, i16* @g_56, align 2 ; <i16> [#uses=0] + br i1 false, label %bb, label %bb44 +} diff --git a/llvm/test/Transforms/LoopUnswitch/2008-11-03-Invariant.ll b/llvm/test/Transforms/LoopUnswitch/2008-11-03-Invariant.ll new file mode 100644 index 00000000000..22d6acde84c --- /dev/null +++ b/llvm/test/Transforms/LoopUnswitch/2008-11-03-Invariant.ll @@ -0,0 +1,42 @@ +; REQUIRES: asserts +; RUN: opt < %s -loop-unswitch -stats -disable-output 2>&1 | FileCheck %s +; RUN: opt < %s -loop-unswitch -enable-mssa-loop-dependency=true -verify-memoryssa -stats -disable-output 2>&1 | FileCheck %s +; PR 3170 + +define i32 @a(i32 %x, i32 %y) nounwind { +; CHECK: 1 loop-unswitch - Number of branches unswitched +; CHECK-NOT: Number of branches unswitched + +entry: + %0 = icmp ult i32 0, %y ; <i1> [#uses=1] + br i1 %0, label %bb.nph, label %bb4 + +bb.nph: ; preds = %entry + %1 = icmp eq i32 %x, 0 ; <i1> [#uses=1] + br label %bb + +bb: ; preds = %bb.nph, %bb3 + %i.01 = phi i32 [ %3, %bb3 ], [ 0, %bb.nph ] ; <i32> [#uses=1] + br i1 %1, label %bb2, label %bb1 + +bb1: ; preds = %bb + %2 = tail call i32 (...) @b() nounwind ; <i32> [#uses=0] + br label %bb2 + +bb2: ; preds = %bb, %bb1 + %3 = add i32 %i.01, 1 ; <i32> [#uses=2] + br label %bb3 + +bb3: ; preds = %bb2 + %i.0 = phi i32 [ %3, %bb2 ] ; <i32> [#uses=1] + %4 = icmp ult i32 %i.0, %y ; <i1> [#uses=1] + br i1 %4, label %bb, label %bb3.bb4_crit_edge + +bb3.bb4_crit_edge: ; preds = %bb3 + br label %bb4 + +bb4: ; preds = %bb3.bb4_crit_edge, %entry + ret i32 0 +} + +declare i32 @b(...) diff --git a/llvm/test/Transforms/LoopUnswitch/2010-11-18-LCSSA.ll b/llvm/test/Transforms/LoopUnswitch/2010-11-18-LCSSA.ll new file mode 100644 index 00000000000..55012720f6b --- /dev/null +++ b/llvm/test/Transforms/LoopUnswitch/2010-11-18-LCSSA.ll @@ -0,0 +1,29 @@ +; RUN: opt < %s -loop-unswitch +; RUN: opt < %s -loop-unswitch -enable-mssa-loop-dependency=true -verify-memoryssa +; PR8622 +@g_38 = external global i32, align 4 + +define void @func_67(i32 %p_68.coerce) nounwind { +entry: + br i1 true, label %for.end12, label %bb.nph + +bb.nph: ; preds = %entry + %g_38.promoted = load i32, i32* @g_38 + br label %for.body + +for.body: ; preds = %for.cond, %bb.nph + %tobool.i = icmp eq i32 %p_68.coerce, 1 + %xor4.i = xor i32 %p_68.coerce, 1 + %call1 = select i1 %tobool.i, i32 0, i32 %xor4.i + br label %for.cond + +for.cond: ; preds = %for.body + br i1 true, label %for.cond.for.end12_crit_edge, label %for.body + +for.cond.for.end12_crit_edge: ; preds = %for.cond + store i32 %call1, i32* @g_38 + br label %for.end12 + +for.end12: ; preds = %for.cond.for.end12_crit_edge, %entry + ret void +} diff --git a/llvm/test/Transforms/LoopUnswitch/2011-06-02-CritSwitch.ll b/llvm/test/Transforms/LoopUnswitch/2011-06-02-CritSwitch.ll new file mode 100644 index 00000000000..609520064a7 --- /dev/null +++ b/llvm/test/Transforms/LoopUnswitch/2011-06-02-CritSwitch.ll @@ -0,0 +1,28 @@ +; RUN: opt -loop-unswitch -disable-output < %s +; PR10031 + +define i32 @test(i32 %command) { +entry: + br label %tailrecurse + +tailrecurse: ; preds = %if.then14, %tailrecurse, %entry + br i1 undef, label %if.then, label %tailrecurse + +if.then: ; preds = %tailrecurse + switch i32 %command, label %sw.bb [ + i32 2, label %land.lhs.true + i32 0, label %land.lhs.true + ] + +land.lhs.true: ; preds = %if.then, %if.then + br i1 undef, label %sw.bb, label %if.then14 + +if.then14: ; preds = %land.lhs.true + switch i32 %command, label %tailrecurse [ + i32 0, label %sw.bb + i32 1, label %sw.bb + ] + +sw.bb: ; preds = %if.then14 + unreachable +} diff --git a/llvm/test/Transforms/LoopUnswitch/2011-09-26-EHCrash.ll b/llvm/test/Transforms/LoopUnswitch/2011-09-26-EHCrash.ll new file mode 100644 index 00000000000..cdb55f57472 --- /dev/null +++ b/llvm/test/Transforms/LoopUnswitch/2011-09-26-EHCrash.ll @@ -0,0 +1,64 @@ +; RUN: opt < %s -sroa -loop-unswitch -disable-output +; RUN: opt < %s -sroa -loop-unswitch -enable-mssa-loop-dependency=true -verify-memoryssa -disable-output +; PR11016 +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" +target triple = "x86_64-apple-macosx10.7.2" + +%class.MyContainer.1.3.19.29 = type { [6 x %class.MyMemVarClass.0.2.18.28*] } +%class.MyMemVarClass.0.2.18.28 = type { i32 } + +define void @_ZN11MyContainer1fEi(%class.MyContainer.1.3.19.29* %this, i32 %doit) uwtable ssp align 2 personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +entry: + br label %for.cond + +for.cond: ; preds = %for.inc, %entry + %inc1 = phi i32 [ %inc, %for.inc ], [ 0, %entry ] + %conv = sext i32 %inc1 to i64 + %cmp = icmp ult i64 %conv, 6 + br i1 %cmp, label %for.body, label %for.end + +for.body: ; preds = %for.cond + %tobool = icmp ne i32 %doit, 0 + br i1 %tobool, label %for.inc, label %if.then + +if.then: ; preds = %for.body + %idxprom = sext i32 %inc1 to i64 + %array_ = getelementptr inbounds %class.MyContainer.1.3.19.29, %class.MyContainer.1.3.19.29* %this, i32 0, i32 0 + %arrayidx = getelementptr inbounds [6 x %class.MyMemVarClass.0.2.18.28*], [6 x %class.MyMemVarClass.0.2.18.28*]* %array_, i32 0, i64 %idxprom + %tmp4 = load %class.MyMemVarClass.0.2.18.28*, %class.MyMemVarClass.0.2.18.28** %arrayidx, align 8 + %isnull = icmp eq %class.MyMemVarClass.0.2.18.28* %tmp4, null + br i1 %isnull, label %for.inc, label %delete.notnull + +delete.notnull: ; preds = %if.then + invoke void @_ZN13MyMemVarClassD1Ev(%class.MyMemVarClass.0.2.18.28* %tmp4) + to label %invoke.cont unwind label %lpad + +invoke.cont: ; preds = %delete.notnull + %0 = bitcast %class.MyMemVarClass.0.2.18.28* %tmp4 to i8* + call void @_ZdlPv(i8* %0) nounwind + br label %for.inc + +lpad: ; preds = %delete.notnull + %1 = landingpad { i8*, i32 } + cleanup + %2 = extractvalue { i8*, i32 } %1, 0 + %3 = extractvalue { i8*, i32 } %1, 1 + %4 = bitcast %class.MyMemVarClass.0.2.18.28* %tmp4 to i8* + call void @_ZdlPv(i8* %4) nounwind + %lpad.val = insertvalue { i8*, i32 } undef, i8* %2, 0 + %lpad.val7 = insertvalue { i8*, i32 } %lpad.val, i32 %3, 1 + resume { i8*, i32 } %lpad.val7 + +for.inc: ; preds = %invoke.cont, %if.then, %for.body + %inc = add nsw i32 %inc1, 1 + br label %for.cond + +for.end: ; preds = %for.cond + ret void +} + +declare void @_ZN13MyMemVarClassD1Ev(%class.MyMemVarClass.0.2.18.28*) + +declare i32 @__gxx_personality_v0(...) + +declare void @_ZdlPv(i8*) nounwind diff --git a/llvm/test/Transforms/LoopUnswitch/2011-11-18-SimpleSwitch.ll b/llvm/test/Transforms/LoopUnswitch/2011-11-18-SimpleSwitch.ll new file mode 100644 index 00000000000..2db66aca089 --- /dev/null +++ b/llvm/test/Transforms/LoopUnswitch/2011-11-18-SimpleSwitch.ll @@ -0,0 +1,95 @@ +; REQUIRES: asserts +; RUN: opt -loop-unswitch -disable-output -stats -info-output-file - < %s | FileCheck --check-prefix=STATS %s +; RUN: opt -S -loop-unswitch -verify-loop-info -verify-dom-info < %s | FileCheck %s +; RUN: opt -S -loop-unswitch -verify-loop-info -verify-dom-info -enable-mssa-loop-dependency=true -verify-memoryssa < %s | FileCheck %s + +; STATS: 2 loop-unswitch - Number of switches unswitched + +; CHECK: %1 = icmp eq i32 %c, 1 +; CHECK-NEXT: br i1 %1, label %.split.us, label %..split_crit_edge + +; CHECK: ..split_crit_edge: ; preds = %0 +; CHECK-NEXT: br label %.split + +; CHECK: .split.us: ; preds = %0 +; CHECK-NEXT: br label %loop_begin.us + +; CHECK: loop_begin.us: ; preds = %loop_begin.backedge.us, %.split.us +; CHECK-NEXT: %var_val.us = load i32, i32* %var +; CHECK-NEXT: switch i32 1, label %default.us-lcssa.us [ +; CHECK-NEXT: i32 1, label %inc.us + +; CHECK: inc.us: ; preds = %loop_begin.us +; CHECK-NEXT: call void @incf() [[NOR_NUW:#[0-9]+]] +; CHECK-NEXT: br label %loop_begin.backedge.us + +; CHECK: .split: ; preds = %..split_crit_edge +; CHECK-NEXT: %2 = icmp eq i32 %c, 2 +; CHECK-NEXT: br i1 %2, label %.split.split.us, label %.split..split.split_crit_edge + +; CHECK: .split..split.split_crit_edge: ; preds = %.split +; CHECK-NEXT: br label %.split.split + +; CHECK: .split.split.us: ; preds = %.split +; CHECK-NEXT: br label %loop_begin.us1 + +; CHECK: loop_begin.us1: ; preds = %loop_begin.backedge.us5, %.split.split.us +; CHECK-NEXT: %var_val.us2 = load i32, i32* %var +; CHECK-NEXT: switch i32 2, label %default.us-lcssa.us-lcssa.us [ +; CHECK-NEXT: i32 1, label %inc.us4 +; CHECK-NEXT: i32 2, label %dec.us3 +; CHECK-NEXT: ] + +; CHECK: dec.us3: ; preds = %loop_begin.us1 +; CHECK-NEXT: call void @decf() [[NOR_NUW]] +; CHECK-NEXT: br label %loop_begin.backedge.us5 + +; CHECK: .split.split: ; preds = %.split..split.split_crit_edge +; CHECK-NEXT: br label %loop_begin + +; CHECK: loop_begin: ; preds = %loop_begin.backedge, %.split.split +; CHECK-NEXT: %var_val = load i32, i32* %var +; CHECK-NEXT: switch i32 %c, label %default.us-lcssa.us-lcssa [ +; CHECK-NEXT: i32 1, label %inc +; CHECK-NEXT: i32 2, label %dec +; CHECK-NEXT: ] + +; CHECK: inc: ; preds = %loop_begin +; CHECK-NEXT: br i1 true, label %us-unreachable.us-lcssa, label %inc.split + +; CHECK: dec: ; preds = %loop_begin +; CHECK-NEXT: br i1 true, label %us-unreachable6, label %dec.split + +define i32 @test(i32* %var) { + %mem = alloca i32 + store i32 2, i32* %mem + %c = load i32, i32* %mem + + br label %loop_begin + +loop_begin: + + %var_val = load i32, i32* %var + + switch i32 %c, label %default [ + i32 1, label %inc + i32 2, label %dec + ] + +inc: + call void @incf() noreturn nounwind + br label %loop_begin +dec: + call void @decf() noreturn nounwind + br label %loop_begin +default: + br label %loop_exit +loop_exit: + ret i32 0 +} + +declare void @incf() noreturn +declare void @decf() noreturn + +; CHECK: attributes #0 = { noreturn } +; CHECK: attributes [[NOR_NUW]] = { noreturn nounwind } diff --git a/llvm/test/Transforms/LoopUnswitch/2011-11-18-TwoSwitches-Threshold.ll b/llvm/test/Transforms/LoopUnswitch/2011-11-18-TwoSwitches-Threshold.ll new file mode 100644 index 00000000000..012916cc243 --- /dev/null +++ b/llvm/test/Transforms/LoopUnswitch/2011-11-18-TwoSwitches-Threshold.ll @@ -0,0 +1,88 @@ +; REQUIRES: asserts +; RUN: opt -loop-unswitch -loop-unswitch-threshold 13 -disable-output -stats -info-output-file - < %s | FileCheck --check-prefix=STATS %s +; RUN: opt -S -loop-unswitch -loop-unswitch-threshold 13 -verify-loop-info -verify-dom-info < %s | FileCheck %s +; RUN: opt -S -loop-unswitch -loop-unswitch-threshold 13 -verify-loop-info -verify-dom-info -enable-mssa-loop-dependency=true -verify-memoryssa < %s | FileCheck %s + +; STATS: 1 loop-unswitch - Number of switches unswitched + +; ModuleID = '../llvm/test/Transforms/LoopUnswitch/2011-11-18-TwoSwitches.ll' + +; CHECK: %1 = icmp eq i32 %c, 1 +; CHECK-NEXT: br i1 %1, label %.split.us, label %..split_crit_edge + +; CHECK: ..split_crit_edge: ; preds = %0 +; CHECK-NEXT: br label %.split + +; CHECK: .split.us: ; preds = %0 +; CHECK-NEXT: br label %loop_begin.us + +; CHECK: loop_begin.us: ; preds = %loop_begin.backedge.us, %.split.us +; CHECK: switch i32 1, label %second_switch.us [ +; CHECK-NEXT: i32 1, label %inc.us + +; CHECK: second_switch.us: ; preds = %loop_begin.us +; CHECK-NEXT: switch i32 %d, label %default.us [ +; CHECK-NEXT: i32 1, label %inc.us +; CHECK-NEXT: ] + +; CHECK: inc.us: ; preds = %second_switch.us, %loop_begin.us +; CHECK-NEXT: call void @incf() [[NOR_NUW:#[0-9]+]] +; CHECK-NEXT: br label %loop_begin.backedge.us + +; CHECK: .split: ; preds = %..split_crit_edge +; CHECK-NEXT: br label %loop_begin + +; CHECK: loop_begin: ; preds = %loop_begin.backedge, %.split +; CHECK: switch i32 %c, label %second_switch [ +; CHECK-NEXT: i32 1, label %loop_begin.inc_crit_edge +; CHECK-NEXT: ] + +; CHECK: loop_begin.inc_crit_edge: ; preds = %loop_begin +; CHECK-NEXT: br i1 true, label %us-unreachable, label %inc + +; CHECK: second_switch: ; preds = %loop_begin +; CHECK-NEXT: switch i32 %d, label %default [ +; CHECK-NEXT: i32 1, label %inc +; CHECK-NEXT: ] + +; CHECK: inc: ; preds = %loop_begin.inc_crit_edge, %second_switch +; CHECK-NEXT: call void @incf() [[NOR_NUW]] +; CHECK-NEXT: br label %loop_begin.backedge + +define i32 @test(i32* %var) { + %mem = alloca i32 + store i32 2, i32* %mem + %c = load i32, i32* %mem + %d = load i32, i32* %mem + + br label %loop_begin + +loop_begin: + + %var_val = load i32, i32* %var + + switch i32 %c, label %second_switch [ + i32 1, label %inc + ] + +second_switch: + switch i32 %d, label %default [ + i32 1, label %inc + ] + +inc: + call void @incf() noreturn nounwind + br label %loop_begin + +default: + br label %loop_begin + +loop_exit: + ret i32 0 +} + +declare void @incf() noreturn +declare void @decf() noreturn + +; CHECK: attributes #0 = { noreturn } +; CHECK: attributes [[NOR_NUW]] = { noreturn nounwind } diff --git a/llvm/test/Transforms/LoopUnswitch/2011-11-18-TwoSwitches.ll b/llvm/test/Transforms/LoopUnswitch/2011-11-18-TwoSwitches.ll new file mode 100644 index 00000000000..04852034225 --- /dev/null +++ b/llvm/test/Transforms/LoopUnswitch/2011-11-18-TwoSwitches.ll @@ -0,0 +1,142 @@ +; REQUIRES: asserts +; RUN: opt -loop-unswitch -loop-unswitch-threshold 1000 -disable-output -stats -info-output-file - < %s | FileCheck --check-prefix=STATS %s +; RUN: opt -S -loop-unswitch -loop-unswitch-threshold 1000 -verify-loop-info -verify-dom-info < %s | FileCheck %s +; RUN: opt -S -loop-unswitch -loop-unswitch-threshold 1000 -verify-loop-info -verify-dom-info -enable-mssa-loop-dependency=true -verify-memoryssa < %s | FileCheck %s + +; STATS: 3 loop-unswitch - Number of switches unswitched + +; CHECK: %1 = icmp eq i32 %c, 1 +; CHECK-NEXT: br i1 %1, label %.split.us, label %..split_crit_edge + +; CHECK: ..split_crit_edge: ; preds = %0 +; CHECK-NEXT: br label %.split + +; CHECK: .split.us: ; preds = %0 +; CHECK-NEXT: %2 = icmp eq i32 %d, 1 +; CHECK-NEXT: br i1 %2, label %.split.us.split.us, label %.split.us..split.us.split_crit_edge + +; CHECK: .split.us..split.us.split_crit_edge: ; preds = %.split.us +; CHECK-NEXT: br label %.split.us.split + +; CHECK: .split.us.split.us: ; preds = %.split.us +; CHECK-NEXT: br label %loop_begin.us.us + +; CHECK: loop_begin.us.us: ; preds = %loop_begin.backedge.us.us, %.split.us.split.us +; CHECK-NEXT: %var_val.us.us = load i32, i32* %var +; CHECK-NEXT: switch i32 1, label %second_switch.us.us [ +; CHECK-NEXT: i32 1, label %inc.us.us + +; CHECK: second_switch.us.us: ; preds = %loop_begin.us.us +; CHECK-NEXT: switch i32 1, label %default.us.us [ +; CHECK-NEXT: i32 1, label %inc.us.us + +; CHECK: inc.us.us: ; preds = %second_switch.us.us, %loop_begin.us.us +; CHECK-NEXT: call void @incf() [[NOR_NUW:#[0-9]+]] +; CHECK-NEXT: br label %loop_begin.backedge.us.us + +; CHECK: .split.us.split: ; preds = %.split.us..split.us.split_crit_edge +; CHECK-NEXT: br label %loop_begin.us + +; CHECK: loop_begin.us: ; preds = %loop_begin.backedge.us, %.split.us.split +; CHECK-NEXT: %var_val.us = load i32, i32* %var +; CHECK-NEXT: switch i32 1, label %second_switch.us [ +; CHECK-NEXT: i32 1, label %inc.us + +; CHECK: second_switch.us: ; preds = %loop_begin.us +; CHECK-NEXT: switch i32 %d, label %default.us [ +; CHECK-NEXT: i32 1, label %second_switch.us.inc.us_crit_edge +; CHECK-NEXT: ] + +; CHECK: second_switch.us.inc.us_crit_edge: ; preds = %second_switch.us +; CHECK-NEXT: br i1 true, label %us-unreachable8, label %inc.us + +; CHECK: inc.us: ; preds = %second_switch.us.inc.us_crit_edge, %loop_begin.us +; CHECK-NEXT: call void @incf() [[NOR_NUW]] +; CHECK-NEXT: br label %loop_begin.backedge.us + +; CHECK: .split: ; preds = %..split_crit_edge +; CHECK-NEXT: %3 = icmp eq i32 %d, 1 +; CHECK-NEXT: br i1 %3, label %.split.split.us, label %.split..split.split_crit_edge + +; CHECK: .split..split.split_crit_edge: ; preds = %.split +; CHECK-NEXT: br label %.split.split + +; CHECK: .split.split.us: ; preds = %.split +; CHECK-NEXT: br label %loop_begin.us1 + +; CHECK: loop_begin.us1: ; preds = %loop_begin.backedge.us6, %.split.split.us +; CHECK-NEXT: %var_val.us2 = load i32, i32* %var +; CHECK-NEXT: switch i32 %c, label %second_switch.us3 [ +; CHECK-NEXT: i32 1, label %loop_begin.inc_crit_edge.us +; CHECK-NEXT: ] + +; CHECK: second_switch.us3: ; preds = %loop_begin.us1 +; CHECK-NEXT: switch i32 1, label %default.us5 [ +; CHECK-NEXT: i32 1, label %inc.us4 +; CHECK-NEXT: ] + +; CHECK: inc.us4: ; preds = %loop_begin.inc_crit_edge.us, %second_switch.us3 +; CHECK-NEXT: call void @incf() [[NOR_NUW]] +; CHECK-NEXT: br label %loop_begin.backedge.us6 + +; CHECK: loop_begin.inc_crit_edge.us: ; preds = %loop_begin.us1 +; CHECK-NEXT: br i1 true, label %us-unreachable.us-lcssa.us, label %inc.us4 + +; CHECK: .split.split: ; preds = %.split..split.split_crit_edge +; CHECK-NEXT: br label %loop_begin + +; CHECK: loop_begin: ; preds = %loop_begin.backedge, %.split.split +; CHECK-NEXT: %var_val = load i32, i32* %var +; CHECK-NEXT: switch i32 %c, label %second_switch [ +; CHECK-NEXT: i32 1, label %loop_begin.inc_crit_edge +; CHECK-NEXT: ] + +; CHECK: loop_begin.inc_crit_edge: ; preds = %loop_begin +; CHECK-NEXT: br i1 true, label %us-unreachable.us-lcssa, label %inc + +; CHECK: second_switch: ; preds = %loop_begin +; CHECK-NEXT: switch i32 %d, label %default [ +; CHECK-NEXT: i32 1, label %second_switch.inc_crit_edge +; CHECK-NEXT: ] + +; CHECK: second_switch.inc_crit_edge: ; preds = %second_switch +; CHECK-NEXT: br i1 true, label %us-unreachable7, label %inc + + +define i32 @test(i32* %var) { + %mem = alloca i32 + store i32 2, i32* %mem + %c = load i32, i32* %mem + %d = load i32, i32* %mem + + br label %loop_begin + +loop_begin: + + %var_val = load i32, i32* %var + + switch i32 %c, label %second_switch [ + i32 1, label %inc + ] + +second_switch: + switch i32 %d, label %default [ + i32 1, label %inc + ] + +inc: + call void @incf() noreturn nounwind + br label %loop_begin + +default: + br label %loop_begin + +loop_exit: + ret i32 0 +} + +declare void @incf() noreturn +declare void @decf() noreturn + +; CHECK: attributes #0 = { noreturn } +; CHECK: attributes [[NOR_NUW]] = { noreturn nounwind } diff --git a/llvm/test/Transforms/LoopUnswitch/2012-04-02-IndirectBr.ll b/llvm/test/Transforms/LoopUnswitch/2012-04-02-IndirectBr.ll new file mode 100644 index 00000000000..8ccf4452388 --- /dev/null +++ b/llvm/test/Transforms/LoopUnswitch/2012-04-02-IndirectBr.ll @@ -0,0 +1,42 @@ +; RUN: opt < %s -S -loop-unswitch -verify-loop-info -verify-dom-info | FileCheck %s +; RUN: opt < %s -S -loop-unswitch -verify-loop-info -verify-dom-info -enable-mssa-loop-dependency=true -verify-memoryssa | FileCheck %s +; PR12343: -loop-unswitch crash on indirect branch + +; CHECK: %0 = icmp eq i64 undef, 0 +; CHECK-NEXT: br i1 %0, label %"5", label %"4" + +; CHECK: "5": ; preds = %entry +; CHECK-NEXT: br label %"16" + +; CHECK: "16": ; preds = %"22", %"5" +; CHECK-NEXT: indirectbr i8* undef, [label %"22", label %"33"] + +; CHECK: "22": ; preds = %"16" +; CHECK-NEXT: br i1 %0, label %"16", label %"26" + +; CHECK: "26": ; preds = %"22" +; CHECK-NEXT: unreachable + +define void @foo() { +entry: + %0 = icmp eq i64 undef, 0 + br i1 %0, label %"5", label %"4" + +"4": ; preds = %entry + unreachable + +"5": ; preds = %entry + br label %"16" + +"16": ; preds = %"22", %"5" + indirectbr i8* undef, [label %"22", label %"33"] + +"22": ; preds = %"16" + br i1 %0, label %"16", label %"26" + +"26": ; preds = %"22" + unreachable + +"33": ; preds = %"16" + unreachable +} diff --git a/llvm/test/Transforms/LoopUnswitch/2012-04-30-LoopUnswitch-LPad-Crash.ll b/llvm/test/Transforms/LoopUnswitch/2012-04-30-LoopUnswitch-LPad-Crash.ll new file mode 100644 index 00000000000..2c1847a545b --- /dev/null +++ b/llvm/test/Transforms/LoopUnswitch/2012-04-30-LoopUnswitch-LPad-Crash.ll @@ -0,0 +1,97 @@ +; RUN: opt < %s -basicaa -instcombine -inline -functionattrs -licm -loop-unswitch -gvn -verify +; PR12573 +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" +target triple = "x86_64-apple-macosx10.7.0" + +%class.D.22.42.66.102.138.158.178.198.238.242.246.250.262.294.302.338.346.379 = type { %class.C.23.43.67.103.139.159.179.199.239.243.247.251.263.295.303.339.347.376*, %class.B.21.41.65.101.137.157.177.197.237.241.245.249.261.293.301.337.345.378 } +%class.C.23.43.67.103.139.159.179.199.239.243.247.251.263.295.303.339.347.376 = type { %class.D.22.42.66.102.138.158.178.198.238.242.246.250.262.294.302.338.346.379* } +%class.B.21.41.65.101.137.157.177.197.237.241.245.249.261.293.301.337.345.378 = type { %class.A.20.40.64.100.136.156.176.196.236.240.244.248.260.292.300.336.344.377* } +%class.A.20.40.64.100.136.156.176.196.236.240.244.248.260.292.300.336.344.377 = type { i8 } + +define void @_Z23get_reconstruction_pathv() uwtable ssp personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +entry: + %c = alloca %class.D.22.42.66.102.138.158.178.198.238.242.246.250.262.294.302.338.346.379, align 8 + br label %for.cond + +for.cond: ; preds = %for.end, %entry + invoke void @_ZN1DptEv(%class.D.22.42.66.102.138.158.178.198.238.242.246.250.262.294.302.338.346.379* %c) + to label %invoke.cont unwind label %lpad + +invoke.cont: ; preds = %for.cond + invoke void @_ZN1C3endEv() + to label %for.cond3 unwind label %lpad + +for.cond3: ; preds = %invoke.cont6, %invoke.cont + invoke void @_ZN1DptEv(%class.D.22.42.66.102.138.158.178.198.238.242.246.250.262.294.302.338.346.379* %c) + to label %invoke.cont4 unwind label %lpad + +invoke.cont4: ; preds = %for.cond3 + invoke void @_ZN1C3endEv() + to label %invoke.cont6 unwind label %lpad + +invoke.cont6: ; preds = %invoke.cont4 + br i1 undef, label %for.cond3, label %for.end + +lpad: ; preds = %for.end, %invoke.cont4, %for.cond3, %invoke.cont, %for.cond + %0 = landingpad { i8*, i32 } + cleanup + resume { i8*, i32 } undef + +for.end: ; preds = %invoke.cont6 + invoke void @_ZN1C13_M_insert_auxER1D() + to label %for.cond unwind label %lpad +} + +define void @_ZN1DptEv(%class.D.22.42.66.102.138.158.178.198.238.242.246.250.262.294.302.338.346.379* %this) uwtable ssp align 2 { +entry: + %this.addr = alloca %class.D.22.42.66.102.138.158.178.198.238.242.246.250.262.294.302.338.346.379*, align 8 + store %class.D.22.42.66.102.138.158.178.198.238.242.246.250.262.294.302.338.346.379* %this, %class.D.22.42.66.102.138.158.178.198.238.242.246.250.262.294.302.338.346.379** %this.addr, align 8 + %this1 = load %class.D.22.42.66.102.138.158.178.198.238.242.246.250.262.294.302.338.346.379*, %class.D.22.42.66.102.138.158.178.198.238.242.246.250.262.294.302.338.346.379** %this.addr + %px = getelementptr inbounds %class.D.22.42.66.102.138.158.178.198.238.242.246.250.262.294.302.338.346.379, %class.D.22.42.66.102.138.158.178.198.238.242.246.250.262.294.302.338.346.379* %this1, i32 0, i32 0 + %0 = load %class.C.23.43.67.103.139.159.179.199.239.243.247.251.263.295.303.339.347.376*, %class.C.23.43.67.103.139.159.179.199.239.243.247.251.263.295.303.339.347.376** %px, align 8 + %tobool = icmp ne %class.C.23.43.67.103.139.159.179.199.239.243.247.251.263.295.303.339.347.376* %0, null + br i1 %tobool, label %cond.end, label %cond.false + +cond.false: ; preds = %entry + call void @_Z10__assert13v() noreturn + unreachable + +cond.end: ; preds = %entry + ret void +} + +declare i32 @__gxx_personality_v0(...) + +declare void @_ZN1C3endEv() + +define void @_ZN1C13_M_insert_auxER1D() uwtable ssp align 2 { +entry: + ret void +} + +define void @_ZN1DD1Ev() unnamed_addr uwtable inlinehint ssp align 2 { +entry: + ret void +} + +define void @_ZN1DD2Ev() unnamed_addr uwtable inlinehint ssp align 2 { +entry: + ret void +} + +define void @_ZN1BD1Ev() unnamed_addr uwtable ssp align 2 { +entry: + ret void +} + +define void @_ZN1BD2Ev() unnamed_addr uwtable ssp align 2 { +entry: + ret void +} + +define void @_ZN1BaSERS_() uwtable ssp align 2 { +entry: + unreachable +} + +declare void @_Z10__assert13v() noreturn diff --git a/llvm/test/Transforms/LoopUnswitch/2012-05-20-Phi.ll b/llvm/test/Transforms/LoopUnswitch/2012-05-20-Phi.ll new file mode 100644 index 00000000000..f5e6af9db38 --- /dev/null +++ b/llvm/test/Transforms/LoopUnswitch/2012-05-20-Phi.ll @@ -0,0 +1,26 @@ +; RUN: opt < %s -loop-unswitch -disable-output +; RUN: opt < %s -loop-unswitch -enable-mssa-loop-dependency=true -verify-memoryssa -disable-output +; PR12887 +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" +target triple = "x86_64-unknown-linux-gnu" + +@a = common global i32 0, align 4 +@c = common global i32 0, align 4 +@b = common global i32 0, align 4 + +define void @func() noreturn nounwind uwtable { +entry: + %0 = load i32, i32* @a, align 4 + %tobool = icmp eq i32 %0, 0 + %1 = load i32, i32* @b, align 4 + br label %while.body + +while.body: ; preds = %while.body, %entry + %d.0 = phi i8 [ undef, %entry ], [ %conv2, %while.body ] + %conv = sext i8 %d.0 to i32 + %cond = select i1 %tobool, i32 0, i32 %conv + %conv11 = zext i8 %d.0 to i32 + %add = add i32 %1, %conv11 + %conv2 = trunc i32 %add to i8 + br label %while.body +} diff --git a/llvm/test/Transforms/LoopUnswitch/2015-06-17-Metadata.ll b/llvm/test/Transforms/LoopUnswitch/2015-06-17-Metadata.ll new file mode 100644 index 00000000000..a215be9d487 --- /dev/null +++ b/llvm/test/Transforms/LoopUnswitch/2015-06-17-Metadata.ll @@ -0,0 +1,77 @@ +;RUN: opt -loop-unswitch -simplifycfg -S < %s | FileCheck %s + +define i32 @foo(i32 %a, i32 %b) { +;CHECK-LABEL: foo +entry: + br label %for.body.lr.ph + +for.body.lr.ph: ; preds = %entry + %cmp0 = icmp sgt i32 %b, 0 + br i1 %cmp0, label %for.body, label %for.cond.cleanup + +for.body: ; preds = %for.inc, %for.body.lr.ph + %inc.i = phi i32 [ 0, %for.body.lr.ph ], [ %inc, %for.inc ] + %mul.i = phi i32 [ 3, %for.body.lr.ph ], [ %mul.p, %for.inc ] + %add.i = phi i32 [ %a, %for.body.lr.ph ], [ %add.p, %for.inc ] + %cmp1 = icmp eq i32 %a, 12345 + br i1 %cmp1, label %if.then, label %if.else, !prof !0 +; CHECK: %cmp1 = icmp eq i32 %a, 12345 +; CHECK-NEXT: br i1 %cmp1, label %for.body.us, label %for.body, !prof !0 +if.then: ; preds = %for.body +; CHECK: for.body.us: +; CHECK: add nsw i32 %{{.*}}, 123 +; CHECK: %exitcond.us = icmp eq i32 %inc.us, %b +; CHECK: br i1 %exitcond.us, label %for.cond.cleanup, label %for.body.us + %add = add nsw i32 %add.i, 123 + br label %for.inc + +if.else: ; preds = %for.body + %mul = mul nsw i32 %mul.i, %b + br label %for.inc +; CHECK: for.body: +; CHECK: %mul = mul nsw i32 %mul.i, %b +; CHECK: %inc = add nuw nsw i32 %inc.i, 1 +; CHECK: %exitcond = icmp eq i32 %inc, %b +; CHECK: br i1 %exitcond, label %for.cond.cleanup, label %for.body +for.inc: ; preds = %if.then, %if.else + %mul.p = phi i32 [ %b, %if.then ], [ %mul, %if.else ] + %add.p = phi i32 [ %add, %if.then ], [ %a, %if.else ] + %inc = add nuw nsw i32 %inc.i, 1 + %exitcond = icmp eq i32 %inc, %b + br i1 %exitcond, label %for.cond.cleanup, label %for.body + +for.cond.cleanup: ; preds = %for.inc, %for.body.lr.ph + %t2 = phi i32 [ %b, %for.body.lr.ph ], [ %mul.p, %for.inc ] + %t1 = phi i32 [ %a, %for.body.lr.ph ], [ %add.p, %for.inc ] + %add3 = add nsw i32 %t2, %t1 + ret i32 %add3 +} + +define void @foo_swapped(i32 %a, i32 %b) { +;CHECK-LABEL: foo_swapped +entry: + br label %for.body +;CHECK: entry: +;CHECK-NEXT: %cmp1 = icmp eq i32 1, 2 +;CHECK-NEXT: br i1 %cmp1, label %for.body, label %for.cond.cleanup.split, !prof !1 +;CHECK: for.body: +for.body: ; preds = %for.inc, %entry + %inc.i = phi i32 [ 0, %entry ], [ %inc, %if.then ] + %add.i = phi i32 [ 100, %entry ], [ %add, %if.then ] + %inc = add nuw nsw i32 %inc.i, 1 + %cmp1 = icmp eq i32 1, 2 + br i1 %cmp1, label %if.then, label %for.cond.cleanup, !prof !0 + +if.then: ; preds = %for.body + %add = add nsw i32 %a, %add.i + + %exitcond = icmp eq i32 %inc, %b + br i1 %exitcond, label %for.cond.cleanup, label %for.body + +for.cond.cleanup: ; preds = %for.inc, %for.body.lr.ph, %for.body + ret void +} +!0 = !{!"branch_weights", i32 64, i32 4} + +;CHECK: !0 = !{!"branch_weights", i32 64, i32 4} +;CHECK: !1 = !{!"branch_weights", i32 4, i32 64} diff --git a/llvm/test/Transforms/LoopUnswitch/2015-09-18-Addrspace.ll b/llvm/test/Transforms/LoopUnswitch/2015-09-18-Addrspace.ll new file mode 100644 index 00000000000..62236b4dd86 --- /dev/null +++ b/llvm/test/Transforms/LoopUnswitch/2015-09-18-Addrspace.ll @@ -0,0 +1,29 @@ +; RUN: opt < %s -loop-unswitch -S | FileCheck %s +; RUN: opt < %s -loop-unswitch -enable-mssa-loop-dependency=true -verify-memoryssa -S | FileCheck %s + +; In cases where two address spaces do not have the same size pointer, the +; input for the addrspacecast should not be used as a substitute for itself +; when manipulating the pointer. + +target datalayout = "e-m:e-p:16:16-p1:32:16-i32:16-i64:16-n8:16" + +define void @foo() { +; CHECK-LABEL: @foo +entry: + %arrayidx.i1 = getelementptr inbounds i16, i16* undef, i16 undef + %arrayidx.i = addrspacecast i16* %arrayidx.i1 to i16 addrspace(1)* + br i1 undef, label %for.body.i, label %bar.exit + +for.body.i: ; preds = %for.body.i, %entry +; When we call makeLoopInvariant (i.e. trivial LICM) on this load, it +; will try to find the base object to prove deferenceability. If we look +; through the addrspacecast, we'll fail an assertion about bitwidths matching +; CHECK-LABEL: for.body.i +; CHECK: %0 = load i16, i16 addrspace(1)* %arrayidx.i, align 2 + %0 = load i16, i16 addrspace(1)* %arrayidx.i, align 2 + %cmp1.i = icmp eq i16 %0, 0 + br i1 %cmp1.i, label %bar.exit, label %for.body.i + +bar.exit: ; preds = %for.body.i, %entry + ret void +} diff --git a/llvm/test/Transforms/LoopUnswitch/AMDGPU/divergent-unswitch.ll b/llvm/test/Transforms/LoopUnswitch/AMDGPU/divergent-unswitch.ll new file mode 100644 index 00000000000..1f106bd894a --- /dev/null +++ b/llvm/test/Transforms/LoopUnswitch/AMDGPU/divergent-unswitch.ll @@ -0,0 +1,85 @@ +; RUN: opt -mtriple=amdgcn-- -O3 -S %s | FileCheck %s + +; Check that loop unswitch happened and condition hoisted out of the loop. +; Condition is uniform so all targets should perform unswitching. + +; CHECK-LABEL: {{^}}define amdgpu_kernel void @uniform_unswitch +; CHECK: entry: +; CHECK-NEXT: [[LOOP_COND:%[a-z0-9]+]] = icmp +; CHECK-NEXT: [[IF_COND:%[a-z0-9]+]] = icmp eq i32 %x, 123456 +; CHECK-NEXT: and i1 [[LOOP_COND]], [[IF_COND]] +; CHECK-NEXT: br i1 + +define amdgpu_kernel void @uniform_unswitch(i32 * nocapture %out, i32 %n, i32 %x) { +entry: + %cmp6 = icmp sgt i32 %n, 0 + br i1 %cmp6, label %for.body.lr.ph, label %for.cond.cleanup + +for.body.lr.ph: ; preds = %entry + %cmp1 = icmp eq i32 %x, 123456 + br label %for.body + +for.cond.cleanup.loopexit: ; preds = %for.inc + br label %for.cond.cleanup + +for.cond.cleanup: ; preds = %for.cond.cleanup.loopexit, %entry + ret void + +for.body: ; preds = %for.inc, %for.body.lr.ph + %i.07 = phi i32 [ 0, %for.body.lr.ph ], [ %inc, %for.inc ] + br i1 %cmp1, label %if.then, label %for.inc + +if.then: ; preds = %for.body + %arrayidx = getelementptr inbounds i32, i32 * %out, i32 %i.07 + store i32 %i.07, i32 * %arrayidx, align 4 + br label %for.inc + +for.inc: ; preds = %for.body, %if.then + %inc = add nuw nsw i32 %i.07, 1 + %exitcond = icmp eq i32 %inc, %n + br i1 %exitcond, label %for.cond.cleanup.loopexit, label %for.body +} + +; Check that loop unswitch does not happen if condition is divergent. + +; CHECK-LABEL: {{^}}define amdgpu_kernel void @divergent_unswitch +; CHECK: entry: +; CHECK: icmp +; CHECK: [[IF_COND:%[a-z0-9]+]] = icmp {{.*}} 567890 +; CHECK: br label +; CHECK: br i1 [[IF_COND]] + +define amdgpu_kernel void @divergent_unswitch(i32 * nocapture %out, i32 %n) { +entry: + %cmp9 = icmp sgt i32 %n, 0 + br i1 %cmp9, label %for.body.lr.ph, label %for.cond.cleanup + +for.body.lr.ph: ; preds = %entry + %call = tail call i32 @llvm.amdgcn.workitem.id.x() #0 + %cmp2 = icmp eq i32 %call, 567890 + br label %for.body + +for.cond.cleanup.loopexit: ; preds = %for.inc + br label %for.cond.cleanup + +for.cond.cleanup: ; preds = %for.cond.cleanup.loopexit, %entry + ret void + +for.body: ; preds = %for.inc, %for.body.lr.ph + %i.010 = phi i32 [ 0, %for.body.lr.ph ], [ %inc, %for.inc ] + br i1 %cmp2, label %if.then, label %for.inc + +if.then: ; preds = %for.body + %arrayidx = getelementptr inbounds i32, i32 * %out, i32 %i.010 + store i32 %i.010, i32 * %arrayidx, align 4 + br label %for.inc + +for.inc: ; preds = %for.body, %if.then + %inc = add nuw nsw i32 %i.010, 1 + %exitcond = icmp eq i32 %inc, %n + br i1 %exitcond, label %for.cond.cleanup.loopexit, label %for.body +} + +declare i32 @llvm.amdgcn.workitem.id.x() #0 + +attributes #0 = { nounwind readnone } diff --git a/llvm/test/Transforms/LoopUnswitch/AMDGPU/lit.local.cfg b/llvm/test/Transforms/LoopUnswitch/AMDGPU/lit.local.cfg new file mode 100644 index 00000000000..2a665f06be7 --- /dev/null +++ b/llvm/test/Transforms/LoopUnswitch/AMDGPU/lit.local.cfg @@ -0,0 +1,2 @@ +if not 'AMDGPU' in config.root.targets: + config.unsupported = True diff --git a/llvm/test/Transforms/LoopUnswitch/LIV-loop-condtion.ll b/llvm/test/Transforms/LoopUnswitch/LIV-loop-condtion.ll new file mode 100644 index 00000000000..bf4b68c1d2e --- /dev/null +++ b/llvm/test/Transforms/LoopUnswitch/LIV-loop-condtion.ll @@ -0,0 +1,29 @@ +; RUN: opt < %s -loop-unswitch -loop-unswitch-threshold=0 -S 2>&1 | FileCheck %s +; RUN: opt < %s -loop-unswitch -loop-unswitch-threshold=0 -enable-mssa-loop-dependency=true -verify-memoryssa -S 2>&1 | FileCheck %s + +; This is to test trivial loop unswitch only happens when trivial condition +; itself is an LIV loop condition (not partial LIV which could occur in and/or). + +define i32 @test(i1 %cond1, i32 %var1) { +entry: + br label %loop_begin + +loop_begin: + %var3 = phi i32 [%var1, %entry], [%var2, %do_something] + %cond2 = icmp eq i32 %var3, 10 + %cond.and = and i1 %cond1, %cond2 + +; %cond.and only has %cond1 as LIV so no unswitch should happen. +; CHECK: br i1 %cond.and, label %do_something, label %loop_exit + br i1 %cond.and, label %do_something, label %loop_exit + +do_something: + %var2 = add i32 %var3, 1 + call void @some_func() noreturn nounwind + br label %loop_begin + +loop_exit: + ret i32 0 +} + +declare void @some_func() noreturn diff --git a/llvm/test/Transforms/LoopUnswitch/basictest.ll b/llvm/test/Transforms/LoopUnswitch/basictest.ll new file mode 100644 index 00000000000..539abd838cf --- /dev/null +++ b/llvm/test/Transforms/LoopUnswitch/basictest.ll @@ -0,0 +1,319 @@ +; RUN: opt < %s -loop-unswitch -verify-loop-info -S < %s 2>&1 | FileCheck %s +; RUN: opt < %s -loop-unswitch -verify-loop-info -enable-mssa-loop-dependency=true -verify-memoryssa -S < %s 2>&1 | FileCheck %s + +define i32 @test(i32* %A, i1 %C) { +entry: + br label %no_exit +no_exit: ; preds = %no_exit.backedge, %entry + %i.0.0 = phi i32 [ 0, %entry ], [ %i.0.0.be, %no_exit.backedge ] ; <i32> [#uses=3] + %gep.upgrd.1 = zext i32 %i.0.0 to i64 ; <i64> [#uses=1] + %tmp.7 = getelementptr i32, i32* %A, i64 %gep.upgrd.1 ; <i32*> [#uses=4] + %tmp.13 = load i32, i32* %tmp.7 ; <i32> [#uses=2] + %tmp.14 = add i32 %tmp.13, 1 ; <i32> [#uses=1] + store i32 %tmp.14, i32* %tmp.7 + br i1 %C, label %then, label %endif +then: ; preds = %no_exit + %tmp.29 = load i32, i32* %tmp.7 ; <i32> [#uses=1] + %tmp.30 = add i32 %tmp.29, 2 ; <i32> [#uses=1] + store i32 %tmp.30, i32* %tmp.7 + %inc9 = add i32 %i.0.0, 1 ; <i32> [#uses=2] + %tmp.112 = icmp ult i32 %inc9, 100000 ; <i1> [#uses=1] + br i1 %tmp.112, label %no_exit.backedge, label %return +no_exit.backedge: ; preds = %endif, %then + %i.0.0.be = phi i32 [ %inc9, %then ], [ %inc, %endif ] ; <i32> [#uses=1] + br label %no_exit +endif: ; preds = %no_exit + %inc = add i32 %i.0.0, 1 ; <i32> [#uses=2] + %tmp.1 = icmp ult i32 %inc, 100000 ; <i1> [#uses=1] + br i1 %tmp.1, label %no_exit.backedge, label %return +return: ; preds = %endif, %then + ret i32 %tmp.13 +} + +; This simple test would normally unswitch, but should be inhibited by the presence of +; the noduplicate call. + +; CHECK-LABEL: @test2( +define i32 @test2(i32* %var) { + %mem = alloca i32 + store i32 2, i32* %mem + %c = load i32, i32* %mem + + br label %loop_begin + +loop_begin: + + %var_val = load i32, i32* %var + + switch i32 %c, label %default [ + i32 1, label %inc + i32 2, label %dec + ] + +inc: + call void @incf() noreturn nounwind + br label %loop_begin +dec: +; CHECK: call void @decf() +; CHECK-NOT: call void @decf() + call void @decf() noreturn nounwind noduplicate + br label %loop_begin +default: + br label %loop_exit +loop_exit: + ret i32 0 +; CHECK: } +} + +; This simple test would normally unswitch, but should be inhibited by the presence of +; the convergent call that is not control-dependent on the unswitch condition. + +; CHECK-LABEL: @test3( +define i32 @test3(i32* %var) { + %mem = alloca i32 + store i32 2, i32* %mem + %c = load i32, i32* %mem + + br label %loop_begin + +loop_begin: + + %var_val = load i32, i32* %var + +; CHECK: call void @conv() +; CHECK-NOT: call void @conv() + call void @conv() convergent + + switch i32 %c, label %default [ + i32 1, label %inc + i32 2, label %dec + ] + +inc: + call void @incf() noreturn nounwind + br label %loop_begin +dec: + call void @decf() noreturn nounwind + br label %loop_begin +default: + br label %loop_exit +loop_exit: + ret i32 0 +; CHECK: } +} + +; Make sure we unswitch %a == 0 out of the loop. +; +; CHECK: define void @and_i2_as_switch_input(i2 +; CHECK: entry: +; This is an indication that the loop has been unswitched. +; CHECK: icmp eq i2 %a, 0 +; CHECK: br +; There should be no more unswitching after the 1st unswitch. +; CHECK-NOT: icmp eq +; CHECK: ret +define void @and_i2_as_switch_input(i2 %a) { +entry: + br label %for.body + +for.body: + %i = phi i2 [ 0, %entry ], [ %inc, %for.inc ] + %and = and i2 %a, %i + %and1 = and i2 %and, %i + switch i2 %and1, label %sw.default [ + i2 0, label %sw.bb + i2 1, label %sw.bb1 + ] + +sw.bb: + br label %sw.epilog + +sw.bb1: + br label %sw.epilog + +sw.default: + br label %sw.epilog + +sw.epilog: + br label %for.inc + +for.inc: + %inc = add nsw i2 %i, 1 + %cmp = icmp slt i2 %inc, 3 + br i1 %cmp, label %for.body, label %for.end + +for.end: + ret void +} + +; Make sure we unswitch %a == !0 out of the loop. +; +; CHECK: define void @or_i2_as_switch_input(i2 +; CHECK: entry: +; This is an indication that the loop has been unswitched. +; CHECK: icmp eq i2 %a, -1 +; CHECK: br +; There should be no more unswitching after the 1st unswitch. +; CHECK-NOT: icmp eq +; CHECK: ret +define void @or_i2_as_switch_input(i2 %a) { +entry: + br label %for.body + +for.body: + %i = phi i2 [ 0, %entry ], [ %inc, %for.inc ] + %or = or i2 %a, %i + %or1 = or i2 %or, %i + switch i2 %or1, label %sw.default [ + i2 2, label %sw.bb + i2 3, label %sw.bb1 + ] + +sw.bb: + br label %sw.epilog + +sw.bb1: + br label %sw.epilog + +sw.default: + br label %sw.epilog + +sw.epilog: + br label %for.inc + +for.inc: + %inc = add nsw i2 %i, 1 + %cmp = icmp slt i2 %inc, 3 + br i1 %cmp, label %for.body, label %for.end + +for.end: + ret void +} + +; Make sure we unswitch %a == !0 out of the loop. Even we do not +; have it as a case value. Unswitching it out allows us to simplify +; the or operator chain. +; +; CHECK: define void @or_i2_as_switch_input_unswitch_default(i2 +; CHECK: entry: +; This is an indication that the loop has been unswitched. +; CHECK: icmp eq i2 %a, -1 +; CHECK: br +; There should be no more unswitching after the 1st unswitch. +; CHECK-NOT: icmp eq +; CHECK: ret +define void @or_i2_as_switch_input_unswitch_default(i2 %a) { +entry: + br label %for.body + +for.body: + %i = phi i2 [ 0, %entry ], [ %inc, %for.inc ] + %or = or i2 %a, %i + %or1 = or i2 %or, %i + switch i2 %or1, label %sw.default [ + i2 1, label %sw.bb + i2 2, label %sw.bb1 + ] + +sw.bb: + br label %sw.epilog + +sw.bb1: + br label %sw.epilog + +sw.default: + br label %sw.epilog + +sw.epilog: + br label %for.inc + +for.inc: + %inc = add nsw i2 %i, 1 + %cmp = icmp slt i2 %inc, 3 + br i1 %cmp, label %for.body, label %for.end + +for.end: + ret void +} + +; Make sure we don't unswitch, as we can not find an input value %a +; that will effectively unswitch 0 or 3 out of the loop. +; +; CHECK: define void @and_or_i2_as_switch_input(i2 +; CHECK: entry: +; This is an indication that the loop has NOT been unswitched. +; CHECK-NOT: icmp +; CHECK: br +define void @and_or_i2_as_switch_input(i2 %a) { +entry: + br label %for.body + +for.body: + %i = phi i2 [ 0, %entry ], [ %inc, %for.inc ] + %and = and i2 %a, %i + %or = or i2 %and, %i + switch i2 %or, label %sw.default [ + i2 0, label %sw.bb + i2 3, label %sw.bb1 + ] + +sw.bb: + br label %sw.epilog + +sw.bb1: + br label %sw.epilog + +sw.default: + br label %sw.epilog + +sw.epilog: + br label %for.inc + +for.inc: + %inc = add nsw i2 %i, 1 + %cmp = icmp slt i2 %inc, 3 + br i1 %cmp, label %for.body, label %for.end + +for.end: + ret void +} + +; Make sure we don't unswitch, as we can not find an input value %a +; that will effectively unswitch true/false out of the loop. +; +; CHECK: define void @and_or_i1_as_branch_input(i1 +; CHECK: entry: +; This is an indication that the loop has NOT been unswitched. +; CHECK-NOT: icmp +; CHECK: br +define void @and_or_i1_as_branch_input(i1 %a) { +entry: + br label %for.body + +for.body: + %i = phi i1 [ 0, %entry ], [ %inc, %for.inc ] + %and = and i1 %a, %i + %or = or i1 %and, %i + br i1 %or, label %sw.bb, label %sw.bb1 + +sw.bb: + br label %sw.epilog + +sw.bb1: + br label %sw.epilog + +sw.epilog: + br label %for.inc + +for.inc: + %inc = add nsw i1 %i, 1 + %cmp = icmp slt i1 %inc, 1 + br i1 %cmp, label %for.body, label %for.end + +for.end: + ret void +} + +declare void @incf() noreturn +declare void @decf() noreturn +declare void @conv() convergent diff --git a/llvm/test/Transforms/LoopUnswitch/cleanuppad.ll b/llvm/test/Transforms/LoopUnswitch/cleanuppad.ll new file mode 100644 index 00000000000..80b913b1035 --- /dev/null +++ b/llvm/test/Transforms/LoopUnswitch/cleanuppad.ll @@ -0,0 +1,45 @@ +; RUN: opt -S -loop-unswitch < %s | FileCheck %s +; RUN: opt -S -loop-unswitch -enable-mssa-loop-dependency=true -verify-memoryssa < %s | FileCheck %s +target triple = "x86_64-pc-win32" + +define void @f(i32 %doit, i1 %x, i1 %y) personality i32 (...)* @__CxxFrameHandler3 { +entry: + %tobool = icmp eq i32 %doit, 0 + br label %for.cond + +for.cond: ; preds = %for.inc, %entry + br i1 %x, label %for.body, label %for.end + +for.body: ; preds = %for.cond + br i1 %tobool, label %if.then, label %for.inc + +if.then: ; preds = %for.body + br i1 %y, label %for.inc, label %delete.notnull + +delete.notnull: ; preds = %if.then + invoke void @g() + to label %invoke.cont unwind label %lpad + +invoke.cont: ; preds = %delete.notnull + br label %for.inc + +lpad: ; preds = %delete.notnull + %cp = cleanuppad within none [] + cleanupret from %cp unwind to caller + +for.inc: ; preds = %invoke.cont, %if.then, %for.body + br label %for.cond + +for.end: ; preds = %for.cond + ret void +} + +declare void @g() + +declare i32 @__CxxFrameHandler3(...) + +; CHECK-LABEL: define void @f( +; CHECK: cleanuppad within none [] +; CHECK-NOT: cleanuppad + +attributes #0 = { ssp uwtable } diff --git a/llvm/test/Transforms/LoopUnswitch/copy-metadata.ll b/llvm/test/Transforms/LoopUnswitch/copy-metadata.ll new file mode 100644 index 00000000000..6b5b93dedf9 --- /dev/null +++ b/llvm/test/Transforms/LoopUnswitch/copy-metadata.ll @@ -0,0 +1,24 @@ +; RUN: opt < %s -loop-unswitch -S < %s 2>&1 | FileCheck %s +; RUN: opt < %s -loop-unswitch -enable-mssa-loop-dependency=true -verify-memoryssa -S < %s 2>&1 | FileCheck %s + +; This test checks if unswitched condition preserve make.implicit metadata. + +define i32 @test(i1 %cond) { +; CHECK-LABEL: @test( +; CHECK: br i1 %cond, label %..split_crit_edge, label %.loop_exit.split_crit_edge, !make.implicit !0 + br label %loop_begin + +loop_begin: + br i1 %cond, label %continue, label %loop_exit, !make.implicit !0 + +continue: + call void @some_func() + br label %loop_begin + +loop_exit: + ret i32 0 +} + +declare void @some_func() + +!0 = !{} diff --git a/llvm/test/Transforms/LoopUnswitch/crash.ll b/llvm/test/Transforms/LoopUnswitch/crash.ll new file mode 100644 index 00000000000..6df3e7f3eb0 --- /dev/null +++ b/llvm/test/Transforms/LoopUnswitch/crash.ll @@ -0,0 +1,67 @@ +; RUN: opt < %s -loop-unswitch -disable-output +; RUN: opt < %s -loop-unswitch -enable-mssa-loop-dependency=true -verify-memoryssa -disable-output + +define void @test1(i32* %S2) { +entry: + br i1 false, label %list_Length.exit, label %cond_true.i +cond_true.i: ; preds = %entry + ret void +list_Length.exit: ; preds = %entry + br i1 false, label %list_Length.exit9, label %cond_true.i5 +cond_true.i5: ; preds = %list_Length.exit + ret void +list_Length.exit9: ; preds = %list_Length.exit + br i1 false, label %bb78, label %return +bb44: ; preds = %bb78, %cond_next68 + br i1 %tmp49.not, label %bb62, label %bb62.loopexit +bb62.loopexit: ; preds = %bb44 + br label %bb62 +bb62: ; preds = %bb62.loopexit, %bb44 + br i1 false, label %return.loopexit, label %cond_next68 +cond_next68: ; preds = %bb62 + br i1 false, label %return.loopexit, label %bb44 +bb78: ; preds = %list_Length.exit9 + %tmp49.not = icmp eq i32* %S2, null ; <i1> [#uses=1] + br label %bb44 +return.loopexit: ; preds = %cond_next68, %bb62 + %retval.0.ph = phi i32 [ 1, %cond_next68 ], [ 0, %bb62 ] ; <i32> [#uses=1] + br label %return +return: ; preds = %return.loopexit, %list_Length.exit9 + %retval.0 = phi i32 [ 0, %list_Length.exit9 ], [ %retval.0.ph, %return.loopexit ] ; <i32> [#uses=0] + ret void +} + +define void @test2() nounwind { +entry: + br label %bb.nph + +bb.nph: ; preds = %entry + %and.i13521 = and <4 x i1> undef, undef ; <<4 x i1>> [#uses=1] + br label %for.body + +for.body: ; preds = %for.body, %bb.nph + %or.i = select <4 x i1> %and.i13521, <4 x i32> undef, <4 x i32> undef ; <<4 x i32>> [#uses=0] + br i1 false, label %for.body, label %for.end + +for.end: ; preds = %for.body, %entry + ret void +} + +; PR6879 +define i32* @test3(i32** %p_45, i16 zeroext %p_46, i64 %p_47, i64 %p_48, i16 signext %p_49) nounwind { +entry: + br label %for.cond + +for.cond: ; preds = %for.cond4, %entry + br i1 false, label %for.cond4, label %for.end88 + +for.cond4: ; preds = %for.cond + %conv46 = trunc i32 0 to i8 ; <i8> [#uses=2] + %cmp60 = icmp sgt i8 %conv46, 124 ; <i1> [#uses=1] + %or.cond = and i1 undef, %cmp60 ; <i1> [#uses=1] + %cond = select i1 %or.cond, i8 %conv46, i8 undef ; <i8> [#uses=0] + br label %for.cond + +for.end88: ; preds = %for.cond + ret i32* undef +} diff --git a/llvm/test/Transforms/LoopUnswitch/elseif-non-exponential-behavior.ll b/llvm/test/Transforms/LoopUnswitch/elseif-non-exponential-behavior.ll new file mode 100644 index 00000000000..b328aaae973 --- /dev/null +++ b/llvm/test/Transforms/LoopUnswitch/elseif-non-exponential-behavior.ll @@ -0,0 +1,63 @@ +; RUN: opt -loop-unswitch -S - < %s | FileCheck %s +; RUN: opt -loop-unswitch -enable-mssa-loop-dependency=true -verify-memoryssa -S - < %s | FileCheck %s + +;CHECK-LABEL: @b +;CHECK: [[Loop1:for\.end.*]]: ; preds = %for.cond.us +;CHECK-NEXT: %[[PhiVar1:pdt.*]] = phi i32 [ %pdt.0.us, %for.cond.us ] +;CHECK: [[Loop2:for\.end.*]]: ; preds = %for.cond.us1 +;CHECK-NEXT: %[[PhiVar2:pdt.*]] = phi i32 [ %pdt.0.us2, %for.cond.us1 ] +;CHECK: [[Loop3:for\.end.*]]: ; preds = %for.cond +;CHECK-NEXT: %[[PhiVar3:pdt.*]] = phi i32 [ %pdt.0, %for.cond ] +;CHECK: [[Join1:for\.end.*]]: ; preds = %[[Loop2]], %[[Loop3]] +;CHECK-NEXT: %[[PhiRes1:pdt.*]] = phi i32 [ %[[PhiVar3]], %[[Loop3]] ], [ %[[PhiVar2]], %[[Loop2]] ] +;CHECK: for.end: ; preds = %[[Loop1]], %[[Join1]] +;CHECK-NEXT: %[[PhiRes2:pdt.*]] = phi i32 [ %[[PhiRes1]], %[[Join1]] ], [ %[[PhiVar1]], %[[Loop1]] ] +;CHECK-NEXT: ret i32 %[[PhiRes2]] + +; Function Attrs: nounwind uwtable +define i32 @b(i32 %x, i32 %y) #0 { +entry: + br label %for.cond + +for.cond: ; preds = %for.inc, %entry + %pdt.0 = phi i32 [ 1, %entry ], [ %pdt.2, %for.inc ] + %i.0 = phi i32 [ 0, %entry ], [ %inc, %for.inc ] + %cmp = icmp slt i32 %i.0, 100 + br i1 %cmp, label %for.body, label %for.end + +for.body: ; preds = %for.cond + %tobool = icmp ne i32 %x, 0 + br i1 %tobool, label %if.then, label %if.else + +if.then: ; preds = %for.body + %mul = mul nsw i32 %pdt.0, 2 + br label %if.end6 + +if.else: ; preds = %for.body + %tobool1 = icmp ne i32 %y, 0 + br i1 %tobool1, label %if.then2, label %if.else4 + +if.then2: ; preds = %if.else + %mul3 = mul nsw i32 %pdt.0, 3 + br label %if.end + +if.else4: ; preds = %if.else + %mul5 = mul nsw i32 %pdt.0, 4 + br label %if.end + +if.end: ; preds = %if.else4, %if.then2 + %pdt.1 = phi i32 [ %mul3, %if.then2 ], [ %mul5, %if.else4 ] + br label %if.end6 + +if.end6: ; preds = %if.end, %if.then + %pdt.2 = phi i32 [ %mul, %if.then ], [ %pdt.1, %if.end ] + br label %for.inc + +for.inc: ; preds = %if.end6 + %inc = add nsw i32 %i.0, 1 + br label %for.cond + +for.end: ; preds = %for.cond + ret i32 %pdt.0 +} + diff --git a/llvm/test/Transforms/LoopUnswitch/exponential-behavior.ll b/llvm/test/Transforms/LoopUnswitch/exponential-behavior.ll new file mode 100644 index 00000000000..9dfa61e028c --- /dev/null +++ b/llvm/test/Transforms/LoopUnswitch/exponential-behavior.ll @@ -0,0 +1,52 @@ +; RUN: opt -loop-unswitch -S < %s | FileCheck %s +; RUN: opt -loop-unswitch -enable-mssa-loop-dependency=true -verify-memoryssa -S < %s | FileCheck %s + +define void @f(i32 %n, i32* %ptr) { +; CHECK-LABEL: @f( +entry: + br label %loop + +loop: + %iv = phi i32 [ 0, %entry ], [ %iv.inc, %be ] + %iv.inc = add i32 %iv, 1 + %unswitch_cond_root = icmp ne i32 %iv.inc, 42 + %us.0 = and i1 %unswitch_cond_root, %unswitch_cond_root + %us.1 = and i1 %us.0, %us.0 + %us.2 = and i1 %us.1, %us.1 + %us.3 = and i1 %us.2, %us.2 + %us.4 = and i1 %us.3, %us.3 + %us.5 = and i1 %us.4, %us.4 + %us.6 = and i1 %us.5, %us.5 + %us.7 = and i1 %us.6, %us.6 + %us.8 = and i1 %us.7, %us.7 + %us.9 = and i1 %us.8, %us.8 + %us.10 = and i1 %us.9, %us.9 + %us.11 = and i1 %us.10, %us.10 + %us.12 = and i1 %us.11, %us.11 + %us.13 = and i1 %us.12, %us.12 + %us.14 = and i1 %us.13, %us.13 + %us.15 = and i1 %us.14, %us.14 + %us.16 = and i1 %us.15, %us.15 + %us.17 = and i1 %us.16, %us.16 + %us.18 = and i1 %us.17, %us.17 + %us.19 = and i1 %us.18, %us.18 + %us.20 = and i1 %us.19, %us.19 + %us.21 = and i1 %us.20, %us.20 + %us.22 = and i1 %us.21, %us.21 + %us.23 = and i1 %us.22, %us.22 + %us.24 = and i1 %us.23, %us.23 + %us.25 = and i1 %us.24, %us.24 + %us.26 = and i1 %us.25, %us.25 + %us.27 = and i1 %us.26, %us.26 + %us.28 = and i1 %us.27, %us.27 + %us.29 = and i1 %us.28, %us.28 + br i1 %us.29, label %leave, label %be + +be: + store volatile i32 0, i32* %ptr + %becond = icmp ult i32 %iv.inc, %n + br i1 %becond, label %leave, label %loop + +leave: + ret void +} diff --git a/llvm/test/Transforms/LoopUnswitch/guards.ll b/llvm/test/Transforms/LoopUnswitch/guards.ll new file mode 100644 index 00000000000..957ea1a7900 --- /dev/null +++ b/llvm/test/Transforms/LoopUnswitch/guards.ll @@ -0,0 +1,98 @@ +; RUN: opt -S -loop-unswitch < %s | FileCheck %s +; RUN: opt -S -loop-unswitch -enable-mssa-loop-dependency=true -verify-memoryssa < %s | FileCheck %s + +declare void @llvm.experimental.guard(i1, ...) + +define void @f_0(i32 %n, i32* %ptr, i1 %c) { +; CHECK-LABEL: @f_0( +; CHECK: loop.us: +; CHECK-NOT: guard +; CHECK: loop: +; CHECK: call void (i1, ...) @llvm.experimental.guard(i1 false) [ "deopt"() ] +entry: + br label %loop + +loop: + %iv = phi i32 [ 0, %entry ], [ %iv.inc, %loop ] + %iv.inc = add i32 %iv, 1 + call void(i1, ...) @llvm.experimental.guard(i1 %c) [ "deopt"() ] + store volatile i32 0, i32* %ptr + %becond = icmp ult i32 %iv.inc, %n + br i1 %becond, label %leave, label %loop + +leave: + ret void +} + +define void @f_1(i32 %n, i32* %ptr, i1 %c_0, i1 %c_1) { +; CHECK-LABEL: @f_1( +; CHECK: loop.us.us: +; CHECK-NOT: guard +; CHECK: loop.us: +; CHECK: call void (i1, ...) @llvm.experimental.guard(i1 false) [ "deopt"(i32 2) ] +; CHECK-NOT: guard +; CHECK: loop.us1: +; CHECK: call void (i1, ...) @llvm.experimental.guard(i1 false) [ "deopt"(i32 1) ] +; CHECK-NOT: guard +; CHECK: loop: +; CHECK: call void (i1, ...) @llvm.experimental.guard(i1 false) [ "deopt"(i32 1) ] +; CHECK: call void (i1, ...) @llvm.experimental.guard(i1 false) [ "deopt"(i32 2) ] +entry: + br label %loop + +loop: + %iv = phi i32 [ 0, %entry ], [ %iv.inc, %loop ] + %iv.inc = add i32 %iv, 1 + call void(i1, ...) @llvm.experimental.guard(i1 %c_0) [ "deopt"(i32 1) ] + store volatile i32 0, i32* %ptr + call void(i1, ...) @llvm.experimental.guard(i1 %c_1) [ "deopt"(i32 2) ] + %becond = icmp ult i32 %iv.inc, %n + br i1 %becond, label %leave, label %loop + +leave: + ret void +} + +; Basic negative test + +define void @f_3(i32 %n, i32* %ptr, i1* %c_ptr) { +; CHECK-LABEL: @f_3( +; CHECK-NOT: loop.us: +entry: + br label %loop + +loop: + %iv = phi i32 [ 0, %entry ], [ %iv.inc, %loop ] + %iv.inc = add i32 %iv, 1 + %c = load volatile i1, i1* %c_ptr + call void(i1, ...) @llvm.experimental.guard(i1 %c) [ "deopt"() ] + store volatile i32 0, i32* %ptr + %becond = icmp ult i32 %iv.inc, %n + br i1 %becond, label %leave, label %loop + +leave: + ret void +} + +define void @f_4(i32 %n, i32* %ptr, i1 %c) { +; CHECK-LABEL: @f_4( +; +; Demonstrate that unswitching on one guard can cause another guard to +; be erased (this has implications on what guards we can keep raw +; pointers to). +entry: + br label %loop + +loop: + %iv = phi i32 [ 0, %entry ], [ %iv.inc, %loop ] + %iv.inc = add i32 %iv, 1 + call void(i1, ...) @llvm.experimental.guard(i1 %c) [ "deopt"(i32 1) ] + store volatile i32 0, i32* %ptr + %neg = xor i1 %c, 1 + call void(i1, ...) @llvm.experimental.guard(i1 %neg) [ "deopt"(i32 2) ] + %becond = icmp ult i32 %iv.inc, %n + br i1 %becond, label %leave, label %loop + +leave: + ret void +} diff --git a/llvm/test/Transforms/LoopUnswitch/infinite-loop.ll b/llvm/test/Transforms/LoopUnswitch/infinite-loop.ll new file mode 100644 index 00000000000..f11aa50e634 --- /dev/null +++ b/llvm/test/Transforms/LoopUnswitch/infinite-loop.ll @@ -0,0 +1,59 @@ +; REQUIRES: asserts +; RUN: opt -loop-unswitch -disable-output -stats -info-output-file - < %s | FileCheck --check-prefix=STATS %s +; RUN: opt -loop-unswitch -enable-mssa-loop-dependency=true -verify-memoryssa -disable-output -stats -info-output-file - < %s | FileCheck --check-prefix=STATS %s +; RUN: opt -loop-unswitch -simplifycfg -S < %s | FileCheck %s +; PR5373 + +; Loop unswitching shouldn't trivially unswitch the true case of condition %a +; in the code here because it leads to an infinite loop. While this doesn't +; contain any instructions with side effects, it's still a kind of side effect. +; It can trivially unswitch on the false case of condition %a though. + +; STATS: 2 loop-unswitch - Number of branches unswitched +; STATS: 2 loop-unswitch - Number of unswitches that are trivial + +; CHECK-LABEL: @func_16( +; CHECK-NEXT: entry: +; CHECK-NEXT: br i1 %a, label %entry.split, label %abort0.split + +; CHECK: entry.split: +; CHECK-NEXT: br i1 %b, label %for.body, label %abort1.split + +; CHECK: for.body: +; CHECK-NEXT: br label %for.body + +; CHECK: abort0.split: +; CHECK-NEXT: call void @end0() [[NOR_NUW:#[0-9]+]] +; CHECK-NEXT: unreachable + +; CHECK: abort1.split: +; CHECK-NEXT: call void @end1() [[NOR_NUW]] +; CHECK-NEXT: unreachable + +; CHECK: } + +define void @func_16(i1 %a, i1 %b) nounwind { +entry: + br label %for.body + +for.body: + br i1 %a, label %cond.end, label %abort0 + +cond.end: + br i1 %b, label %for.body, label %abort1 + +abort0: + call void @end0() noreturn nounwind + unreachable + +abort1: + call void @end1() noreturn nounwind + unreachable +} + +declare void @end0() noreturn +declare void @end1() noreturn + +; CHECK: attributes #0 = { nounwind } +; CHECK: attributes #1 = { noreturn } +; CHECK: attributes [[NOR_NUW]] = { noreturn nounwind } diff --git a/llvm/test/Transforms/LoopUnswitch/invalidate-scev.ll b/llvm/test/Transforms/LoopUnswitch/invalidate-scev.ll new file mode 100644 index 00000000000..78ef4f00abc --- /dev/null +++ b/llvm/test/Transforms/LoopUnswitch/invalidate-scev.ll @@ -0,0 +1,34 @@ +; RUN: opt -S -indvars -loop-unswitch < %s | FileCheck %s +; RUN: opt -S -indvars -loop-unswitch -enable-mssa-loop-dependency=true -verify-memoryssa < %s | FileCheck %s + +target triple = "x86_64-unknown-linux-gnu" + +define void @test_01() { + +; Make sure we don't fail by SCEV's assertion due to incorrect invalidation. +; CHECK-LABEL: @test_01 + +entry: + br label %loop + +loop: ; preds = %backedge, %entry + %p_50.addr.0 = phi i16 [ undef, %entry ], [ %add2699, %backedge ] + %idxprom2690 = sext i16 %p_50.addr.0 to i32 + %arrayidx2691 = getelementptr inbounds [5 x i32], [5 x i32]* undef, i32 0, i32 %idxprom2690 + %0 = load i32, i32* %arrayidx2691, align 1 + %tobool2692 = icmp ne i32 %0, 0 + br label %inner_loop + +inner_loop: ; preds = %inner_backedge, %loop + br i1 %tobool2692, label %backedge, label %inner_backedge + +inner_backedge: ; preds = %inner_loop + br label %inner_loop + +backedge: ; preds = %inner_loop + %add2699 = add nsw i16 %p_50.addr.0, 1 + br i1 false, label %loop, label %exit + +exit: ; preds = %backedge + unreachable +} diff --git a/llvm/test/Transforms/LoopUnswitch/msan.ll b/llvm/test/Transforms/LoopUnswitch/msan.ll new file mode 100644 index 00000000000..194e64687be --- /dev/null +++ b/llvm/test/Transforms/LoopUnswitch/msan.ll @@ -0,0 +1,154 @@ +; RUN: opt < %s -loop-unswitch -verify-loop-info -S < %s 2>&1 | FileCheck %s +; RUN: opt < %s -loop-unswitch -verify-loop-info -enable-mssa-loop-dependency=true -verify-memoryssa -S < %s 2>&1 | FileCheck %s + +@sink = global i32 0, align 4 +@y = global i64 0, align 8 + +; The following is approximately: +; void f(bool x, int p, int q) { +; volatile bool x2 = x; +; for (int i = 0; i < 1; ++i) { +; if (x2) { +; if (y) +; sink = p; +; else +; sink = q; +; } +; } +; } +; With MemorySanitizer, the loop can not be unswitched on "y", because "y" could +; be uninitialized when x == false. +; Test that the branch on "y" is inside the loop (after the first unconditional +; branch). + +define void @may_not_execute(i1 zeroext %x, i32 %p, i32 %q) sanitize_memory { +; CHECK-LABEL: @may_not_execute( +entry: +; CHECK: %[[Y:.*]] = load i64, i64* @y, align 8 +; CHECK: %[[YB:.*]] = icmp eq i64 %[[Y]], 0 +; CHECK-NOT: br i1 +; CHECK: br label +; CHECK: br i1 %[[YB]] + + %x2 = alloca i8, align 1 + %frombool1 = zext i1 %x to i8 + store volatile i8 %frombool1, i8* %x2, align 1 + %0 = load i64, i64* @y, align 8 + %tobool3 = icmp eq i64 %0, 0 + br label %for.body + +for.body: + %i.01 = phi i32 [ 0, %entry ], [ %inc, %for.inc ] + %x2.0. = load volatile i8, i8* %x2, align 1 + %tobool2 = icmp eq i8 %x2.0., 0 + br i1 %tobool2, label %for.inc, label %if.then + +if.then: + br i1 %tobool3, label %if.else, label %if.then4 + +if.then4: + store volatile i32 %p, i32* @sink, align 4 + br label %for.inc + +if.else: + store volatile i32 %q, i32* @sink, align 4 + br label %for.inc + +for.inc: + %inc = add nsw i32 %i.01, 1 + %cmp = icmp slt i32 %inc, 1 + br i1 %cmp, label %for.body, label %for.end + +for.end: + ret void +} + + +; The same as above, but "y" is a function parameter instead of a global. +; This shows that it is not enough to suppress hoisting of load instructions, +; the actual problem is in the speculative branching. + +define void @may_not_execute2(i1 zeroext %x, i1 zeroext %y, i32 %p, i32 %q) sanitize_memory { +; CHECK-LABEL: @may_not_execute2( +entry: +; CHECK-NOT: br i1 +; CHECK: br label +; CHECK: br i1 %y, + %x2 = alloca i8, align 1 + %frombool2 = zext i1 %x to i8 + store volatile i8 %frombool2, i8* %x2, align 1 + br label %for.body + +for.body: + %i.01 = phi i32 [ 0, %entry ], [ %inc, %for.inc ] + %x2.0. = load volatile i8, i8* %x2, align 1 + %tobool3 = icmp eq i8 %x2.0., 0 + br i1 %tobool3, label %for.inc, label %if.then + +if.then: + br i1 %y, label %if.then5, label %if.else + +if.then5: + store volatile i32 %p, i32* @sink, align 4 + br label %for.inc + +if.else: + store volatile i32 %q, i32* @sink, align 4 + br label %for.inc + +for.inc: + %inc = add nsw i32 %i.01, 1 + %cmp = icmp slt i32 %inc, 1 + br i1 %cmp, label %for.body, label %for.end + +for.end: + ret void +} + + +; The following is approximately: +; void f(bool x, int p, int q) { +; volatile bool x2 = x; +; for (int i = 0; i < 1; ++i) { +; if (y) +; sink = p; +; else +; sink = q; +; } +; } +; "if (y)" is guaranteed to execute; the loop can be unswitched. + +define void @must_execute(i1 zeroext %x, i32 %p, i32 %q) sanitize_memory { +; CHECK-LABEL: @must_execute( +entry: +; CHECK: %[[Y:.*]] = load i64, i64* @y, align 8 +; CHECK-NEXT: %[[YB:.*]] = icmp eq i64 %[[Y]], 0 +; CHECK-NEXT: br i1 %[[YB]], + + %x2 = alloca i8, align 1 + %frombool1 = zext i1 %x to i8 + store volatile i8 %frombool1, i8* %x2, align 1 + %0 = load i64, i64* @y, align 8 + %tobool2 = icmp eq i64 %0, 0 + br label %for.body + +for.body: + %i.01 = phi i32 [ 0, %entry ], [ %inc, %for.inc ] + br i1 %tobool2, label %if.else, label %if.then + +if.then: + store volatile i32 %p, i32* @sink, align 4 + br label %for.inc + +if.else: + store volatile i32 %q, i32* @sink, align 4 + br label %for.inc + +for.inc: + %inc = add nsw i32 %i.01, 1 + %cmp = icmp slt i32 %inc, 1 + br i1 %cmp, label %for.body, label %for.end + +for.end: + ret void +} diff --git a/llvm/test/Transforms/LoopUnswitch/pr32818.ll b/llvm/test/Transforms/LoopUnswitch/pr32818.ll new file mode 100644 index 00000000000..ed33494f59c --- /dev/null +++ b/llvm/test/Transforms/LoopUnswitch/pr32818.ll @@ -0,0 +1,20 @@ +; Check that the call doesn't get removed even if +; it has no uses. It could have side-effects. +; RUN: opt -loop-unswitch -S %s | FileCheck %s +; RUN: opt -loop-unswitch -enable-mssa-loop-dependency=true -verify-memoryssa -S %s | FileCheck %s + +; CHECK-LABEL: @tinky +define i32 @tinkywinky(i8 %patatino) { + %cmp1 = icmp slt i8 %patatino, 5 + br label %body +body: + %i = select i1 %cmp1, i8 6, i8 undef + br i1 true, label %body, label %end +end: + %split = phi i8 [ %i, %body ] + %conv4 = sext i8 %split to i32 +; CHECK: tail call fastcc i32 @fn5( + %call = tail call fastcc i32 @fn5(i32 %conv4) + ret i32 0 +} +declare fastcc i32 @fn5(i32 returned) unnamed_addr diff --git a/llvm/test/Transforms/LoopUnswitch/preserve-analyses.ll b/llvm/test/Transforms/LoopUnswitch/preserve-analyses.ll new file mode 100644 index 00000000000..d731fba34a1 --- /dev/null +++ b/llvm/test/Transforms/LoopUnswitch/preserve-analyses.ll @@ -0,0 +1,130 @@ +; RUN: opt -loop-unswitch -verify-loop-info -verify-dom-info -disable-output < %s +; RUN: opt -loop-unswitch -enable-mssa-loop-dependency=true -verify-memoryssa -verify-loop-info -verify-dom-info -disable-output < %s + +; Loop unswitch should be able to unswitch these loops and +; preserve LCSSA and LoopSimplify forms. + +target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:64" +target triple = "armv6-apple-darwin9" + +@delim1 = external global i32 ; <i32*> [#uses=1] +@delim2 = external global i32 ; <i32*> [#uses=1] + +define i32 @ineqn(i8* %s, i8* %p) nounwind readonly { +entry: + %0 = load i32, i32* @delim1, align 4 ; <i32> [#uses=1] + %1 = load i32, i32* @delim2, align 4 ; <i32> [#uses=1] + br label %bb8.outer + +bb: ; preds = %bb8 + %2 = icmp eq i8* %p_addr.0, %s ; <i1> [#uses=1] + br i1 %2, label %bb10, label %bb2 + +bb2: ; preds = %bb + %3 = getelementptr inbounds i8, i8* %p_addr.0, i32 1 ; <i8*> [#uses=3] + switch i32 %ineq.0.ph, label %bb8.backedge [ + i32 0, label %bb3 + i32 1, label %bb6 + ] + +bb8.backedge: ; preds = %bb6, %bb5, %bb2 + br label %bb8 + +bb3: ; preds = %bb2 + %4 = icmp eq i32 %8, %0 ; <i1> [#uses=1] + br i1 %4, label %bb8.outer.loopexit, label %bb5 + +bb5: ; preds = %bb3 + br i1 %6, label %bb6, label %bb8.backedge + +bb6: ; preds = %bb5, %bb2 + %5 = icmp eq i32 %8, %1 ; <i1> [#uses=1] + br i1 %5, label %bb7, label %bb8.backedge + +bb7: ; preds = %bb6 + %.lcssa1 = phi i8* [ %3, %bb6 ] ; <i8*> [#uses=1] + br label %bb8.outer.backedge + +bb8.outer.backedge: ; preds = %bb8.outer.loopexit, %bb7 + %.lcssa2 = phi i8* [ %.lcssa1, %bb7 ], [ %.lcssa, %bb8.outer.loopexit ] ; <i8*> [#uses=1] + %ineq.0.ph.be = phi i32 [ 0, %bb7 ], [ 1, %bb8.outer.loopexit ] ; <i32> [#uses=1] + br label %bb8.outer + +bb8.outer.loopexit: ; preds = %bb3 + %.lcssa = phi i8* [ %3, %bb3 ] ; <i8*> [#uses=1] + br label %bb8.outer.backedge + +bb8.outer: ; preds = %bb8.outer.backedge, %entry + %ineq.0.ph = phi i32 [ 0, %entry ], [ %ineq.0.ph.be, %bb8.outer.backedge ] ; <i32> [#uses=3] + %p_addr.0.ph = phi i8* [ %p, %entry ], [ %.lcssa2, %bb8.outer.backedge ] ; <i8*> [#uses=1] + %6 = icmp eq i32 %ineq.0.ph, 1 ; <i1> [#uses=1] + br label %bb8 + +bb8: ; preds = %bb8.outer, %bb8.backedge + %p_addr.0 = phi i8* [ %p_addr.0.ph, %bb8.outer ], [ %3, %bb8.backedge ] ; <i8*> [#uses=3] + %7 = load i8, i8* %p_addr.0, align 1 ; <i8> [#uses=2] + %8 = sext i8 %7 to i32 ; <i32> [#uses=2] + %9 = icmp eq i8 %7, 0 ; <i1> [#uses=1] + br i1 %9, label %bb10, label %bb + +bb10: ; preds = %bb8, %bb + %.0 = phi i32 [ %ineq.0.ph, %bb ], [ 0, %bb8 ] ; <i32> [#uses=1] + ret i32 %.0 +} + +; This is a simplified form of ineqn from above. It triggers some +; different cases in the loop-unswitch code. + +define void @simplified_ineqn() nounwind readonly { +entry: + br label %bb8.outer + +bb8.outer: ; preds = %bb6, %bb2, %entry + %x = phi i32 [ 0, %entry ], [ 0, %bb6 ], [ 1, %bb2 ] ; <i32> [#uses=1] + br i1 undef, label %return, label %bb2 + +bb2: ; preds = %bb + switch i32 %x, label %bb6 [ + i32 0, label %bb8.outer + ] + +bb6: ; preds = %bb2 + br i1 undef, label %bb8.outer, label %bb2 + +return: ; preds = %bb8, %bb + ret void +} + +; This function requires special handling to preserve LCSSA form. +; PR4934 + +define void @pnp_check_irq() nounwind noredzone { +entry: + %conv56 = trunc i64 undef to i32 ; <i32> [#uses=1] + br label %while.cond.i + +while.cond.i: ; preds = %while.cond.i.backedge, %entry + %call.i25 = call i8* @pci_get_device() nounwind noredzone ; <i8*> [#uses=2] + br i1 undef, label %if.then65, label %while.body.i + +while.body.i: ; preds = %while.cond.i + br i1 undef, label %if.then31.i.i, label %while.cond.i.backedge + +while.cond.i.backedge: ; preds = %if.then31.i.i, %while.body.i + br label %while.cond.i + +if.then31.i.i: ; preds = %while.body.i + switch i32 %conv56, label %while.cond.i.backedge [ + i32 14, label %if.then42.i.i + i32 15, label %if.then42.i.i + ] + +if.then42.i.i: ; preds = %if.then31.i.i, %if.then31.i.i + %call.i25.lcssa48 = phi i8* [ %call.i25, %if.then31.i.i ], [ %call.i25, %if.then31.i.i ] ; <i8*> [#uses=0] + unreachable + +if.then65: ; preds = %while.cond.i + unreachable +} + +declare i8* @pci_get_device() noredzone diff --git a/llvm/test/Transforms/LoopUnswitch/simplify-with-nonvalness.ll b/llvm/test/Transforms/LoopUnswitch/simplify-with-nonvalness.ll new file mode 100644 index 00000000000..d2436f06e0c --- /dev/null +++ b/llvm/test/Transforms/LoopUnswitch/simplify-with-nonvalness.ll @@ -0,0 +1,59 @@ +; RUN: opt < %s -loop-unswitch -verify-loop-info -S < %s 2>&1 | FileCheck %s +; RUN: opt < %s -loop-unswitch -verify-loop-info -enable-mssa-loop-dependency=true -verify-memoryssa -S < %s 2>&1 | FileCheck %s + +; There are 1 case and 1 default case in the switch. after we unswitch, we know the +; %a is definitely not 0 in one of the unswitched loop, make sure we take advantage +; of that and simplify the branches in the loop. +; +; CHECK: define void @simplify_with_nonvalness( + +; This is the loop in which we know %a is definitely 0. +; CHECK: sw.bb.us: +; CHECK: br i1 true, label %if.then.us, label %if.end.us + +; This is the loop in which we do not know what %a is but we know %a is definitely NOT 0. +; Make sure we use that information to simplify. +; The icmp eq i32 %a, 0 in one of the unswitched loop is simplified to false. +; CHECK: sw.bb.split: +; CHECK: br i1 false, label %if.then, label %if.end + +define void @simplify_with_nonvalness(i32 %a) #0 { +entry: + br label %for.cond + +for.cond: + %i.0 = phi i32 [ 0, %entry ], [ %inc, %for.inc ] + %cmp = icmp slt i32 %i.0, 1024 + br i1 %cmp, label %for.body, label %for.end + +for.body: + switch i32 %a, label %sw.default [ + i32 0, label %sw.bb + ] + +sw.bb: + %cmp1 = icmp eq i32 %a, 0 + br i1 %cmp1, label %if.then, label %if.end + +if.then: + call void (...) @bar() + br label %if.end + +if.end: + br label %sw.epilog + +sw.default: + br label %sw.epilog + +sw.epilog: + br label %for.inc + +for.inc: + %inc = add nsw i32 %i.0, 1 + br label %for.cond + +for.end: + ret void +} + +declare void @bar(...) diff --git a/llvm/test/Transforms/LoopUnswitch/trivial-unswitch.ll b/llvm/test/Transforms/LoopUnswitch/trivial-unswitch.ll new file mode 100644 index 00000000000..c820a53d991 --- /dev/null +++ b/llvm/test/Transforms/LoopUnswitch/trivial-unswitch.ll @@ -0,0 +1,92 @@ +; RUN: opt < %s -loop-unswitch -loop-unswitch-threshold=0 -verify-loop-info -S < %s 2>&1 | FileCheck %s +; RUN: opt < %s -loop-unswitch -loop-unswitch-threshold=0 -verify-loop-info -enable-mssa-loop-dependency=true -verify-memoryssa -S < %s 2>&1 | FileCheck %s + +; This test contains two trivial unswitch condition in one loop. +; LoopUnswitch pass should be able to unswitch the second one +; after unswitching the first one. + + +; CHECK: br i1 %cond1, label %..split_crit_edge, label %.loop_exit.split_crit_edge + +; CHECK: ..split_crit_edge: ; preds = %0 +; CHECK: br label %.split + +; CHECK: .split: ; preds = %..split_crit_edge +; CHECK: br i1 %cond2, label %.split..split.split_crit_edge, label %.split.loop_exit.split1_crit_edge + +; CHECK: .split..split.split_crit_edge: ; preds = %.split +; CHECK: br label %.split.split + +; CHECK: .split.split: ; preds = %.split..split.split_crit_edge +; CHECK: br label %loop_begin + +; CHECK: loop_begin: ; preds = %do_something, %.split.split +; CHECK: br i1 true, label %continue, label %loop_exit + +; CHECK: continue: ; preds = %loop_begin +; CHECK: %var_val = load i32, i32* %var +; CHECK: br i1 true, label %do_something, label %loop_exit + +define i32 @test(i32* %var, i1 %cond1, i1 %cond2) { + br label %loop_begin + +loop_begin: + br i1 %cond1, label %continue, label %loop_exit ; first trivial condition + +continue: + %var_val = load i32, i32* %var + br i1 %cond2, label %do_something, label %loop_exit ; second trivial condition + +do_something: + call void @some_func() noreturn nounwind + br label %loop_begin + +loop_exit: + ret i32 0 +} + + +; We will not be able trivially unswitch on the SwitchInst, as its input +; is a constant. However, since its a constant we should be able to figure +; out that the switch can be folded into a unconditional branch to %continue. +; Then we unswitch on the br inst in %continue. +; +; CHECK: define i32 @test2( +; This is an indication that the loop has been unswitched on %cond1. +; CHECK: br i1 %cond1, label %..split_crit_edge, label %.loop_exit.split_crit_edge + +; CHECK: ..split_crit_edge: ; preds = %0 +; CHECK: br label %.split + +; CHECK: .split: ; preds = %..split_crit_edge +; CHECK: br label %loop_begin + +; CHECK: loop_begin: ; preds = %do_something, %.split +; CHECK: switch i32 + +; CHECK: continue: ; preds = %loop_begin +; CHECK: %var_val = load i32, i32* %var +; CHECK: br i1 true, label %do_something, label %loop_exit + +define i32 @test2(i32* %var, i1 %cond1) { + br label %loop_begin + +loop_begin: + switch i32 1, label %continue [ + i32 0, label %loop_exit + i32 1, label %continue + ] + +continue: + %var_val = load i32, i32* %var + br i1 %cond1, label %do_something, label %loop_exit + +do_something: + call void @some_func() noreturn nounwind + br label %loop_begin + +loop_exit: + ret i32 0 +} + +declare void @some_func() noreturn diff --git a/llvm/test/Transforms/LoopUnswitch/unswitch-equality-undef.ll b/llvm/test/Transforms/LoopUnswitch/unswitch-equality-undef.ll new file mode 100644 index 00000000000..c6b49c7281d --- /dev/null +++ b/llvm/test/Transforms/LoopUnswitch/unswitch-equality-undef.ll @@ -0,0 +1,122 @@ +; REQUIRES: asserts +; RUN: opt < %s -instcombine -licm -loop-unswitch -loop-unswitch-threshold=1000 -enable-mssa-loop-dependency=true -verify-memoryssa -disable-output -stats 2>&1| FileCheck %s +; Check no loop unswitch is done because unswitching of equality expr with +; undef is unsafe before the freeze patch is committed. +; CHECK-NOT: Number of branches unswitched + +define void @ham(i64 %arg) local_unnamed_addr { +bb: + %tmp = icmp eq i64 %arg, 0 + br i1 %tmp, label %bb3, label %bb1 + +bb1: ; preds = %bb + %tmp2 = load volatile i64, i64* @global, align 8 + br label %bb3 + +bb3: ; preds = %bb1, %bb + %tmp4 = phi i64 [ %tmp2, %bb1 ], [ undef, %bb ] + %tmp5 = load i64, i64* @global.1, align 8 + br label %bb6 + +bb6: ; preds = %bb21, %bb3 + %tmp7 = phi i64 [ 3, %bb21 ], [ %tmp5, %bb3 ] + %tmp8 = phi i64 [ %tmp25, %bb21 ], [ 0, %bb3 ] + %tmp9 = icmp eq i64 %tmp7, %arg + br i1 %tmp9, label %bb10, label %bb28 + +bb10: ; preds = %bb6 + %tmp11 = icmp eq i64 %tmp7, 0 + br i1 %tmp11, label %bb21, label %bb12 + +bb12: ; preds = %bb10 + %tmp13 = load i64, i64* @global.2, align 8 + %tmp14 = add nsw i64 %tmp13, 1 + store i64 %tmp14, i64* @global.2, align 8 + %tmp15 = load i64, i64* @global.3, align 8 + %tmp16 = icmp eq i64 %tmp15, %tmp4 + br i1 %tmp16, label %bb17, label %bb21 + +bb17: ; preds = %bb12 + %tmp18 = phi i64 [ %tmp15, %bb12 ] + %tmp19 = load i64, i64* @global.4, align 8 + %tmp20 = add nsw i64 %tmp19, %tmp18 + store i64 %tmp20, i64* @global.5, align 8 + br label %bb29 + +bb21: ; preds = %bb12, %bb10 + %tmp22 = load i64, i64* @global.3, align 8 + %tmp23 = load volatile i64, i64* @global, align 8 + %tmp24 = add nsw i64 %tmp23, %tmp22 + store i64 %tmp24, i64* @global.5, align 8 + store i64 3, i64* @global.1, align 8 + %tmp25 = add nsw i64 %tmp8, 1 + %tmp26 = load i64, i64* @global.6, align 8 + %tmp27 = icmp slt i64 %tmp25, %tmp26 + br i1 %tmp27, label %bb6, label %bb28 + +bb28: ; preds = %bb21, %bb6 + br label %bb29 + +bb29: ; preds = %bb28, %bb17 + ret void +} + +define void @zot(i64 %arg, i64 %arg1) local_unnamed_addr { +bb: + %tmp = icmp eq i64 %arg, 0 + %tmp2 = select i1 %tmp, i64 %arg1, i64 undef + %tmp3 = load i64, i64* @global.1, align 8 + br label %bb4 + +bb4: ; preds = %bb19, %bb + %tmp5 = phi i64 [ 3, %bb19 ], [ %tmp3, %bb ] + %tmp6 = phi i64 [ %tmp23, %bb19 ], [ 0, %bb ] + %tmp7 = icmp eq i64 %tmp5, %arg + br i1 %tmp7, label %bb8, label %bb26 + +bb8: ; preds = %bb4 + %tmp9 = icmp eq i64 %tmp5, 0 + br i1 %tmp9, label %bb19, label %bb10 + +bb10: ; preds = %bb8 + %tmp11 = load i64, i64* @global.2, align 8 + %tmp12 = add nsw i64 %tmp11, 1 + store i64 %tmp12, i64* @global.2, align 8 + %tmp13 = load i64, i64* @global.3, align 8 + %tmp14 = icmp eq i64 %tmp13, %tmp2 + br i1 %tmp14, label %bb15, label %bb19 + +bb15: ; preds = %bb10 + %tmp16 = phi i64 [ %tmp13, %bb10 ] + %tmp17 = load i64, i64* @global.4, align 8 + %tmp18 = add nsw i64 %tmp17, %tmp16 + store i64 %tmp18, i64* @global.5, align 8 + br label %bb27 + +bb19: ; preds = %bb10, %bb8 + %tmp20 = load i64, i64* @global.3, align 8 + %tmp21 = load volatile i64, i64* @global, align 8 + %tmp22 = add nsw i64 %tmp21, %tmp20 + store i64 %tmp22, i64* @global.5, align 8 + store i64 3, i64* @global.1, align 8 + %tmp23 = add nsw i64 %tmp6, 1 + %tmp24 = load i64, i64* @global.6, align 8 + %tmp25 = icmp slt i64 %tmp23, %tmp24 + br i1 %tmp25, label %bb4, label %bb26 + +bb26: ; preds = %bb19, %bb4 + br label %bb27 + +bb27: ; preds = %bb26, %bb15 + ret void +} + +@global = common global i64 0, align 8 +@global.1 = common global i64 0, align 8 +@global.2 = common global i64 0, align 8 +@global.3 = common global i64 0, align 8 +@global.4 = common global i64 0, align 8 +@global.5 = common global i64 0, align 8 +@global.6 = common global i64 0, align 8 + + diff --git a/llvm/test/Transforms/LoopUnswitch/unswitch-select.ll b/llvm/test/Transforms/LoopUnswitch/unswitch-select.ll new file mode 100644 index 00000000000..7b62587f53f --- /dev/null +++ b/llvm/test/Transforms/LoopUnswitch/unswitch-select.ll @@ -0,0 +1,27 @@ +; REQUIRES: asserts +; RUN: opt < %s -loop-unswitch -disable-output -stats 2>&1| FileCheck %s +; RUN: opt < %s -loop-unswitch -enable-mssa-loop-dependency=true -verify-memoryssa -disable-output -stats 2>&1| FileCheck %s + +; Check the select statement in the loop will be unswitched. +; CHECK: 1 loop-unswitch - Number of selects unswitched +define i32 @test(i1 zeroext %x, i32 %a) local_unnamed_addr #0 { +entry: + br label %while.cond + +while.cond: ; preds = %while.body, %entry + %i.0 = phi i32 [ 0, %entry ], [ %inc, %while.body ] + %s.0 = phi i32 [ %a, %entry ], [ %add, %while.body ] + %cmp = icmp slt i32 %i.0, 10000 + br i1 %cmp, label %while.body, label %while.end + +while.body: ; preds = %while.cond + %cond = select i1 %x, i32 %a, i32 %i.0 + %add = add nsw i32 %s.0, %cond + %inc = add nsw i32 %i.0, 1 + br label %while.cond + +while.end: ; preds = %while.cond + %s.0.lcssa = phi i32 [ %s.0, %while.cond ] + ret i32 %s.0.lcssa +} + |
