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| author | David Blaikie <dblaikie@gmail.com> | 2015-02-27 21:17:42 +0000 |
|---|---|---|
| committer | David Blaikie <dblaikie@gmail.com> | 2015-02-27 21:17:42 +0000 |
| commit | a79ac14fa68297f9888bc70a10df5ed9b8864e38 (patch) | |
| tree | 8d8217a8928e3ee599bdde405e2e178b3a55b645 /llvm/test/Transforms/LoopUnswitch/2011-11-18-SimpleSwitch.ll | |
| parent | 83687fb9e654c9d0086e7f6b728c26fa0b729e71 (diff) | |
| download | bcm5719-llvm-a79ac14fa68297f9888bc70a10df5ed9b8864e38.tar.gz bcm5719-llvm-a79ac14fa68297f9888bc70a10df5ed9b8864e38.zip | |
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction
Essentially the same as the GEP change in r230786.
A similar migration script can be used to update test cases, though a few more
test case improvements/changes were required this time around: (r229269-r229278)
import fileinput
import sys
import re
pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)")
for line in sys.stdin:
sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line))
Reviewers: rafael, dexonsmith, grosser
Differential Revision: http://reviews.llvm.org/D7649
llvm-svn: 230794
Diffstat (limited to 'llvm/test/Transforms/LoopUnswitch/2011-11-18-SimpleSwitch.ll')
| -rw-r--r-- | llvm/test/Transforms/LoopUnswitch/2011-11-18-SimpleSwitch.ll | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/llvm/test/Transforms/LoopUnswitch/2011-11-18-SimpleSwitch.ll b/llvm/test/Transforms/LoopUnswitch/2011-11-18-SimpleSwitch.ll index a8608b87720..a35596aff11 100644 --- a/llvm/test/Transforms/LoopUnswitch/2011-11-18-SimpleSwitch.ll +++ b/llvm/test/Transforms/LoopUnswitch/2011-11-18-SimpleSwitch.ll @@ -15,7 +15,7 @@ ; CHECK-NEXT: br label %loop_begin.us ; CHECK: loop_begin.us: ; preds = %loop_begin.backedge.us, %.split.us -; CHECK-NEXT: %var_val.us = load i32* %var +; CHECK-NEXT: %var_val.us = load i32, i32* %var ; CHECK-NEXT: switch i32 1, label %default.us-lcssa.us [ ; CHECK-NEXT: i32 1, label %inc.us @@ -34,7 +34,7 @@ ; CHECK-NEXT: br label %loop_begin.us1 ; CHECK: loop_begin.us1: ; preds = %loop_begin.backedge.us5, %.split.split.us -; CHECK-NEXT: %var_val.us2 = load i32* %var +; CHECK-NEXT: %var_val.us2 = load i32, i32* %var ; CHECK-NEXT: switch i32 2, label %default.us-lcssa.us-lcssa.us [ ; CHECK-NEXT: i32 1, label %inc.us4 ; CHECK-NEXT: i32 2, label %dec.us3 @@ -48,7 +48,7 @@ ; CHECK-NEXT: br label %loop_begin ; CHECK: loop_begin: ; preds = %loop_begin.backedge, %.split.split -; CHECK-NEXT: %var_val = load i32* %var +; CHECK-NEXT: %var_val = load i32, i32* %var ; CHECK-NEXT: switch i32 %c, label %default.us-lcssa.us-lcssa [ ; CHECK-NEXT: i32 1, label %inc ; CHECK-NEXT: i32 2, label %dec @@ -63,13 +63,13 @@ define i32 @test(i32* %var) { %mem = alloca i32 store i32 2, i32* %mem - %c = load i32* %mem + %c = load i32, i32* %mem br label %loop_begin loop_begin: - %var_val = load i32* %var + %var_val = load i32, i32* %var switch i32 %c, label %default [ i32 1, label %inc |
