summaryrefslogtreecommitdiffstats
path: root/llvm/test/Transforms/LoopStrengthReduce/X86
diff options
context:
space:
mode:
authorFlorian Hahn <flo@fhahn.com>2019-03-15 12:17:36 +0000
committerFlorian Hahn <flo@fhahn.com>2019-03-15 12:17:36 +0000
commitd9e88f7b7fef8f1a3dd48cf245365b65cc330eb5 (patch)
tree429c533d7d2cb5fd6e15e2c8fdb88645b83b4ef0 /llvm/test/Transforms/LoopStrengthReduce/X86
parent04188fc0c6e61b62f2c8efde620d637bd7caf926 (diff)
downloadbcm5719-llvm-d9e88f7b7fef8f1a3dd48cf245365b65cc330eb5.tar.gz
bcm5719-llvm-d9e88f7b7fef8f1a3dd48cf245365b65cc330eb5.zip
[LSR] Check for signed overflow in NarrowSearchSpaceByDetectingSupersets.
We are adding a sign extended IR value to an int64_t, which can cause signed overflows, as in the attached test case, where we have a formula with BaseOffset = -1 and a constant with numeric_limits<int64_t>::min(). If the addition would overflow, skip the simplification for this formula. Note that the target triple is required to trigger the failure. Reviewers: qcolombet, gilr, kparzysz, efriedma Reviewed By: efriedma Differential Revision: https://reviews.llvm.org/D59211 llvm-svn: 356256
Diffstat (limited to 'llvm/test/Transforms/LoopStrengthReduce/X86')
-rw-r--r--llvm/test/Transforms/LoopStrengthReduce/X86/lsr-overflow.ll38
1 files changed, 38 insertions, 0 deletions
diff --git a/llvm/test/Transforms/LoopStrengthReduce/X86/lsr-overflow.ll b/llvm/test/Transforms/LoopStrengthReduce/X86/lsr-overflow.ll
new file mode 100644
index 00000000000..4109dfcd2e0
--- /dev/null
+++ b/llvm/test/Transforms/LoopStrengthReduce/X86/lsr-overflow.ll
@@ -0,0 +1,38 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt -lsr-complexity-limit=50 -loop-reduce -S %s | FileCheck %s
+
+target triple = "x86_64-apple-macosx10.14.0"
+target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
+
+define void @overflow1(i64 %a) {
+; CHECK-LABEL: @overflow1(
+; CHECK-NEXT: bb:
+; CHECK-NEXT: br label [[BB1:%.*]]
+; CHECK: bb1:
+; CHECK-NEXT: [[TMP:%.*]] = phi i64 [ [[A:%.*]], [[BB:%.*]] ], [ [[TMP6:%.*]], [[BB1]] ]
+; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[TMP]], -9223372036854775808
+; CHECK-NEXT: [[TMP4:%.*]] = icmp ne i64 [[TMP0]], 0
+; CHECK-NEXT: [[TMP5:%.*]] = and i1 [[TMP4]], true
+; CHECK-NEXT: [[TMP6]] = add i64 [[TMP]], 1
+; CHECK-NEXT: br i1 [[TMP5]], label [[BB1]], label [[BB7:%.*]]
+; CHECK: bb7:
+; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[TMP6]], -1
+; CHECK-NEXT: [[TMP9:%.*]] = and i64 [[TMP1]], 1
+; CHECK-NEXT: [[TMP10:%.*]] = icmp eq i64 [[TMP9]], 0
+; CHECK-NEXT: unreachable
+;
+bb:
+ br label %bb1
+
+bb1: ; preds = %bb1, %bb
+ %tmp = phi i64 [ %a, %bb ], [ %tmp6, %bb1 ]
+ %tmp4 = icmp ne i64 %tmp, -9223372036854775808
+ %tmp5 = and i1 %tmp4, 1
+ %tmp6 = add i64 %tmp, 1
+ br i1 %tmp5, label %bb1, label %bb7
+
+bb7: ; preds = %bb1
+ %tmp9 = and i64 %tmp, 1
+ %tmp10 = icmp eq i64 %tmp9, 0
+ unreachable
+}
OpenPOWER on IntegriCloud