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| author | Hans Wennborg <hans@hanshq.net> | 2017-10-04 17:54:06 +0000 |
|---|---|---|
| committer | Hans Wennborg <hans@hanshq.net> | 2017-10-04 17:54:06 +0000 |
| commit | 2a6c9adb2f30f725579bcc8922583798a5b0feea (patch) | |
| tree | 63dd6580649e5d0d4bbb7c9d1018f108ab348ca2 /llvm/test/Transforms/LoopStrengthReduce/X86 | |
| parent | 084400bad95254f612c2eb0bbd4a614b01ca2a66 (diff) | |
| download | bcm5719-llvm-2a6c9adb2f30f725579bcc8922583798a5b0feea.tar.gz bcm5719-llvm-2a6c9adb2f30f725579bcc8922583798a5b0feea.zip | |
Revert r314886 "[X86] Improvement in CodeGen instruction selection for LEAs (re-applying post required revision changes.)"
It broke the Chromium / SQLite build; see PR34830.
> Summary:
> 1/ Operand folding during complex pattern matching for LEAs has been
> extended, such that it promotes Scale to accommodate similar operand
> appearing in the DAG.
> e.g.
> T1 = A + B
> T2 = T1 + 10
> T3 = T2 + A
> For above DAG rooted at T3, X86AddressMode will no look like
> Base = B , Index = A , Scale = 2 , Disp = 10
>
> 2/ During OptimizeLEAPass down the pipeline factorization is now performed over LEAs
> so that if there is an opportunity then complex LEAs (having 3 operands)
> could be factored out.
> e.g.
> leal 1(%rax,%rcx,1), %rdx
> leal 1(%rax,%rcx,2), %rcx
> will be factored as following
> leal 1(%rax,%rcx,1), %rdx
> leal (%rdx,%rcx) , %edx
>
> 3/ Aggressive operand folding for AM based selection for LEAs is sensitive to loops,
> thus avoiding creation of any complex LEAs within a loop.
>
> Reviewers: lsaba, RKSimon, craig.topper, qcolombet, jmolloy
>
> Reviewed By: lsaba
>
> Subscribers: jmolloy, spatel, igorb, llvm-commits
>
> Differential Revision: https://reviews.llvm.org/D35014
llvm-svn: 314919
Diffstat (limited to 'llvm/test/Transforms/LoopStrengthReduce/X86')
| -rw-r--r-- | llvm/test/Transforms/LoopStrengthReduce/X86/ivchain-X86.ll | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/llvm/test/Transforms/LoopStrengthReduce/X86/ivchain-X86.ll b/llvm/test/Transforms/LoopStrengthReduce/X86/ivchain-X86.ll index 3f6d234c929..7c01432914f 100644 --- a/llvm/test/Transforms/LoopStrengthReduce/X86/ivchain-X86.ll +++ b/llvm/test/Transforms/LoopStrengthReduce/X86/ivchain-X86.ll @@ -13,14 +13,14 @@ ; X64-NEXT: .p2align ; X64: %loop ; no complex address modes -; X64-NOT: [1-9]+(%{{[^)]+}},%{{[^)]+}}, +; X64-NOT: (%{{[^)]+}},%{{[^)]+}}, ; ; X32: @simple ; no expensive address computation in the preheader ; X32-NOT: imul ; X32: %loop ; no complex address modes -; X32-NOT: [1-9]+(%{{[^)]+}},%{{[^)]+}}, +; X32-NOT: (%{{[^)]+}},%{{[^)]+}}, define i32 @simple(i32* %a, i32* %b, i32 %x) nounwind { entry: br label %loop @@ -103,7 +103,7 @@ exit: ; X32-NOT: mov{{.*}}(%esp){{$}} ; X32: %for.body{{$}} ; no complex address modes -; X32-NOT: [1-9]+(%{{[^)]+}},%{{[^)]+}}, +; X32-NOT: (%{{[^)]+}},%{{[^)]+}}, ; no reloads ; X32-NOT: (%esp) define void @extrastride(i8* nocapture %main, i32 %main_stride, i32* nocapture %res, i32 %x, i32 %y, i32 %z) nounwind { |
