Temporarily Revert "Add basic loop fusion pass."

As it's causing some bot failures (and per request from kbarton).

This reverts commit r358543/ab70da07286e618016e78247e4a24fcb84077fda.

llvm-svn: 358546

10 files changed, 0 insertions, 3485 deletions

diff --git a/llvm/test/Transforms/LoopSimplifyCFG/constant-fold-branch.ll b/llvm/test/Transforms/LoopSimplifyCFG/constant-fold-branch.ll
deleted file mode 100644
index b2f0f33496a..00000000000
--- a/llvm/test/Transforms/LoopSimplifyCFG/constant-fold-branch.ll
+++ /dev/null
@@ -1,2774 +0,0 @@
-; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; REQUIRES: asserts
-; RUN: opt -S -enable-loop-simplifycfg-term-folding=true -loop-simplifycfg -verify-loop-info -verify-dom-info -verify-loop-lcssa < %s | FileCheck %s
-; RUN: opt -S -enable-loop-simplifycfg-term-folding=true -passes='require<domtree>,loop(simplify-cfg)' -verify-loop-info -verify-dom-info -verify-loop-lcssa < %s | FileCheck %s
-; RUN: opt -S -enable-loop-simplifycfg-term-folding=true -loop-simplifycfg -enable-mssa-loop-dependency=true -verify-memoryssa -verify-loop-info -verify-dom-info -verify-loop-lcssa < %s | FileCheck %s
-
-target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128-ni:1"
-
-; Make sure that we can eliminate a provably dead backedge.
-define i32 @dead_backedge_test_branch_loop(i32 %end) {
-; CHECK-LABEL: @dead_backedge_test_branch_loop(
-; CHECK-NEXT:  preheader:
-; CHECK-NEXT:    br label [[HEADER:%.*]]
-; CHECK:       header:
-; CHECK-NEXT:    [[I:%.*]] = phi i32 [ 0, [[PREHEADER:%.*]] ], [ [[I_BE:%.*]], [[HEADER_BACKEDGE:%.*]] ]
-; CHECK-NEXT:    [[I_1:%.*]] = add i32 [[I]], 1
-; CHECK-NEXT:    [[CMP1:%.*]] = icmp slt i32 [[I_1]], 100
-; CHECK-NEXT:    br i1 [[CMP1]], label [[HEADER_BACKEDGE]], label [[DEAD_BACKEDGE:%.*]]
-; CHECK:       header.backedge:
-; CHECK-NEXT:    [[I_BE]] = phi i32 [ [[I_1]], [[HEADER]] ], [ [[I_2:%.*]], [[DEAD_BACKEDGE]] ]
-; CHECK-NEXT:    br label [[HEADER]]
-; CHECK:       dead_backedge:
-; CHECK-NEXT:    [[I_2]] = add i32 [[I_1]], 10
-; CHECK-NEXT:    br i1 false, label [[HEADER_BACKEDGE]], label [[EXIT:%.*]]
-; CHECK:       exit:
-; CHECK-NEXT:    [[I_2_LCSSA:%.*]] = phi i32 [ [[I_2]], [[DEAD_BACKEDGE]] ]
-; CHECK-NEXT:    ret i32 [[I_2_LCSSA]]
-;
-preheader:
-  br label %header
-
-header:
-  %i = phi i32 [0, %preheader], [%i.1, %header], [%i.2, %dead_backedge]
-  %i.1 = add i32 %i, 1
-  %cmp1 = icmp slt i32 %i.1, 100
-  br i1 %cmp1, label %header, label %dead_backedge
-
-dead_backedge:
-  %i.2 = add i32 %i.1, 10
-  br i1 false, label %header, label %exit
-
-exit:
-  ret i32 %i.2
-}
-
-; Make sure that we can eliminate a provably dead backedge with switch.
-define i32 @dead_backedge_test_switch_loop(i32 %end) {
-; CHECK-LABEL: @dead_backedge_test_switch_loop(
-; CHECK-NEXT:  preheader:
-; CHECK-NEXT:    br label [[HEADER:%.*]]
-; CHECK:       header:
-; CHECK-NEXT:    [[I:%.*]] = phi i32 [ 0, [[PREHEADER:%.*]] ], [ [[I_BE:%.*]], [[HEADER_BACKEDGE:%.*]] ]
-; CHECK-NEXT:    [[I_1:%.*]] = add i32 [[I]], 1
-; CHECK-NEXT:    [[CMP1:%.*]] = icmp slt i32 [[I_1]], 100
-; CHECK-NEXT:    br i1 [[CMP1]], label [[HEADER_BACKEDGE]], label [[DEAD_BACKEDGE:%.*]]
-; CHECK:       header.backedge:
-; CHECK-NEXT:    [[I_BE]] = phi i32 [ [[I_1]], [[HEADER]] ], [ [[I_2:%.*]], [[DEAD_BACKEDGE]] ]
-; CHECK-NEXT:    br label [[HEADER]]
-; CHECK:       dead_backedge:
-; CHECK-NEXT:    [[I_2]] = add i32 [[I_1]], 10
-; CHECK-NEXT:    switch i32 1, label [[EXIT:%.*]] [
-; CHECK-NEXT:    i32 0, label [[HEADER_BACKEDGE]]
-; CHECK-NEXT:    ]
-; CHECK:       exit:
-; CHECK-NEXT:    [[I_2_LCSSA:%.*]] = phi i32 [ [[I_2]], [[DEAD_BACKEDGE]] ]
-; CHECK-NEXT:    ret i32 [[I_2_LCSSA]]
-;
-preheader:
-  br label %header
-
-header:
-  %i = phi i32 [0, %preheader], [%i.1, %header], [%i.2, %dead_backedge]
-  %i.1 = add i32 %i, 1
-  %cmp1 = icmp slt i32 %i.1, 100
-  br i1 %cmp1, label %header, label %dead_backedge
-
-dead_backedge:
-  %i.2 = add i32 %i.1, 10
-  switch i32 1, label %exit [i32 0, label %header]
-
-exit:
-  ret i32 %i.2
-}
-
-; Check that we can eliminate a triangle.
-define i32 @dead_block_test_branch_loop(i32 %end) {
-; CHECK-LABEL: @dead_block_test_branch_loop(
-; CHECK-NEXT:  preheader:
-; CHECK-NEXT:    br label [[HEADER:%.*]]
-; CHECK:       header:
-; CHECK-NEXT:    [[I:%.*]] = phi i32 [ 0, [[PREHEADER:%.*]] ], [ [[I_INC:%.*]], [[HEADER]] ]
-; CHECK-NEXT:    [[I_INC]] = add i32 [[I]], 1
-; CHECK-NEXT:    [[CMP:%.*]] = icmp slt i32 [[I_INC]], [[END:%.*]]
-; CHECK-NEXT:    br i1 [[CMP]], label [[HEADER]], label [[EXIT:%.*]]
-; CHECK:       exit:
-; CHECK-NEXT:    [[I_INC_LCSSA:%.*]] = phi i32 [ [[I_INC]], [[HEADER]] ]
-; CHECK-NEXT:    ret i32 [[I_INC_LCSSA]]
-;
-preheader:
-  br label %header
-
-header:
-  %i = phi i32 [0, %preheader], [%i.inc, %backedge]
-  br i1 true, label %backedge, label %dead
-
-dead:
-  %i.2 = add i32 %i, 1
-  br label %backedge
-
-backedge:
-  %i.1 = phi i32 [%i, %header], [%i.2, %dead]
-  %i.inc = add i32 %i.1, 1
-  %cmp = icmp slt i32 %i.inc, %end
-  br i1 %cmp, label %header, label %exit
-
-exit:
-  ret i32 %i.inc
-}
-
-; Check that we can eliminate dead branches of a switch.
-define i32 @dead_block_test_switch_loop(i32 %end) {
-; CHECK-LABEL: @dead_block_test_switch_loop(
-; CHECK-NEXT:  preheader:
-; CHECK-NEXT:    br label [[HEADER:%.*]]
-; CHECK:       header:
-; CHECK-NEXT:    [[I:%.*]] = phi i32 [ 0, [[PREHEADER:%.*]] ], [ [[I_INC:%.*]], [[HEADER]] ]
-; CHECK-NEXT:    [[I_INC]] = add i32 [[I]], 1
-; CHECK-NEXT:    [[CMP:%.*]] = icmp slt i32 [[I_INC]], [[END:%.*]]
-; CHECK-NEXT:    br i1 [[CMP]], label [[HEADER]], label [[EXIT:%.*]]
-; CHECK:       exit:
-; CHECK-NEXT:    [[I_INC_LCSSA:%.*]] = phi i32 [ [[I_INC]], [[HEADER]] ]
-; CHECK-NEXT:    ret i32 [[I_INC_LCSSA]]
-;
-preheader:
-  br label %header
-
-header:
-  %i = phi i32 [0, %preheader], [%i.inc, %backedge]
-  switch i32 1, label %dead [i32 0, label %dead
-  i32 1, label %backedge
-  i32 2, label %dead]
-
-dead:
-  %i.2 = add i32 %i, 1
-  br label %backedge
-
-backedge:
-  %i.1 = phi i32 [%i, %header], [%i.2, %dead]
-  %i.inc = add i32 %i.1, 1
-  %cmp = icmp slt i32 %i.inc, %end
-  br i1 %cmp, label %header, label %exit
-exit:
-  ret i32 %i.inc
-}
-
-; Check that we can eliminate several dead blocks.
-define i32 @dead_block_propogate_test_branch_loop(i32 %end) {
-; CHECK-LABEL: @dead_block_propogate_test_branch_loop(
-; CHECK-NEXT:  preheader:
-; CHECK-NEXT:    br label [[HEADER:%.*]]
-; CHECK:       header:
-; CHECK-NEXT:    [[I:%.*]] = phi i32 [ 0, [[PREHEADER:%.*]] ], [ [[I_INC:%.*]], [[HEADER]] ]
-; CHECK-NEXT:    [[I_INC]] = add i32 [[I]], 1
-; CHECK-NEXT:    [[CMP:%.*]] = icmp slt i32 [[I_INC]], [[END:%.*]]
-; CHECK-NEXT:    br i1 [[CMP]], label [[HEADER]], label [[EXIT:%.*]]
-; CHECK:       exit:
-; CHECK-NEXT:    [[I_INC_LCSSA:%.*]] = phi i32 [ [[I_INC]], [[HEADER]] ]
-; CHECK-NEXT:    ret i32 [[I_INC_LCSSA]]
-;
-preheader:
-  br label %header
-
-header:
-  %i = phi i32 [0, %preheader], [%i.inc, %backedge]
-  br i1 true, label %backedge, label %dead
-
-dead:
-  %i.2 = add i32 %i, 1
-  br label %dummy
-
-dummy:
-  br label %backedge
-
-backedge:
-  %i.1 = phi i32 [%i, %header], [%i.2, %dummy]
-  %i.inc = add i32 %i.1, 1
-  %cmp = icmp slt i32 %i.inc, %end
-  br i1 %cmp, label %header, label %exit
-
-exit:
-  ret i32 %i.inc
-}
-
-; Check that we can eliminate several blocks while removing a switch.
-define i32 @dead_block_propogate_test_switch_loop(i32 %end) {
-; CHECK-LABEL: @dead_block_propogate_test_switch_loop(
-; CHECK-NEXT:  preheader:
-; CHECK-NEXT:    br label [[HEADER:%.*]]
-; CHECK:       header:
-; CHECK-NEXT:    [[I:%.*]] = phi i32 [ 0, [[PREHEADER:%.*]] ], [ [[I_INC:%.*]], [[HEADER]] ]
-; CHECK-NEXT:    [[I_INC]] = add i32 [[I]], 1
-; CHECK-NEXT:    [[CMP:%.*]] = icmp slt i32 [[I_INC]], [[END:%.*]]
-; CHECK-NEXT:    br i1 [[CMP]], label [[HEADER]], label [[EXIT:%.*]]
-; CHECK:       exit:
-; CHECK-NEXT:    [[I_INC_LCSSA:%.*]] = phi i32 [ [[I_INC]], [[HEADER]] ]
-; CHECK-NEXT:    ret i32 [[I_INC_LCSSA]]
-;
-preheader:
-  br label %header
-
-header:
-  %i = phi i32 [0, %preheader], [%i.inc, %backedge]
-  switch i32 1, label %dead [i32 0, label %dead
-  i32 1, label %backedge
-  i32 2, label %dead]
-
-dead:
-  %i.2 = add i32 %i, 1
-  br label %dummy
-
-dummy:
-  br label %backedge
-
-backedge:
-  %i.1 = phi i32 [%i, %header], [%i.2, %dummy]
-  %i.inc = add i32 %i.1, 1
-  %cmp = icmp slt i32 %i.inc, %end
-  br i1 %cmp, label %header, label %exit
-
-exit:
-  ret i32 %i.inc
-}
-
-; Check that we preserve static reachibility of a dead exit block while deleting
-; a branch.
-define i32 @dead_exit_test_branch_loop(i32 %end) {
-; CHECK-LABEL: @dead_exit_test_branch_loop(
-; CHECK-NEXT:  preheader:
-; CHECK-NEXT:    switch i32 0, label [[PREHEADER_SPLIT:%.*]] [
-; CHECK-NEXT:    i32 1, label [[DEAD:%.*]]
-; CHECK-NEXT:    ]
-; CHECK:       preheader.split:
-; CHECK-NEXT:    br label [[HEADER:%.*]]
-; CHECK:       header:
-; CHECK-NEXT:    [[I:%.*]] = phi i32 [ 0, [[PREHEADER_SPLIT]] ], [ [[I_INC:%.*]], [[HEADER]] ]
-; CHECK-NEXT:    [[I_INC]] = add i32 [[I]], 1
-; CHECK-NEXT:    [[CMP:%.*]] = icmp slt i32 [[I_INC]], [[END:%.*]]
-; CHECK-NEXT:    br i1 [[CMP]], label [[HEADER]], label [[EXIT_LOOPEXIT:%.*]]
-; CHECK:       dead:
-; CHECK-NEXT:    br label [[DUMMY:%.*]]
-; CHECK:       dummy:
-; CHECK-NEXT:    br label [[EXIT:%.*]]
-; CHECK:       exit.loopexit:
-; CHECK-NEXT:    [[I_INC_LCSSA:%.*]] = phi i32 [ [[I_INC]], [[HEADER]] ]
-; CHECK-NEXT:    br label [[EXIT]]
-; CHECK:       exit:
-; CHECK-NEXT:    [[I_1:%.*]] = phi i32 [ undef, [[DUMMY]] ], [ [[I_INC_LCSSA]], [[EXIT_LOOPEXIT]] ]
-; CHECK-NEXT:    ret i32 [[I_1]]
-;
-preheader:
-  br label %header
-
-header:
-  %i = phi i32 [0, %preheader], [%i.inc, %backedge]
-  br i1 true, label %backedge, label %dead
-
-dead:
-  br label %dummy
-
-dummy:
-  br label %exit
-
-backedge:
-  %i.inc = add i32 %i, 1
-  %cmp = icmp slt i32 %i.inc, %end
-  br i1 %cmp, label %header, label %exit
-
-exit:
-  %i.1 = phi i32 [%i.inc, %backedge], [%i, %dummy]
-  ret i32 %i.1
-}
-
-; Check that we preserve static reachibility of a dead exit block while deleting
-; a switch.
-define i32 @dead_exit_test_switch_loop(i32 %end) {
-; CHECK-LABEL: @dead_exit_test_switch_loop(
-; CHECK-NEXT:  preheader:
-; CHECK-NEXT:    switch i32 0, label [[PREHEADER_SPLIT:%.*]] [
-; CHECK-NEXT:    i32 1, label [[DEAD:%.*]]
-; CHECK-NEXT:    ]
-; CHECK:       preheader.split:
-; CHECK-NEXT:    br label [[HEADER:%.*]]
-; CHECK:       header:
-; CHECK-NEXT:    [[I:%.*]] = phi i32 [ 0, [[PREHEADER_SPLIT]] ], [ [[I_INC:%.*]], [[HEADER]] ]
-; CHECK-NEXT:    [[I_INC]] = add i32 [[I]], 1
-; CHECK-NEXT:    [[CMP:%.*]] = icmp slt i32 [[I_INC]], [[END:%.*]]
-; CHECK-NEXT:    br i1 [[CMP]], label [[HEADER]], label [[EXIT_LOOPEXIT:%.*]]
-; CHECK:       dead:
-; CHECK-NEXT:    br label [[DUMMY:%.*]]
-; CHECK:       dummy:
-; CHECK-NEXT:    br label [[EXIT:%.*]]
-; CHECK:       exit.loopexit:
-; CHECK-NEXT:    [[I_INC_LCSSA:%.*]] = phi i32 [ [[I_INC]], [[HEADER]] ]
-; CHECK-NEXT:    br label [[EXIT]]
-; CHECK:       exit:
-; CHECK-NEXT:    [[I_1:%.*]] = phi i32 [ undef, [[DUMMY]] ], [ [[I_INC_LCSSA]], [[EXIT_LOOPEXIT]] ]
-; CHECK-NEXT:    ret i32 [[I_1]]
-;
-preheader:
-  br label %header
-
-header:
-  %i = phi i32 [0, %preheader], [%i.inc, %backedge]
-  switch i32 1, label %dead [i32 0, label %dead
-  i32 1, label %backedge
-  i32 2, label %dead]
-
-dead:
-  br label %dummy
-
-dummy:
-  br label %exit
-
-backedge:
-  %i.inc = add i32 %i, 1
-  %cmp = icmp slt i32 %i.inc, %end
-  br i1 %cmp, label %header, label %exit
-
-exit:
-  %i.1 = phi i32 [%i.inc, %backedge], [%i, %dummy]
-  ret i32 %i.1
-}
-
-; Check that we can completely eliminate the current loop, branch case.
-define i32 @dead_loop_test_branch_loop(i32 %end) {
-; CHECK-LABEL: @dead_loop_test_branch_loop(
-; CHECK-NEXT:  preheader:
-; CHECK-NEXT:    br label [[HEADER:%.*]]
-; CHECK:       header:
-; CHECK-NEXT:    [[I:%.*]] = phi i32 [ 0, [[PREHEADER:%.*]] ], [ [[I_INC:%.*]], [[BACKEDGE:%.*]] ]
-; CHECK-NEXT:    br i1 true, label [[BACKEDGE]], label [[DEAD:%.*]]
-; CHECK:       dead:
-; CHECK-NEXT:    [[I_2:%.*]] = add i32 [[I]], 1
-; CHECK-NEXT:    br label [[BACKEDGE]]
-; CHECK:       backedge:
-; CHECK-NEXT:    [[I_1:%.*]] = phi i32 [ [[I]], [[HEADER]] ], [ [[I_2]], [[DEAD]] ]
-; CHECK-NEXT:    [[I_INC]] = add i32 [[I_1]], 1
-; CHECK-NEXT:    [[CMP:%.*]] = icmp slt i32 [[I_INC]], [[END:%.*]]
-; CHECK-NEXT:    br i1 false, label [[HEADER]], label [[EXIT:%.*]]
-; CHECK:       exit:
-; CHECK-NEXT:    [[I_INC_LCSSA:%.*]] = phi i32 [ [[I_INC]], [[BACKEDGE]] ]
-; CHECK-NEXT:    ret i32 [[I_INC_LCSSA]]
-;
-preheader:
-  br label %header
-
-header:
-  %i = phi i32 [0, %preheader], [%i.inc, %backedge]
-  br i1 true, label %backedge, label %dead
-
-dead:
-  %i.2 = add i32 %i, 1
-  br label %dummy
-
-dummy:
-  br label %backedge
-
-backedge:
-  %i.1 = phi i32 [%i, %header], [%i.2, %dummy]
-  %i.inc = add i32 %i.1, 1
-  %cmp = icmp slt i32 %i.inc, %end
-  br i1 false, label %header, label %exit
-
-exit:
-  ret i32 %i.inc
-}
-
-; Check that we can completely eliminate the current loop, switch case.
-define i32 @dead_loop_test_switch_loop(i32 %end) {
-; CHECK-LABEL: @dead_loop_test_switch_loop(
-; CHECK-NEXT:  preheader:
-; CHECK-NEXT:    br label [[HEADER:%.*]]
-; CHECK:       header:
-; CHECK-NEXT:    [[I:%.*]] = phi i32 [ 0, [[PREHEADER:%.*]] ], [ [[I_INC:%.*]], [[BACKEDGE:%.*]] ]
-; CHECK-NEXT:    switch i32 1, label [[DEAD:%.*]] [
-; CHECK-NEXT:    i32 0, label [[DEAD]]
-; CHECK-NEXT:    i32 1, label [[BACKEDGE]]
-; CHECK-NEXT:    i32 2, label [[DEAD]]
-; CHECK-NEXT:    ]
-; CHECK:       dead:
-; CHECK-NEXT:    [[I_2:%.*]] = add i32 [[I]], 1
-; CHECK-NEXT:    br label [[BACKEDGE]]
-; CHECK:       backedge:
-; CHECK-NEXT:    [[I_1:%.*]] = phi i32 [ [[I]], [[HEADER]] ], [ [[I_2]], [[DEAD]] ]
-; CHECK-NEXT:    [[I_INC]] = add i32 [[I_1]], 1
-; CHECK-NEXT:    [[CMP:%.*]] = icmp slt i32 [[I_INC]], [[END:%.*]]
-; CHECK-NEXT:    br i1 false, label [[HEADER]], label [[EXIT:%.*]]
-; CHECK:       exit:
-; CHECK-NEXT:    [[I_INC_LCSSA:%.*]] = phi i32 [ [[I_INC]], [[BACKEDGE]] ]
-; CHECK-NEXT:    ret i32 [[I_INC_LCSSA]]
-;
-preheader:
-  br label %header
-header:
-  %i = phi i32 [0, %preheader], [%i.inc, %backedge]
-  switch i32 1, label %dead [i32 0, label %dead
-  i32 1, label %backedge
-  i32 2, label %dead]
-dead:
-  %i.2 = add i32 %i, 1
-  br label %dummy
-
-dummy:
-  br label %backedge
-
-backedge:
-  %i.1 = phi i32 [%i, %header], [%i.2, %dummy]
-  %i.inc = add i32 %i.1, 1
-  %cmp = icmp slt i32 %i.inc, %end
-  br i1 false, label %header, label %exit
-
-exit:
-  ret i32 %i.inc
-}
-
-; Check that we can delete a dead inner loop entirely.
-define i32 @dead_sub_loop_test_branch_loop(i32 %end) {
-; CHECK-LABEL: @dead_sub_loop_test_branch_loop(
-; CHECK-NEXT:  preheader:
-; CHECK-NEXT:    br label [[HEADER:%.*]]
-; CHECK:       header:
-; CHECK-NEXT:    [[I:%.*]] = phi i32 [ 0, [[PREHEADER:%.*]] ], [ [[I_INC:%.*]], [[EXIT_A:%.*]] ]
-; CHECK-NEXT:    br label [[LIVE_LOOP:%.*]]
-; CHECK:       live_loop:
-; CHECK-NEXT:    [[A:%.*]] = phi i32 [ 0, [[HEADER]] ], [ [[A_INC:%.*]], [[LIVE_LOOP]] ]
-; CHECK-NEXT:    [[A_INC]] = add i32 [[A]], 1
-; CHECK-NEXT:    [[CMP_A:%.*]] = icmp slt i32 [[A_INC]], [[END:%.*]]
-; CHECK-NEXT:    br i1 [[CMP_A]], label [[LIVE_LOOP]], label [[EXIT_A]]
-; CHECK:       exit.a:
-; CHECK-NEXT:    [[I_INC]] = add i32 [[I]], 1
-; CHECK-NEXT:    [[CMP:%.*]] = icmp slt i32 [[I_INC]], [[END]]
-; CHECK-NEXT:    br i1 [[CMP]], label [[HEADER]], label [[EXIT:%.*]]
-; CHECK:       exit:
-; CHECK-NEXT:    [[I_INC_LCSSA:%.*]] = phi i32 [ [[I_INC]], [[EXIT_A]] ]
-; CHECK-NEXT:    ret i32 [[I_INC_LCSSA]]
-;
-preheader:
-  br label %header
-
-header:
-  %i = phi i32 [0, %preheader], [%i.inc, %backedge]
-  br i1 true, label %live_preheader, label %dead_preheader
-
-live_preheader:
-  br label %live_loop
-
-live_loop:
-  %a = phi i32 [0, %live_preheader], [%a.inc, %live_loop]
-  %a.inc = add i32 %a, 1
-  %cmp.a = icmp slt i32 %a.inc, %end
-  br i1 %cmp.a, label %live_loop, label %exit.a
-
-exit.a:
-  br label %backedge
-
-dead_preheader:
-  br label %dead_loop
-
-dead_loop:
-  %b = phi i32 [0, %dead_preheader], [%b.inc, %dead_loop]
-  %b.inc = add i32 %b, 1
-  %cmp.b = icmp slt i32 %b.inc, %end
-  br i1 %cmp.b, label %dead_loop, label %exit.b
-
-exit.b:
-  br label %backedge
-
-backedge:
-  %i.inc = add i32 %i, 1
-  %cmp = icmp slt i32 %i.inc, %end
-  br i1 %cmp, label %header, label %exit
-
-exit:
-  ret i32 %i.inc
-}
-
-define i32 @dead_sub_loop_test_switch_loop(i32 %end) {
-; CHECK-LABEL: @dead_sub_loop_test_switch_loop(
-; CHECK-NEXT:  preheader:
-; CHECK-NEXT:    br label [[HEADER:%.*]]
-; CHECK:       header:
-; CHECK-NEXT:    [[I:%.*]] = phi i32 [ 0, [[PREHEADER:%.*]] ], [ [[I_INC:%.*]], [[EXIT_A:%.*]] ]
-; CHECK-NEXT:    br label [[LIVE_LOOP:%.*]]
-; CHECK:       live_loop:
-; CHECK-NEXT:    [[A:%.*]] = phi i32 [ 0, [[HEADER]] ], [ [[A_INC:%.*]], [[LIVE_LOOP]] ]
-; CHECK-NEXT:    [[A_INC]] = add i32 [[A]], 1
-; CHECK-NEXT:    [[CMP_A:%.*]] = icmp slt i32 [[A_INC]], [[END:%.*]]
-; CHECK-NEXT:    br i1 [[CMP_A]], label [[LIVE_LOOP]], label [[EXIT_A]]
-; CHECK:       exit.a:
-; CHECK-NEXT:    [[I_INC]] = add i32 [[I]], 1
-; CHECK-NEXT:    [[CMP:%.*]] = icmp slt i32 [[I_INC]], [[END]]
-; CHECK-NEXT:    br i1 [[CMP]], label [[HEADER]], label [[EXIT:%.*]]
-; CHECK:       exit:
-; CHECK-NEXT:    [[I_INC_LCSSA:%.*]] = phi i32 [ [[I_INC]], [[EXIT_A]] ]
-; CHECK-NEXT:    ret i32 [[I_INC_LCSSA]]
-;
-preheader:
-  br label %header
-
-header:
-  %i = phi i32 [0, %preheader], [%i.inc, %backedge]
-  switch i32 1, label %dead_preheader [i32 0, label %dead_preheader
-  i32 1, label %live_preheader
-  i32 2, label %dead_preheader]
-
-live_preheader:
-  br label %live_loop
-
-live_loop:
-  %a = phi i32 [0, %live_preheader], [%a.inc, %live_loop]
-  %a.inc = add i32 %a, 1
-  %cmp.a = icmp slt i32 %a.inc, %end
-  br i1 %cmp.a, label %live_loop, label %exit.a
-
-exit.a:
-  br label %backedge
-
-dead_preheader:
-  br label %dead_loop
-
-dead_loop:
-  %b = phi i32 [0, %dead_preheader], [%b.inc, %dead_loop]
-  %b.inc = add i32 %b, 1
-  %cmp.b = icmp slt i32 %b.inc, %end
-  br i1 %cmp.b, label %dead_loop, label %exit.b
-
-exit.b:
-  br label %backedge
-
-backedge:
-  %i.inc = add i32 %i, 1
-  %cmp = icmp slt i32 %i.inc, %end
-  br i1 %cmp, label %header, label %exit
-
-exit:
-  ret i32 %i.inc
-}
-
-; Check that we preserve static reachability of an exit block even if we prove
-; that the loop is infinite. Branch case.
-define i32 @inf_loop_test_branch_loop(i32 %end) {
-; CHECK-LABEL: @inf_loop_test_branch_loop(
-; CHECK-NEXT:  preheader:
-; CHECK-NEXT:    switch i32 0, label [[PREHEADER_SPLIT:%.*]] [
-; CHECK-NEXT:    i32 1, label [[EXIT:%.*]]
-; CHECK-NEXT:    ]
-; CHECK:       preheader.split:
-; CHECK-NEXT:    br label [[HEADER:%.*]]
-; CHECK:       header:
-; CHECK-NEXT:    [[I:%.*]] = phi i32 [ 0, [[PREHEADER_SPLIT]] ], [ [[I_INC:%.*]], [[HEADER]] ]
-; CHECK-NEXT:    [[I_INC]] = add i32 [[I]], 1
-; CHECK-NEXT:    [[CMP:%.*]] = icmp slt i32 [[I_INC]], [[END:%.*]]
-; CHECK-NEXT:    br label [[HEADER]]
-; CHECK:       exit:
-; CHECK-NEXT:    ret i32 undef
-;
-preheader:
-  br label %header
-
-header:
-  %i = phi i32 [0, %preheader], [%i.inc, %backedge]
-  br i1 true, label %backedge, label %dead
-
-dead:
-  %i.2 = add i32 %i, 1
-  br label %dummy
-
-dummy:
-  br label %backedge
-
-backedge:
-  %i.1 = phi i32 [%i, %header], [%i.2, %dummy]
-  %i.inc = add i32 %i.1, 1
-  %cmp = icmp slt i32 %i.inc, %end
-  br i1 true, label %header, label %exit
-
-exit:
-  ret i32 %i.inc
-}
-
-define i32 @inf_loop_test_switch_loop(i32 %end) {
-; CHECK-LABEL: @inf_loop_test_switch_loop(
-; CHECK-NEXT:  preheader:
-; CHECK-NEXT:    switch i32 0, label [[PREHEADER_SPLIT:%.*]] [
-; CHECK-NEXT:    i32 1, label [[EXIT:%.*]]
-; CHECK-NEXT:    ]
-; CHECK:       preheader.split:
-; CHECK-NEXT:    br label [[HEADER:%.*]]
-; CHECK:       header:
-; CHECK-NEXT:    [[I:%.*]] = phi i32 [ 0, [[PREHEADER_SPLIT]] ], [ [[I_INC:%.*]], [[HEADER]] ]
-; CHECK-NEXT:    [[I_INC]] = add i32 [[I]], 1
-; CHECK-NEXT:    [[CMP:%.*]] = icmp slt i32 [[I_INC]], [[END:%.*]]
-; CHECK-NEXT:    br label [[HEADER]]
-; CHECK:       exit:
-; CHECK-NEXT:    ret i32 undef
-;
-preheader:
-  br label %header
-header:
-  %i = phi i32 [0, %preheader], [%i.inc, %backedge]
-  switch i32 1, label %dead [i32 0, label %dead
-  i32 1, label %backedge
-  i32 2, label %dead]
-dead:
-  %i.2 = add i32 %i, 1
-  br label %dummy
-dummy:
-  br label %backedge
-backedge:
-  %i.1 = phi i32 [%i, %header], [%i.2, %dummy]
-  %i.inc = add i32 %i.1, 1
-  %cmp = icmp slt i32 %i.inc, %end
-  br i1 true, label %header, label %exit
-exit:
-  ret i32 %i.inc
-}
-
-; Check that when the block is not actually dead, we don't remove it.
-define i32 @live_block_test_branch_loop(i1 %c, i32 %end) {
-; CHECK-LABEL: @live_block_test_branch_loop(
-; CHECK-NEXT:  preheader:
-; CHECK-NEXT:    br label [[HEADER:%.*]]
-; CHECK:       header:
-; CHECK-NEXT:    [[I:%.*]] = phi i32 [ 0, [[PREHEADER:%.*]] ], [ [[I_INC:%.*]], [[BACKEDGE:%.*]] ]
-; CHECK-NEXT:    br i1 [[C:%.*]], label [[CHECK:%.*]], label [[LIVE:%.*]]
-; CHECK:       check:
-; CHECK-NEXT:    br label [[BACKEDGE]]
-; CHECK:       live:
-; CHECK-NEXT:    [[I_2:%.*]] = add i32 [[I]], 1
-; CHECK-NEXT:    br label [[BACKEDGE]]
-; CHECK:       backedge:
-; CHECK-NEXT:    [[I_1:%.*]] = phi i32 [ [[I]], [[CHECK]] ], [ [[I_2]], [[LIVE]] ]
-; CHECK-NEXT:    [[I_INC]] = add i32 [[I_1]], 1
-; CHECK-NEXT:    [[CMP:%.*]] = icmp slt i32 [[I_INC]], [[END:%.*]]
-; CHECK-NEXT:    br i1 [[CMP]], label [[HEADER]], label [[EXIT:%.*]]
-; CHECK:       exit:
-; CHECK-NEXT:    [[I_INC_LCSSA:%.*]] = phi i32 [ [[I_INC]], [[BACKEDGE]] ]
-; CHECK-NEXT:    ret i32 [[I_INC_LCSSA]]
-;
-preheader:
-  br label %header
-
-header:
-  %i = phi i32 [0, %preheader], [%i.inc, %backedge]
-  br i1 %c, label %check, label %live
-
-check:
-  br i1 true, label %backedge, label %live
-
-live:
-  %i.2 = add i32 %i, 1
-  br label %backedge
-
-backedge:
-  %i.1 = phi i32 [%i, %check], [%i.2, %live]
-  %i.inc = add i32 %i.1, 1
-  %cmp = icmp slt i32 %i.inc, %end
-  br i1 %cmp, label %header, label %exit
-
-exit:
-  ret i32 %i.inc
-}
-
-; Check that when the block is not actually dead, we don't remove it. Version
-; with Phi node.
-define i32 @live_block_test_branch_loop_phis(i1 %c, i32 %end) {
-; CHECK-LABEL: @live_block_test_branch_loop_phis(
-; CHECK-NEXT:  preheader:
-; CHECK-NEXT:    br label [[HEADER:%.*]]
-; CHECK:       header:
-; CHECK-NEXT:    [[I:%.*]] = phi i32 [ 0, [[PREHEADER:%.*]] ], [ [[I_INC:%.*]], [[BACKEDGE:%.*]] ]
-; CHECK-NEXT:    br i1 [[C:%.*]], label [[CHECK:%.*]], label [[LIVE:%.*]]
-; CHECK:       check:
-; CHECK-NEXT:    br label [[BACKEDGE]]
-; CHECK:       live:
-; CHECK-NEXT:    [[I_2:%.*]] = add i32 [[I]], 1
-; CHECK-NEXT:    br label [[BACKEDGE]]
-; CHECK:       backedge:
-; CHECK-NEXT:    [[I_1:%.*]] = phi i32 [ [[I]], [[CHECK]] ], [ [[I_2]], [[LIVE]] ]
-; CHECK-NEXT:    [[I_INC]] = add i32 [[I_1]], 1
-; CHECK-NEXT:    [[CMP:%.*]] = icmp slt i32 [[I_INC]], [[END:%.*]]
-; CHECK-NEXT:    br i1 [[CMP]], label [[HEADER]], label [[EXIT:%.*]]
-; CHECK:       exit:
-; CHECK-NEXT:    [[I_INC_LCSSA:%.*]] = phi i32 [ [[I_INC]], [[BACKEDGE]] ]
-; CHECK-NEXT:    ret i32 [[I_INC_LCSSA]]
-;
-preheader:
-  br label %header
-
-header:
-  %i = phi i32 [0, %preheader], [%i.inc, %backedge]
-  br i1 %c, label %check, label %live
-
-check:
-  br i1 true, label %backedge, label %live
-
-live:
-  %phi = phi i32 [ 1, %header ], [ -1, %check ]
-  %i.2 = add i32 %i, %phi
-  br label %backedge
-
-backedge:
-  %i.1 = phi i32 [%i, %check], [%i.2, %live]
-  %i.inc = add i32 %i.1, 1
-  %cmp = icmp slt i32 %i.inc, %end
-  br i1 %cmp, label %header, label %exit
-
-exit:
-  ret i32 %i.inc
-}
-
-define i32 @live_block_test_switch_loop(i1 %c, i32 %end) {
-; CHECK-LABEL: @live_block_test_switch_loop(
-; CHECK-NEXT:  preheader:
-; CHECK-NEXT:    br label [[HEADER:%.*]]
-; CHECK:       header:
-; CHECK-NEXT:    [[I:%.*]] = phi i32 [ 0, [[PREHEADER:%.*]] ], [ [[I_INC:%.*]], [[BACKEDGE:%.*]] ]
-; CHECK-NEXT:    br i1 [[C:%.*]], label [[CHECK:%.*]], label [[LIVE:%.*]]
-; CHECK:       check:
-; CHECK-NEXT:    br label [[BACKEDGE]]
-; CHECK:       live:
-; CHECK-NEXT:    [[I_2:%.*]] = add i32 [[I]], 1
-; CHECK-NEXT:    br label [[BACKEDGE]]
-; CHECK:       backedge:
-; CHECK-NEXT:    [[I_1:%.*]] = phi i32 [ [[I]], [[CHECK]] ], [ [[I_2]], [[LIVE]] ]
-; CHECK-NEXT:    [[I_INC]] = add i32 [[I_1]], 1
-; CHECK-NEXT:    [[CMP:%.*]] = icmp slt i32 [[I_INC]], [[END:%.*]]
-; CHECK-NEXT:    br i1 [[CMP]], label [[HEADER]], label [[EXIT:%.*]]
-; CHECK:       exit:
-; CHECK-NEXT:    [[I_INC_LCSSA:%.*]] = phi i32 [ [[I_INC]], [[BACKEDGE]] ]
-; CHECK-NEXT:    ret i32 [[I_INC_LCSSA]]
-;
-preheader:
-  br label %header
-
-header:
-  %i = phi i32 [0, %preheader], [%i.inc, %backedge]
-  br i1 %c, label %check, label %live
-
-check:
-  switch i32 1, label %live [i32 0, label %live
-  i32 1, label %backedge
-  i32 2, label %live]
-
-live:
-  %i.2 = add i32 %i, 1
-  br label %backedge
-
-backedge:
-  %i.1 = phi i32 [%i, %check], [%i.2, %live]
-  %i.inc = add i32 %i.1, 1
-  %cmp = icmp slt i32 %i.inc, %end
-  br i1 %cmp, label %header, label %exit
-
-exit:
-  ret i32 %i.inc
-}
-
-define i32 @live_block_test_switch_loop_phis(i1 %c, i32 %end) {
-; CHECK-LABEL: @live_block_test_switch_loop_phis(
-; CHECK-NEXT:  preheader:
-; CHECK-NEXT:    br label [[HEADER:%.*]]
-; CHECK:       header:
-; CHECK-NEXT:    [[I:%.*]] = phi i32 [ 0, [[PREHEADER:%.*]] ], [ [[I_INC:%.*]], [[BACKEDGE:%.*]] ]
-; CHECK-NEXT:    br i1 [[C:%.*]], label [[CHECK:%.*]], label [[LIVE:%.*]]
-; CHECK:       check:
-; CHECK-NEXT:    br label [[BACKEDGE]]
-; CHECK:       live:
-; CHECK-NEXT:    [[I_2:%.*]] = add i32 [[I]], 1
-; CHECK-NEXT:    br label [[BACKEDGE]]
-; CHECK:       backedge:
-; CHECK-NEXT:    [[I_1:%.*]] = phi i32 [ [[I]], [[CHECK]] ], [ [[I_2]], [[LIVE]] ]
-; CHECK-NEXT:    [[I_INC]] = add i32 [[I_1]], 1
-; CHECK-NEXT:    [[CMP:%.*]] = icmp slt i32 [[I_INC]], [[END:%.*]]
-; CHECK-NEXT:    br i1 [[CMP]], label [[HEADER]], label [[EXIT:%.*]]
-; CHECK:       exit:
-; CHECK-NEXT:    [[I_INC_LCSSA:%.*]] = phi i32 [ [[I_INC]], [[BACKEDGE]] ]
-; CHECK-NEXT:    ret i32 [[I_INC_LCSSA]]
-;
-preheader:
-  br label %header
-
-header:
-  %i = phi i32 [0, %preheader], [%i.inc, %backedge]
-  br i1 %c, label %check, label %live
-
-check:
-  switch i32 1, label %live [i32 0, label %live
-  i32 1, label %backedge
-  i32 2, label %live]
-
-live:
-  %phi = phi i32 [ 1, %header ], [ -1, %check ], [ -1, %check ], [ -1, %check ]
-  %i.2 = add i32 %i, %phi
-  br label %backedge
-
-backedge:
-  %i.1 = phi i32 [%i, %check], [%i.2, %live]
-  %i.inc = add i32 %i.1, 1
-  %cmp = icmp slt i32 %i.inc, %end
-  br i1 %cmp, label %header, label %exit
-
-exit:
-  ret i32 %i.inc
-}
-
-; Check that we can remove part of blocks of inner loop while the loop still
-; preserves, in presence of outer loop.
-define i32 @partial_sub_loop_test_branch_loop(i32 %end) {
-; CHECK-LABEL: @partial_sub_loop_test_branch_loop(
-; CHECK-NEXT:  entry:
-; CHECK-NEXT:    br label [[OUTER_HEADER:%.*]]
-; CHECK:       outer_header:
-; CHECK-NEXT:    [[J:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[J_INC:%.*]], [[OUTER_BACKEDGE:%.*]] ]
-; CHECK-NEXT:    br label [[HEADER:%.*]]
-; CHECK:       header:
-; CHECK-NEXT:    [[I:%.*]] = phi i32 [ 0, [[OUTER_HEADER]] ], [ [[I_INC:%.*]], [[HEADER]] ]
-; CHECK-NEXT:    [[I_INC]] = add i32 [[I]], 1
-; CHECK-NEXT:    [[CMP:%.*]] = icmp slt i32 [[I_INC]], [[END:%.*]]
-; CHECK-NEXT:    br i1 [[CMP]], label [[HEADER]], label [[OUTER_BACKEDGE]]
-; CHECK:       outer_backedge:
-; CHECK-NEXT:    [[I_INC_LCSSA:%.*]] = phi i32 [ [[I_INC]], [[HEADER]] ]
-; CHECK-NEXT:    [[J_INC]] = add i32 [[J]], 1
-; CHECK-NEXT:    [[CMP_J:%.*]] = icmp slt i32 [[J_INC]], [[END]]
-; CHECK-NEXT:    br i1 [[CMP_J]], label [[OUTER_HEADER]], label [[EXIT:%.*]]
-; CHECK:       exit:
-; CHECK-NEXT:    [[I_INC_LCSSA_LCSSA:%.*]] = phi i32 [ [[I_INC_LCSSA]], [[OUTER_BACKEDGE]] ]
-; CHECK-NEXT:    ret i32 [[I_INC_LCSSA_LCSSA]]
-;
-entry:
-  br label %outer_header
-
-outer_header:
-  %j = phi i32 [0, %entry], [%j.inc, %outer_backedge]
-  br label %preheader
-
-preheader:
-  br label %header
-
-header:
-  %i = phi i32 [0, %preheader], [%i.inc, %backedge]
-  br i1 true, label %backedge, label %dead
-
-dead:
-  %i.2 = add i32 %i, 1
-  br label %backedge
-
-backedge:
-  %i.1 = phi i32 [%i, %header], [%i.2, %dead]
-  %i.inc = add i32 %i.1, 1
-  %cmp = icmp slt i32 %i.inc, %end
-  br i1 %cmp, label %header, label %outer_backedge
-
-outer_backedge:
-  %j.inc = add i32 %j, 1
-  %cmp.j = icmp slt i32 %j.inc, %end
-  br i1 %cmp.j, label %outer_header, label %exit
-
-exit:
-  ret i32 %i.inc
-}
-
-define i32 @partial_sub_loop_test_switch_loop(i32 %end) {
-; CHECK-LABEL: @partial_sub_loop_test_switch_loop(
-; CHECK-NEXT:  entry:
-; CHECK-NEXT:    br label [[OUTER_HEADER:%.*]]
-; CHECK:       outer_header:
-; CHECK-NEXT:    [[J:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[J_INC:%.*]], [[OUTER_BACKEDGE:%.*]] ]
-; CHECK-NEXT:    br label [[HEADER:%.*]]
-; CHECK:       header:
-; CHECK-NEXT:    [[I:%.*]] = phi i32 [ 0, [[OUTER_HEADER]] ], [ [[I_INC:%.*]], [[HEADER]] ]
-; CHECK-NEXT:    [[I_INC]] = add i32 [[I]], 1
-; CHECK-NEXT:    [[CMP:%.*]] = icmp slt i32 [[I_INC]], [[END:%.*]]
-; CHECK-NEXT:    br i1 [[CMP]], label [[HEADER]], label [[OUTER_BACKEDGE]]
-; CHECK:       outer_backedge:
-; CHECK-NEXT:    [[I_INC_LCSSA:%.*]] = phi i32 [ [[I_INC]], [[HEADER]] ]
-; CHECK-NEXT:    [[J_INC]] = add i32 [[J]], 1
-; CHECK-NEXT:    [[CMP_J:%.*]] = icmp slt i32 [[J_INC]], [[END]]
-; CHECK-NEXT:    br i1 [[CMP_J]], label [[OUTER_HEADER]], label [[EXIT:%.*]]
-; CHECK:       exit:
-; CHECK-NEXT:    [[I_INC_LCSSA_LCSSA:%.*]] = phi i32 [ [[I_INC_LCSSA]], [[OUTER_BACKEDGE]] ]
-; CHECK-NEXT:    ret i32 [[I_INC_LCSSA_LCSSA]]
-;
-entry:
-  br label %outer_header
-
-outer_header:
-  %j = phi i32 [0, %entry], [%j.inc, %outer_backedge]
-  br label %preheader
-
-preheader:
-  br label %header
-
-header:
-  %i = phi i32 [0, %preheader], [%i.inc, %backedge]
-  switch i32 1, label %dead [i32 0, label %dead
-  i32 1, label %backedge
-  i32 2, label %dead]
-
-dead:
-  %i.2 = add i32 %i, 1
-  br label %backedge
-
-backedge:
-  %i.1 = phi i32 [%i, %header], [%i.2, %dead]
-  %i.inc = add i32 %i.1, 1
-  %cmp = icmp slt i32 %i.inc, %end
-  br i1 %cmp, label %header, label %outer_backedge
-
-outer_backedge:
-  %j.inc = add i32 %j, 1
-  %cmp.j = icmp slt i32 %j.inc, %end
-  br i1 %cmp.j, label %outer_header, label %exit
-
-exit:
-  ret i32 %i.inc
-}
-
-; Check that we can completely delete inner loop and preserve the outer loop.
-define i32 @full_sub_loop_test_branch_loop(i32 %end) {
-; CHECK-LABEL: @full_sub_loop_test_branch_loop(
-; CHECK-NEXT:  entry:
-; CHECK-NEXT:    br label [[OUTER_HEADER:%.*]]
-; CHECK:       outer_header:
-; CHECK-NEXT:    [[J:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[J_INC:%.*]], [[OUTER_BACKEDGE:%.*]] ]
-; CHECK-NEXT:    br label [[HEADER:%.*]]
-; CHECK:       header:
-; CHECK-NEXT:    [[I:%.*]] = phi i32 [ 0, [[OUTER_HEADER]] ], [ [[I_INC:%.*]], [[BACKEDGE:%.*]] ]
-; CHECK-NEXT:    [[MUL:%.*]] = mul i32 [[I]], [[I]]
-; CHECK-NEXT:    br i1 false, label [[BACKEDGE]], label [[DEAD:%.*]]
-; CHECK:       dead:
-; CHECK-NEXT:    [[I_2:%.*]] = add i32 [[I]], 1
-; CHECK-NEXT:    br label [[BACKEDGE]]
-; CHECK:       backedge:
-; CHECK-NEXT:    [[I_1:%.*]] = phi i32 [ [[I]], [[HEADER]] ], [ [[I_2]], [[DEAD]] ]
-; CHECK-NEXT:    [[I_INC]] = add i32 [[I_1]], 1
-; CHECK-NEXT:    br i1 false, label [[HEADER]], label [[OUTER_BACKEDGE]]
-; CHECK:       outer_backedge:
-; CHECK-NEXT:    [[I_INC_LCSSA:%.*]] = phi i32 [ [[I_INC]], [[BACKEDGE]] ]
-; CHECK-NEXT:    [[J_INC]] = add i32 [[J]], 1
-; CHECK-NEXT:    [[CMP_J:%.*]] = icmp slt i32 [[J_INC]], [[END:%.*]]
-; CHECK-NEXT:    br i1 [[CMP_J]], label [[OUTER_HEADER]], label [[EXIT:%.*]]
-; CHECK:       exit:
-; CHECK-NEXT:    [[I_INC_LCSSA_LCSSA:%.*]] = phi i32 [ [[I_INC_LCSSA]], [[OUTER_BACKEDGE]] ]
-; CHECK-NEXT:    ret i32 [[I_INC_LCSSA_LCSSA]]
-;
-entry:
-  br label %outer_header
-
-outer_header:
-  %j = phi i32 [0, %entry], [%j.inc, %outer_backedge]
-  br label %preheader
-
-preheader:
-  br label %header
-
-header:
-  %i = phi i32 [0, %preheader], [%i.inc, %backedge]
-  br label  %live_part
-
-live_part:
-  %mul = mul i32 %i, %i
-  br i1 false, label %backedge, label %dead
-
-dead:
-  %i.2 = add i32 %i, 1
-  br label %backedge
-
-backedge:
-  %i.1 = phi i32 [%i, %live_part], [%i.2, %dead]
-  %i.inc = add i32 %i.1, 1
-  br i1 false, label %header, label %outer_backedge
-
-outer_backedge:
-  %j.inc = add i32 %j, 1
-  %cmp.j = icmp slt i32 %j.inc, %end
-  br i1 %cmp.j, label %outer_header, label %exit
-
-exit:
-  ret i32 %i.inc
-}
-
-define i32 @full_sub_loop_test_switch_loop(i32 %end) {
-; CHECK-LABEL: @full_sub_loop_test_switch_loop(
-; CHECK-NEXT:  entry:
-; CHECK-NEXT:    br label [[OUTER_HEADER:%.*]]
-; CHECK:       outer_header:
-; CHECK-NEXT:    [[J:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[J_INC:%.*]], [[OUTER_BACKEDGE:%.*]] ]
-; CHECK-NEXT:    br label [[HEADER:%.*]]
-; CHECK:       header:
-; CHECK-NEXT:    [[I:%.*]] = phi i32 [ 0, [[OUTER_HEADER]] ], [ [[I_INC:%.*]], [[BACKEDGE:%.*]] ]
-; CHECK-NEXT:    [[MUL:%.*]] = mul i32 [[I]], [[I]]
-; CHECK-NEXT:    switch i32 1, label [[DEAD:%.*]] [
-; CHECK-NEXT:    i32 0, label [[BACKEDGE]]
-; CHECK-NEXT:    ]
-; CHECK:       dead:
-; CHECK-NEXT:    [[I_2:%.*]] = add i32 [[I]], 1
-; CHECK-NEXT:    br label [[BACKEDGE]]
-; CHECK:       backedge:
-; CHECK-NEXT:    [[I_1:%.*]] = phi i32 [ [[I]], [[HEADER]] ], [ [[I_2]], [[DEAD]] ]
-; CHECK-NEXT:    [[I_INC]] = add i32 [[I_1]], 1
-; CHECK-NEXT:    switch i32 1, label [[OUTER_BACKEDGE]] [
-; CHECK-NEXT:    i32 0, label [[HEADER]]
-; CHECK-NEXT:    ]
-; CHECK:       outer_backedge:
-; CHECK-NEXT:    [[I_INC_LCSSA:%.*]] = phi i32 [ [[I_INC]], [[BACKEDGE]] ]
-; CHECK-NEXT:    [[J_INC]] = add i32 [[J]], 1
-; CHECK-NEXT:    [[CMP_J:%.*]] = icmp slt i32 [[J_INC]], [[END:%.*]]
-; CHECK-NEXT:    br i1 [[CMP_J]], label [[OUTER_HEADER]], label [[EXIT:%.*]]
-; CHECK:       exit:
-; CHECK-NEXT:    [[I_INC_LCSSA_LCSSA:%.*]] = phi i32 [ [[I_INC_LCSSA]], [[OUTER_BACKEDGE]] ]
-; CHECK-NEXT:    ret i32 [[I_INC_LCSSA_LCSSA]]
-;
-entry:
-  br label %outer_header
-
-outer_header:
-  %j = phi i32 [0, %entry], [%j.inc, %outer_backedge]
-  br label %preheader
-
-preheader:
-  br label %header
-
-header:
-  %i = phi i32 [0, %preheader], [%i.inc, %backedge]
-  br label  %live_part
-
-live_part:
-  %mul = mul i32 %i, %i
-  switch i32 1, label %dead [i32 0, label %backedge]
-
-dead:
-  %i.2 = add i32 %i, 1
-  br label %backedge
-
-backedge:
-  %i.1 = phi i32 [%i, %live_part], [%i.2, %dead]
-  %i.inc = add i32 %i.1, 1
-  switch i32 1, label %outer_backedge [i32 0, label %header]
-
-outer_backedge:
-  %j.inc = add i32 %j, 1
-  %cmp.j = icmp slt i32 %j.inc, %end
-  br i1 %cmp.j, label %outer_header, label %exit
-
-exit:
-  ret i32 %i.inc
-}
-
-; Inverted condition in live_part.
-define i32 @full_sub_loop_test_branch_loop_inverse_1(i32 %end) {
-; CHECK-LABEL: @full_sub_loop_test_branch_loop_inverse_1(
-; CHECK-NEXT:  entry:
-; CHECK-NEXT:    br label [[OUTER_HEADER:%.*]]
-; CHECK:       outer_header:
-; CHECK-NEXT:    [[J:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[J_INC:%.*]], [[OUTER_BACKEDGE:%.*]] ]
-; CHECK-NEXT:    br label [[HEADER:%.*]]
-; CHECK:       header:
-; CHECK-NEXT:    [[I:%.*]] = phi i32 [ 0, [[OUTER_HEADER]] ], [ [[I_INC:%.*]], [[BACKEDGE:%.*]] ]
-; CHECK-NEXT:    [[MUL:%.*]] = mul i32 [[I]], [[I]]
-; CHECK-NEXT:    br i1 true, label [[BACKEDGE]], label [[DEAD:%.*]]
-; CHECK:       dead:
-; CHECK-NEXT:    [[I_2:%.*]] = add i32 [[I]], 1
-; CHECK-NEXT:    br label [[BACKEDGE]]
-; CHECK:       backedge:
-; CHECK-NEXT:    [[I_1:%.*]] = phi i32 [ [[I]], [[HEADER]] ], [ [[I_2]], [[DEAD]] ]
-; CHECK-NEXT:    [[I_INC]] = add i32 [[I_1]], 1
-; CHECK-NEXT:    br i1 false, label [[HEADER]], label [[OUTER_BACKEDGE]]
-; CHECK:       outer_backedge:
-; CHECK-NEXT:    [[I_INC_LCSSA:%.*]] = phi i32 [ [[I_INC]], [[BACKEDGE]] ]
-; CHECK-NEXT:    [[J_INC]] = add i32 [[J]], 1
-; CHECK-NEXT:    [[CMP_J:%.*]] = icmp slt i32 [[J_INC]], [[END:%.*]]
-; CHECK-NEXT:    br i1 [[CMP_J]], label [[OUTER_HEADER]], label [[EXIT:%.*]]
-; CHECK:       exit:
-; CHECK-NEXT:    [[I_INC_LCSSA_LCSSA:%.*]] = phi i32 [ [[I_INC_LCSSA]], [[OUTER_BACKEDGE]] ]
-; CHECK-NEXT:    ret i32 [[I_INC_LCSSA_LCSSA]]
-;
-entry:
-  br label %outer_header
-
-outer_header:
-  %j = phi i32 [0, %entry], [%j.inc, %outer_backedge]
-  br label %preheader
-
-preheader:
-  br label %header
-
-header:
-  %i = phi i32 [0, %preheader], [%i.inc, %backedge]
-  br label  %live_part
-
-live_part:
-  %mul = mul i32 %i, %i
-  br i1 true, label %backedge, label %dead
-
-dead:
-  %i.2 = add i32 %i, 1
-  br label %backedge
-
-backedge:
-  %i.1 = phi i32 [%i, %live_part], [%i.2, %dead]
-  %i.inc = add i32 %i.1, 1
-  br i1 false, label %header, label %outer_backedge
-
-outer_backedge:
-  %j.inc = add i32 %j, 1
-  %cmp.j = icmp slt i32 %j.inc, %end
-  br i1 %cmp.j, label %outer_header, label %exit
-
-exit:
-  ret i32 %i.inc
-}
-
-define i32 @full_sub_loop_test_switch_loop_inverse_1(i32 %end) {
-; CHECK-LABEL: @full_sub_loop_test_switch_loop_inverse_1(
-; CHECK-NEXT:  entry:
-; CHECK-NEXT:    br label [[OUTER_HEADER:%.*]]
-; CHECK:       outer_header:
-; CHECK-NEXT:    [[J:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[J_INC:%.*]], [[OUTER_BACKEDGE:%.*]] ]
-; CHECK-NEXT:    br label [[HEADER:%.*]]
-; CHECK:       header:
-; CHECK-NEXT:    [[I:%.*]] = phi i32 [ 0, [[OUTER_HEADER]] ], [ [[I_INC:%.*]], [[BACKEDGE:%.*]] ]
-; CHECK-NEXT:    [[MUL:%.*]] = mul i32 [[I]], [[I]]
-; CHECK-NEXT:    switch i32 1, label [[BACKEDGE]] [
-; CHECK-NEXT:    i32 0, label [[DEAD:%.*]]
-; CHECK-NEXT:    ]
-; CHECK:       dead:
-; CHECK-NEXT:    [[I_2:%.*]] = add i32 [[I]], 1
-; CHECK-NEXT:    br label [[BACKEDGE]]
-; CHECK:       backedge:
-; CHECK-NEXT:    [[I_1:%.*]] = phi i32 [ [[I]], [[HEADER]] ], [ [[I_2]], [[DEAD]] ]
-; CHECK-NEXT:    [[I_INC]] = add i32 [[I_1]], 1
-; CHECK-NEXT:    switch i32 1, label [[OUTER_BACKEDGE]] [
-; CHECK-NEXT:    i32 0, label [[HEADER]]
-; CHECK-NEXT:    ]
-; CHECK:       outer_backedge:
-; CHECK-NEXT:    [[I_INC_LCSSA:%.*]] = phi i32 [ [[I_INC]], [[BACKEDGE]] ]
-; CHECK-NEXT:    [[J_INC]] = add i32 [[J]], 1
-; CHECK-NEXT:    [[CMP_J:%.*]] = icmp slt i32 [[J_INC]], [[END:%.*]]
-; CHECK-NEXT:    br i1 [[CMP_J]], label [[OUTER_HEADER]], label [[EXIT:%.*]]
-; CHECK:       exit:
-; CHECK-NEXT:    [[I_INC_LCSSA_LCSSA:%.*]] = phi i32 [ [[I_INC_LCSSA]], [[OUTER_BACKEDGE]] ]
-; CHECK-NEXT:    ret i32 [[I_INC_LCSSA_LCSSA]]
-;
-entry:
-  br label %outer_header
-
-outer_header:
-  %j = phi i32 [0, %entry], [%j.inc, %outer_backedge]
-  br label %preheader
-
-preheader:
-  br label %header
-
-header:
-  %i = phi i32 [0, %preheader], [%i.inc, %backedge]
-  br label  %live_part
-
-live_part:
-  %mul = mul i32 %i, %i
-  switch i32 1, label %backedge [i32 0, label %dead]
-
-dead:
-  %i.2 = add i32 %i, 1
-  br label %backedge
-
-backedge:
-  %i.1 = phi i32 [%i, %live_part], [%i.2, %dead]
-  %i.inc = add i32 %i.1, 1
-  switch i32 1, label %outer_backedge [i32 0, label %header]
-
-outer_backedge:
-  %j.inc = add i32 %j, 1
-  %cmp.j = icmp slt i32 %j.inc, %end
-  br i1 %cmp.j, label %outer_header, label %exit
-
-exit:
-  ret i32 %i.inc
-}
-
-define i32 @full_sub_loop_test_branch_loop_inverse_2(i32 %end) {
-; CHECK-LABEL: @full_sub_loop_test_branch_loop_inverse_2(
-; CHECK-NEXT:  entry:
-; CHECK-NEXT:    br label [[OUTER_HEADER:%.*]]
-; CHECK:       outer_header:
-; CHECK-NEXT:    [[J:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[J_INC:%.*]], [[OUTER_BACKEDGE:%.*]] ]
-; CHECK-NEXT:    switch i32 0, label [[PREHEADER_SPLIT:%.*]] [
-; CHECK-NEXT:    i32 1, label [[OUTER_BACKEDGE]]
-; CHECK-NEXT:    ]
-; CHECK:       preheader.split:
-; CHECK-NEXT:    br label [[HEADER:%.*]]
-; CHECK:       header:
-; CHECK-NEXT:    [[I:%.*]] = phi i32 [ 0, [[PREHEADER_SPLIT]] ], [ [[I_INC:%.*]], [[HEADER]] ]
-; CHECK-NEXT:    [[MUL:%.*]] = mul i32 [[I]], [[I]]
-; CHECK-NEXT:    [[I_2:%.*]] = add i32 [[I]], 1
-; CHECK-NEXT:    [[I_INC]] = add i32 [[I_2]], 1
-; CHECK-NEXT:    br label [[HEADER]]
-; CHECK:       outer_backedge:
-; CHECK-NEXT:    [[J_INC]] = add i32 [[J]], 1
-; CHECK-NEXT:    [[CMP_J:%.*]] = icmp slt i32 [[J_INC]], [[END:%.*]]
-; CHECK-NEXT:    br i1 [[CMP_J]], label [[OUTER_HEADER]], label [[EXIT:%.*]]
-; CHECK:       exit:
-; CHECK-NEXT:    [[I_INC_LCSSA_LCSSA:%.*]] = phi i32 [ undef, [[OUTER_BACKEDGE]] ]
-; CHECK-NEXT:    ret i32 [[I_INC_LCSSA_LCSSA]]
-;
-entry:
-  br label %outer_header
-
-outer_header:
-  %j = phi i32 [0, %entry], [%j.inc, %outer_backedge]
-  br label %preheader
-
-preheader:
-  br label %header
-
-header:
-  %i = phi i32 [0, %preheader], [%i.inc, %backedge]
-  br label  %live_part
-
-live_part:
-  %mul = mul i32 %i, %i
-  br i1 false, label %backedge, label %dead
-
-dead:
-  %i.2 = add i32 %i, 1
-  br label %backedge
-
-backedge:
-  %i.1 = phi i32 [%i, %live_part], [%i.2, %dead]
-  %i.inc = add i32 %i.1, 1
-  br i1 true, label %header, label %outer_backedge
-
-outer_backedge:
-  %j.inc = add i32 %j, 1
-  %cmp.j = icmp slt i32 %j.inc, %end
-  br i1 %cmp.j, label %outer_header, label %exit
-
-exit:
-  ret i32 %i.inc
-}
-
-define i32 @full_sub_loop_test_switch_loop_inverse_2(i32 %end) {
-; CHECK-LABEL: @full_sub_loop_test_switch_loop_inverse_2(
-; CHECK-NEXT:  entry:
-; CHECK-NEXT:    br label [[OUTER_HEADER:%.*]]
-; CHECK:       outer_header:
-; CHECK-NEXT:    [[J:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[J_INC:%.*]], [[OUTER_BACKEDGE:%.*]] ]
-; CHECK-NEXT:    switch i32 0, label [[PREHEADER_SPLIT:%.*]] [
-; CHECK-NEXT:    i32 1, label [[OUTER_BACKEDGE]]
-; CHECK-NEXT:    ]
-; CHECK:       preheader.split:
-; CHECK-NEXT:    br label [[HEADER:%.*]]
-; CHECK:       header:
-; CHECK-NEXT:    [[I:%.*]] = phi i32 [ 0, [[PREHEADER_SPLIT]] ], [ [[I_INC:%.*]], [[HEADER]] ]
-; CHECK-NEXT:    [[MUL:%.*]] = mul i32 [[I]], [[I]]
-; CHECK-NEXT:    [[I_2:%.*]] = add i32 [[I]], 1
-; CHECK-NEXT:    [[I_INC]] = add i32 [[I_2]], 1
-; CHECK-NEXT:    br label [[HEADER]]
-; CHECK:       outer_backedge:
-; CHECK-NEXT:    [[J_INC]] = add i32 [[J]], 1
-; CHECK-NEXT:    [[CMP_J:%.*]] = icmp slt i32 [[J_INC]], [[END:%.*]]
-; CHECK-NEXT:    br i1 [[CMP_J]], label [[OUTER_HEADER]], label [[EXIT:%.*]]
-; CHECK:       exit:
-; CHECK-NEXT:    [[I_INC_LCSSA_LCSSA:%.*]] = phi i32 [ undef, [[OUTER_BACKEDGE]] ]
-; CHECK-NEXT:    ret i32 [[I_INC_LCSSA_LCSSA]]
-;
-entry:
-  br label %outer_header
-
-outer_header:
-  %j = phi i32 [0, %entry], [%j.inc, %outer_backedge]
-  br label %preheader
-
-preheader:
-  br label %header
-
-header:
-  %i = phi i32 [0, %preheader], [%i.inc, %backedge]
-  br label  %live_part
-
-live_part:
-  %mul = mul i32 %i, %i
-  switch i32 1, label %dead [i32 0, label %backedge]
-
-dead:
-  %i.2 = add i32 %i, 1
-  br label %backedge
-
-backedge:
-  %i.1 = phi i32 [%i, %live_part], [%i.2, %dead]
-  %i.inc = add i32 %i.1, 1
-  switch i32 1, label %header [i32 0, label %outer_backedge]
-
-outer_backedge:
-  %j.inc = add i32 %j, 1
-  %cmp.j = icmp slt i32 %j.inc, %end
-  br i1 %cmp.j, label %outer_header, label %exit
-
-exit:
-  ret i32 %i.inc
-}
-
-
-define i32 @full_sub_loop_test_branch_loop_inverse_3(i32 %end) {
-; CHECK-LABEL: @full_sub_loop_test_branch_loop_inverse_3(
-; CHECK-NEXT:  entry:
-; CHECK-NEXT:    br label [[OUTER_HEADER:%.*]]
-; CHECK:       outer_header:
-; CHECK-NEXT:    [[J:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[J_INC:%.*]], [[OUTER_BACKEDGE:%.*]] ]
-; CHECK-NEXT:    switch i32 0, label [[PREHEADER_SPLIT:%.*]] [
-; CHECK-NEXT:    i32 1, label [[OUTER_BACKEDGE]]
-; CHECK-NEXT:    ]
-; CHECK:       preheader.split:
-; CHECK-NEXT:    br label [[HEADER:%.*]]
-; CHECK:       header:
-; CHECK-NEXT:    [[I:%.*]] = phi i32 [ 0, [[PREHEADER_SPLIT]] ], [ [[I_INC:%.*]], [[HEADER]] ]
-; CHECK-NEXT:    [[MUL:%.*]] = mul i32 [[I]], [[I]]
-; CHECK-NEXT:    [[I_INC]] = add i32 [[I]], 1
-; CHECK-NEXT:    br label [[HEADER]]
-; CHECK:       outer_backedge:
-; CHECK-NEXT:    [[J_INC]] = add i32 [[J]], 1
-; CHECK-NEXT:    [[CMP_J:%.*]] = icmp slt i32 [[J_INC]], [[END:%.*]]
-; CHECK-NEXT:    br i1 [[CMP_J]], label [[OUTER_HEADER]], label [[EXIT:%.*]]
-; CHECK:       exit:
-; CHECK-NEXT:    [[I_INC_LCSSA_LCSSA:%.*]] = phi i32 [ undef, [[OUTER_BACKEDGE]] ]
-; CHECK-NEXT:    ret i32 [[I_INC_LCSSA_LCSSA]]
-;
-entry:
-  br label %outer_header
-
-outer_header:
-  %j = phi i32 [0, %entry], [%j.inc, %outer_backedge]
-  br label %preheader
-
-preheader:
-  br label %header
-
-header:
-  %i = phi i32 [0, %preheader], [%i.inc, %backedge]
-  br label  %live_part
-
-live_part:
-  %mul = mul i32 %i, %i
-  br i1 true, label %backedge, label %dead
-
-dead:
-  %i.2 = add i32 %i, 1
-  br label %backedge
-
-backedge:
-  %i.1 = phi i32 [%i, %live_part], [%i.2, %dead]
-  %i.inc = add i32 %i.1, 1
-  br i1 true, label %header, label %outer_backedge
-
-outer_backedge:
-  %j.inc = add i32 %j, 1
-  %cmp.j = icmp slt i32 %j.inc, %end
-  br i1 %cmp.j, label %outer_header, label %exit
-
-exit:
-  ret i32 %i.inc
-}
-
-define i32 @full_sub_loop_test_switch_loop_inverse_3(i32 %end) {
-; CHECK-LABEL: @full_sub_loop_test_switch_loop_inverse_3(
-; CHECK-NEXT:  entry:
-; CHECK-NEXT:    br label [[OUTER_HEADER:%.*]]
-; CHECK:       outer_header:
-; CHECK-NEXT:    [[J:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[J_INC:%.*]], [[OUTER_BACKEDGE:%.*]] ]
-; CHECK-NEXT:    switch i32 0, label [[PREHEADER_SPLIT:%.*]] [
-; CHECK-NEXT:    i32 1, label [[OUTER_BACKEDGE]]
-; CHECK-NEXT:    ]
-; CHECK:       preheader.split:
-; CHECK-NEXT:    br label [[HEADER:%.*]]
-; CHECK:       header:
-; CHECK-NEXT:    [[I:%.*]] = phi i32 [ 0, [[PREHEADER_SPLIT]] ], [ [[I_INC:%.*]], [[HEADER]] ]
-; CHECK-NEXT:    [[MUL:%.*]] = mul i32 [[I]], [[I]]
-; CHECK-NEXT:    [[I_INC]] = add i32 [[I]], 1
-; CHECK-NEXT:    br label [[HEADER]]
-; CHECK:       outer_backedge:
-; CHECK-NEXT:    [[J_INC]] = add i32 [[J]], 1
-; CHECK-NEXT:    [[CMP_J:%.*]] = icmp slt i32 [[J_INC]], [[END:%.*]]
-; CHECK-NEXT:    br i1 [[CMP_J]], label [[OUTER_HEADER]], label [[EXIT:%.*]]
-; CHECK:       exit:
-; CHECK-NEXT:    [[I_INC_LCSSA_LCSSA:%.*]] = phi i32 [ undef, [[OUTER_BACKEDGE]] ]
-; CHECK-NEXT:    ret i32 [[I_INC_LCSSA_LCSSA]]
-;
-entry:
-  br label %outer_header
-
-outer_header:
-  %j = phi i32 [0, %entry], [%j.inc, %outer_backedge]
-  br label %preheader
-
-preheader:
-  br label %header
-
-header:
-  %i = phi i32 [0, %preheader], [%i.inc, %backedge]
-  br label  %live_part
-
-live_part:
-  %mul = mul i32 %i, %i
-  switch i32 1, label %backedge [i32 0, label %dead]
-
-dead:
-  %i.2 = add i32 %i, 1
-  br label %backedge
-
-backedge:
-  %i.1 = phi i32 [%i, %live_part], [%i.2, %dead]
-  %i.inc = add i32 %i.1, 1
-  switch i32 1, label %header [i32 0, label %outer_backedge]
-
-outer_backedge:
-  %j.inc = add i32 %j, 1
-  %cmp.j = icmp slt i32 %j.inc, %end
-  br i1 %cmp.j, label %outer_header, label %exit
-
-exit:
-  ret i32 %i.inc
-}
-
-define i32 @exit_branch_from_inner_to_grandparent(i1 %cond1, i1 %cond2, i32 %N) {
-; CHECK-LABEL: @exit_branch_from_inner_to_grandparent(
-; CHECK-NEXT:  preheader:
-; CHECK-NEXT:    br label [[LOOP_1:%.*]]
-; CHECK:       loop_1:
-; CHECK-NEXT:    [[I:%.*]] = phi i32 [ 0, [[PREHEADER:%.*]] ], [ [[I_NEXT:%.*]], [[LOOP_1_BACKEDGE:%.*]] ]
-; CHECK-NEXT:    br label [[LOOP_2:%.*]]
-; CHECK:       loop_2:
-; CHECK-NEXT:    [[J:%.*]] = phi i32 [ 0, [[LOOP_1]] ], [ [[J_NEXT:%.*]], [[LOOP_2_BACKEDGE:%.*]] ]
-; CHECK-NEXT:    switch i32 0, label [[LOOP_2_SPLIT:%.*]] [
-; CHECK-NEXT:    i32 1, label [[LOOP_2_BACKEDGE]]
-; CHECK-NEXT:    ]
-; CHECK:       loop_2.split:
-; CHECK-NEXT:    br label [[LOOP_3:%.*]]
-; CHECK:       loop_3:
-; CHECK-NEXT:    [[K:%.*]] = phi i32 [ 0, [[LOOP_2_SPLIT]] ], [ [[K_NEXT:%.*]], [[LOOP_3_BACKEDGE:%.*]] ]
-; CHECK-NEXT:    br i1 [[COND1:%.*]], label [[LOOP_3_BACKEDGE]], label [[LOOP_1_BACKEDGE_LOOPEXIT:%.*]]
-; CHECK:       loop_3_backedge:
-; CHECK-NEXT:    [[K_NEXT]] = add i32 [[K]], 1
-; CHECK-NEXT:    br label [[LOOP_3]]
-; CHECK:       loop_2_backedge:
-; CHECK-NEXT:    [[J_NEXT]] = add i32 [[J]], 1
-; CHECK-NEXT:    [[C_2:%.*]] = icmp slt i32 [[J_NEXT]], [[N:%.*]]
-; CHECK-NEXT:    br i1 [[C_2]], label [[LOOP_2]], label [[LOOP_1_BACKEDGE_LOOPEXIT1:%.*]]
-; CHECK:       loop_1_backedge.loopexit:
-; CHECK-NEXT:    br label [[LOOP_1_BACKEDGE]]
-; CHECK:       loop_1_backedge.loopexit1:
-; CHECK-NEXT:    br label [[LOOP_1_BACKEDGE]]
-; CHECK:       loop_1_backedge:
-; CHECK-NEXT:    [[I_NEXT]] = add i32 [[I]], 1
-; CHECK-NEXT:    [[C_1:%.*]] = icmp slt i32 [[I_NEXT]], [[N]]
-; CHECK-NEXT:    br i1 [[C_1]], label [[LOOP_1]], label [[EXIT:%.*]]
-; CHECK:       exit:
-; CHECK-NEXT:    [[I_LCSSA:%.*]] = phi i32 [ [[I]], [[LOOP_1_BACKEDGE]] ]
-; CHECK-NEXT:    ret i32 [[I_LCSSA]]
-;
-preheader:
-  br label %loop_1
-
-loop_1:
-  %i = phi i32 [ 0, %preheader ], [ %i.next, %loop_1_backedge ]
-  br label %loop_2
-
-loop_2:
-  %j = phi i32 [ 0, %loop_1 ], [ %j.next, %loop_2_backedge ]
-  br label %loop_3
-
-loop_3:
-  %k = phi i32 [ 0, %loop_2 ], [ %k.next, %loop_3_backedge ]
-  br i1 %cond1, label %loop_3_backedge, label %loop_1_backedge
-
-loop_3_backedge:
-  %k.next = add i32 %k, 1
-  br i1 true, label %loop_3, label %loop_2_backedge
-
-loop_2_backedge:
-  %j.next = add i32 %j, 1
-  %c_2 = icmp slt i32 %j.next, %N
-  br i1 %c_2, label %loop_2, label %loop_1_backedge
-
-loop_1_backedge:
-  %i.next = add i32 %i, 1
-  %c_1 = icmp slt i32 %i.next, %N
-  br i1 %c_1, label %loop_1, label %exit
-
-exit:
-  ret i32 %i
-}
-
-define i32 @exit_switch_from_inner_to_grandparent(i1 %cond1, i1 %cond2, i32 %N) {
-; CHECK-LABEL: @exit_switch_from_inner_to_grandparent(
-; CHECK-NEXT:  preheader:
-; CHECK-NEXT:    br label [[LOOP_1:%.*]]
-; CHECK:       loop_1:
-; CHECK-NEXT:    [[I:%.*]] = phi i32 [ 0, [[PREHEADER:%.*]] ], [ [[I_NEXT:%.*]], [[LOOP_1_BACKEDGE:%.*]] ]
-; CHECK-NEXT:    br label [[LOOP_2:%.*]]
-; CHECK:       loop_2:
-; CHECK-NEXT:    [[J:%.*]] = phi i32 [ 0, [[LOOP_1]] ], [ [[J_NEXT:%.*]], [[LOOP_2_BACKEDGE:%.*]] ]
-; CHECK-NEXT:    switch i32 0, label [[LOOP_2_SPLIT:%.*]] [
-; CHECK-NEXT:    i32 1, label [[LOOP_2_BACKEDGE]]
-; CHECK-NEXT:    ]
-; CHECK:       loop_2.split:
-; CHECK-NEXT:    br label [[LOOP_3:%.*]]
-; CHECK:       loop_3:
-; CHECK-NEXT:    [[K:%.*]] = phi i32 [ 0, [[LOOP_2_SPLIT]] ], [ [[K_NEXT:%.*]], [[LOOP_3_BACKEDGE:%.*]] ]
-; CHECK-NEXT:    br i1 [[COND1:%.*]], label [[LOOP_3_BACKEDGE]], label [[LOOP_1_BACKEDGE_LOOPEXIT:%.*]]
-; CHECK:       loop_3_backedge:
-; CHECK-NEXT:    [[K_NEXT]] = add i32 [[K]], 1
-; CHECK-NEXT:    br label [[LOOP_3]]
-; CHECK:       loop_2_backedge:
-; CHECK-NEXT:    [[J_NEXT]] = add i32 [[J]], 1
-; CHECK-NEXT:    [[C_2:%.*]] = icmp slt i32 [[J_NEXT]], [[N:%.*]]
-; CHECK-NEXT:    br i1 [[C_2]], label [[LOOP_2]], label [[LOOP_1_BACKEDGE_LOOPEXIT1:%.*]]
-; CHECK:       loop_1_backedge.loopexit:
-; CHECK-NEXT:    br label [[LOOP_1_BACKEDGE]]
-; CHECK:       loop_1_backedge.loopexit1:
-; CHECK-NEXT:    br label [[LOOP_1_BACKEDGE]]
-; CHECK:       loop_1_backedge:
-; CHECK-NEXT:    [[I_NEXT]] = add i32 [[I]], 1
-; CHECK-NEXT:    [[C_1:%.*]] = icmp slt i32 [[I_NEXT]], [[N]]
-; CHECK-NEXT:    br i1 [[C_1]], label [[LOOP_1]], label [[EXIT:%.*]]
-; CHECK:       exit:
-; CHECK-NEXT:    [[I_LCSSA:%.*]] = phi i32 [ [[I]], [[LOOP_1_BACKEDGE]] ]
-; CHECK-NEXT:    ret i32 [[I_LCSSA]]
-;
-preheader:
-  br label %loop_1
-
-loop_1:
-  %i = phi i32 [ 0, %preheader ], [ %i.next, %loop_1_backedge ]
-  br label %loop_2
-
-loop_2:
-  %j = phi i32 [ 0, %loop_1 ], [ %j.next, %loop_2_backedge ]
-  br label %loop_3
-
-loop_3:
-  %k = phi i32 [ 0, %loop_2 ], [ %k.next, %loop_3_backedge ]
-  br i1 %cond1, label %loop_3_backedge, label %loop_1_backedge
-
-loop_3_backedge:
-  %k.next = add i32 %k, 1
-  switch i32 1, label %loop_3 [i32 0, label %loop_2_backedge]
-
-loop_2_backedge:
-  %j.next = add i32 %j, 1
-  %c_2 = icmp slt i32 %j.next, %N
-  br i1 %c_2, label %loop_2, label %loop_1_backedge
-
-loop_1_backedge:
-  %i.next = add i32 %i, 1
-  %c_1 = icmp slt i32 %i.next, %N
-  br i1 %c_1, label %loop_1, label %exit
-
-exit:
-  ret i32 %i
-}
-
-define i32 @intermediate_branch_from_inner_to_grandparent(i1 %cond1, i1 %cond2, i32 %N) {
-; CHECK-LABEL: @intermediate_branch_from_inner_to_grandparent(
-; CHECK-NEXT:  preheader:
-; CHECK-NEXT:    br label [[LOOP_1:%.*]]
-; CHECK:       loop_1:
-; CHECK-NEXT:    [[I:%.*]] = phi i32 [ 0, [[PREHEADER:%.*]] ], [ [[I_NEXT:%.*]], [[LOOP_1_BACKEDGE:%.*]] ]
-; CHECK-NEXT:    br label [[LOOP_2:%.*]]
-; CHECK:       loop_2:
-; CHECK-NEXT:    [[J:%.*]] = phi i32 [ 0, [[LOOP_1]] ], [ [[J_NEXT:%.*]], [[LOOP_2_BACKEDGE:%.*]] ]
-; CHECK-NEXT:    br label [[LOOP_3:%.*]]
-; CHECK:       loop_3:
-; CHECK-NEXT:    [[K:%.*]] = phi i32 [ 0, [[LOOP_2]] ], [ [[K_NEXT:%.*]], [[LOOP_3_BACKEDGE:%.*]] ]
-; CHECK-NEXT:    br i1 [[COND1:%.*]], label [[LOOP_3_BACKEDGE]], label [[INTERMEDIATE:%.*]]
-; CHECK:       intermediate:
-; CHECK-NEXT:    br i1 false, label [[LOOP_3_BACKEDGE]], label [[LOOP_1_BACKEDGE_LOOPEXIT:%.*]]
-; CHECK:       loop_3_backedge:
-; CHECK-NEXT:    [[K_NEXT]] = add i32 [[K]], 1
-; CHECK-NEXT:    br i1 [[COND2:%.*]], label [[LOOP_3]], label [[LOOP_2_BACKEDGE]]
-; CHECK:       loop_2_backedge:
-; CHECK-NEXT:    [[J_NEXT]] = add i32 [[J]], 1
-; CHECK-NEXT:    [[C_2:%.*]] = icmp slt i32 [[J_NEXT]], [[N:%.*]]
-; CHECK-NEXT:    br i1 [[C_2]], label [[LOOP_2]], label [[LOOP_1_BACKEDGE_LOOPEXIT1:%.*]]
-; CHECK:       loop_1_backedge.loopexit:
-; CHECK-NEXT:    br label [[LOOP_1_BACKEDGE]]
-; CHECK:       loop_1_backedge.loopexit1:
-; CHECK-NEXT:    br label [[LOOP_1_BACKEDGE]]
-; CHECK:       loop_1_backedge:
-; CHECK-NEXT:    [[I_NEXT]] = add i32 [[I]], 1
-; CHECK-NEXT:    [[C_1:%.*]] = icmp slt i32 [[I_NEXT]], [[N]]
-; CHECK-NEXT:    br i1 [[C_1]], label [[LOOP_1]], label [[EXIT:%.*]]
-; CHECK:       exit:
-; CHECK-NEXT:    [[I_LCSSA:%.*]] = phi i32 [ [[I]], [[LOOP_1_BACKEDGE]] ]
-; CHECK-NEXT:    ret i32 [[I_LCSSA]]
-;
-preheader:
-  br label %loop_1
-
-loop_1:
-  %i = phi i32 [ 0, %preheader ], [ %i.next, %loop_1_backedge ]
-  br label %loop_2
-
-loop_2:
-  %j = phi i32 [ 0, %loop_1 ], [ %j.next, %loop_2_backedge ]
-  br label %loop_3
-
-loop_3:
-  %k = phi i32 [ 0, %loop_2 ], [ %k.next, %loop_3_backedge ]
-  br i1 %cond1, label %loop_3_backedge, label %intermediate
-
-intermediate:
-  br i1 false, label %loop_3_backedge, label %loop_1_backedge
-
-loop_3_backedge:
-  %k.next = add i32 %k, 1
-  br i1 %cond2, label %loop_3, label %loop_2_backedge
-
-loop_2_backedge:
-  %j.next = add i32 %j, 1
-  %c_2 = icmp slt i32 %j.next, %N
-  br i1 %c_2, label %loop_2, label %loop_1_backedge
-
-loop_1_backedge:
-  %i.next = add i32 %i, 1
-  %c_1 = icmp slt i32 %i.next, %N
-  br i1 %c_1, label %loop_1, label %exit
-
-exit:
-  ret i32 %i
-}
-
-define i32 @intermediate_switch_from_inner_to_grandparent(i1 %cond1, i1 %cond2, i32 %N) {
-; CHECK-LABEL: @intermediate_switch_from_inner_to_grandparent(
-; CHECK-NEXT:  preheader:
-; CHECK-NEXT:    br label [[LOOP_1:%.*]]
-; CHECK:       loop_1:
-; CHECK-NEXT:    [[I:%.*]] = phi i32 [ 0, [[PREHEADER:%.*]] ], [ [[I_NEXT:%.*]], [[LOOP_1_BACKEDGE:%.*]] ]
-; CHECK-NEXT:    br label [[LOOP_2:%.*]]
-; CHECK:       loop_2:
-; CHECK-NEXT:    [[J:%.*]] = phi i32 [ 0, [[LOOP_1]] ], [ [[J_NEXT:%.*]], [[LOOP_2_BACKEDGE:%.*]] ]
-; CHECK-NEXT:    br label [[LOOP_3:%.*]]
-; CHECK:       loop_3:
-; CHECK-NEXT:    [[K:%.*]] = phi i32 [ 0, [[LOOP_2]] ], [ [[K_NEXT:%.*]], [[LOOP_3_BACKEDGE:%.*]] ]
-; CHECK-NEXT:    br i1 [[COND1:%.*]], label [[LOOP_3_BACKEDGE]], label [[INTERMEDIATE:%.*]]
-; CHECK:       intermediate:
-; CHECK-NEXT:    switch i32 1, label [[LOOP_1_BACKEDGE_LOOPEXIT:%.*]] [
-; CHECK-NEXT:    i32 0, label [[LOOP_3_BACKEDGE]]
-; CHECK-NEXT:    ]
-; CHECK:       loop_3_backedge:
-; CHECK-NEXT:    [[K_NEXT]] = add i32 [[K]], 1
-; CHECK-NEXT:    br i1 [[COND2:%.*]], label [[LOOP_3]], label [[LOOP_2_BACKEDGE]]
-; CHECK:       loop_2_backedge:
-; CHECK-NEXT:    [[J_NEXT]] = add i32 [[J]], 1
-; CHECK-NEXT:    [[C_2:%.*]] = icmp slt i32 [[J_NEXT]], [[N:%.*]]
-; CHECK-NEXT:    br i1 [[C_2]], label [[LOOP_2]], label [[LOOP_1_BACKEDGE_LOOPEXIT1:%.*]]
-; CHECK:       loop_1_backedge.loopexit:
-; CHECK-NEXT:    br label [[LOOP_1_BACKEDGE]]
-; CHECK:       loop_1_backedge.loopexit1:
-; CHECK-NEXT:    br label [[LOOP_1_BACKEDGE]]
-; CHECK:       loop_1_backedge:
-; CHECK-NEXT:    [[I_NEXT]] = add i32 [[I]], 1
-; CHECK-NEXT:    [[C_1:%.*]] = icmp slt i32 [[I_NEXT]], [[N]]
-; CHECK-NEXT:    br i1 [[C_1]], label [[LOOP_1]], label [[EXIT:%.*]]
-; CHECK:       exit:
-; CHECK-NEXT:    [[I_LCSSA:%.*]] = phi i32 [ [[I]], [[LOOP_1_BACKEDGE]] ]
-; CHECK-NEXT:    ret i32 [[I_LCSSA]]
-;
-preheader:
-  br label %loop_1
-
-loop_1:
-  %i = phi i32 [ 0, %preheader ], [ %i.next, %loop_1_backedge ]
-  br label %loop_2
-
-loop_2:
-  %j = phi i32 [ 0, %loop_1 ], [ %j.next, %loop_2_backedge ]
-  br label %loop_3
-
-loop_3:
-  %k = phi i32 [ 0, %loop_2 ], [ %k.next, %loop_3_backedge ]
-  br i1 %cond1, label %loop_3_backedge, label %intermediate
-
-intermediate:
-  switch i32 1, label %loop_1_backedge [i32 0, label %loop_3_backedge]
-
-loop_3_backedge:
-  %k.next = add i32 %k, 1
-  br i1 %cond2, label %loop_3, label %loop_2_backedge
-
-loop_2_backedge:
-  %j.next = add i32 %j, 1
-  %c_2 = icmp slt i32 %j.next, %N
-  br i1 %c_2, label %loop_2, label %loop_1_backedge
-
-loop_1_backedge:
-  %i.next = add i32 %i, 1
-  %c_1 = icmp slt i32 %i.next, %N
-  br i1 %c_1, label %loop_1, label %exit
-
-exit:
-  ret i32 %i
-}
-
-define i32 @intermediate_branch_from_inner_to_parent(i1 %cond1, i1 %cond2, i32 %N) {
-; CHECK-LABEL: @intermediate_branch_from_inner_to_parent(
-; CHECK-NEXT:  preheader:
-; CHECK-NEXT:    br label [[LOOP_1:%.*]]
-; CHECK:       loop_1:
-; CHECK-NEXT:    [[I:%.*]] = phi i32 [ 0, [[PREHEADER:%.*]] ], [ [[I_NEXT:%.*]], [[LOOP_1_BACKEDGE:%.*]] ]
-; CHECK-NEXT:    br label [[LOOP_2:%.*]]
-; CHECK:       loop_2:
-; CHECK-NEXT:    [[J:%.*]] = phi i32 [ 0, [[LOOP_1]] ], [ [[J_NEXT:%.*]], [[LOOP_2_BACKEDGE:%.*]] ]
-; CHECK-NEXT:    br label [[LOOP_3:%.*]]
-; CHECK:       loop_3:
-; CHECK-NEXT:    [[K:%.*]] = phi i32 [ 0, [[LOOP_2]] ], [ [[K_NEXT:%.*]], [[LOOP_3_BACKEDGE:%.*]] ]
-; CHECK-NEXT:    br i1 [[COND1:%.*]], label [[LOOP_3_BACKEDGE]], label [[INTERMEDIATE:%.*]]
-; CHECK:       intermediate:
-; CHECK-NEXT:    br i1 false, label [[LOOP_3_BACKEDGE]], label [[LOOP_2_BACKEDGE]]
-; CHECK:       loop_3_backedge:
-; CHECK-NEXT:    [[K_NEXT]] = add i32 [[K]], 1
-; CHECK-NEXT:    br i1 [[COND2:%.*]], label [[LOOP_3]], label [[LOOP_2_BACKEDGE]]
-; CHECK:       loop_2_backedge:
-; CHECK-NEXT:    [[J_NEXT]] = add i32 [[J]], 1
-; CHECK-NEXT:    [[C_2:%.*]] = icmp slt i32 [[J_NEXT]], [[N:%.*]]
-; CHECK-NEXT:    br i1 [[C_2]], label [[LOOP_2]], label [[LOOP_1_BACKEDGE]]
-; CHECK:       loop_1_backedge:
-; CHECK-NEXT:    [[I_NEXT]] = add i32 [[I]], 1
-; CHECK-NEXT:    [[C_1:%.*]] = icmp slt i32 [[I_NEXT]], [[N]]
-; CHECK-NEXT:    br i1 [[C_1]], label [[LOOP_1]], label [[EXIT:%.*]]
-; CHECK:       exit:
-; CHECK-NEXT:    [[I_LCSSA:%.*]] = phi i32 [ [[I]], [[LOOP_1_BACKEDGE]] ]
-; CHECK-NEXT:    ret i32 [[I_LCSSA]]
-;
-preheader:
-  br label %loop_1
-
-loop_1:
-  %i = phi i32 [ 0, %preheader ], [ %i.next, %loop_1_backedge ]
-  br label %loop_2
-
-loop_2:
-  %j = phi i32 [ 0, %loop_1 ], [ %j.next, %loop_2_backedge ]
-  br label %loop_3
-
-loop_3:
-  %k = phi i32 [ 0, %loop_2 ], [ %k.next, %loop_3_backedge ]
-  br i1 %cond1, label %loop_3_backedge, label %intermediate
-
-intermediate:
-  br i1 false, label %loop_3_backedge, label %loop_2_backedge
-
-loop_3_backedge:
-  %k.next = add i32 %k, 1
-  br i1 %cond2, label %loop_3, label %loop_2_backedge
-
-loop_2_backedge:
-  %j.next = add i32 %j, 1
-  %c_2 = icmp slt i32 %j.next, %N
-  br i1 %c_2, label %loop_2, label %loop_1_backedge
-
-loop_1_backedge:
-  %i.next = add i32 %i, 1
-  %c_1 = icmp slt i32 %i.next, %N
-  br i1 %c_1, label %loop_1, label %exit
-
-exit:
-  ret i32 %i
-}
-
-define i32 @intermediate_switch_from_inner_to_parent(i1 %cond1, i1 %cond2, i32 %N) {
-; CHECK-LABEL: @intermediate_switch_from_inner_to_parent(
-; CHECK-NEXT:  preheader:
-; CHECK-NEXT:    br label [[LOOP_1:%.*]]
-; CHECK:       loop_1:
-; CHECK-NEXT:    [[I:%.*]] = phi i32 [ 0, [[PREHEADER:%.*]] ], [ [[I_NEXT:%.*]], [[LOOP_1_BACKEDGE:%.*]] ]
-; CHECK-NEXT:    br label [[LOOP_2:%.*]]
-; CHECK:       loop_2:
-; CHECK-NEXT:    [[J:%.*]] = phi i32 [ 0, [[LOOP_1]] ], [ [[J_NEXT:%.*]], [[LOOP_2_BACKEDGE:%.*]] ]
-; CHECK-NEXT:    br label [[LOOP_3:%.*]]
-; CHECK:       loop_3:
-; CHECK-NEXT:    [[K:%.*]] = phi i32 [ 0, [[LOOP_2]] ], [ [[K_NEXT:%.*]], [[LOOP_3_BACKEDGE:%.*]] ]
-; CHECK-NEXT:    br i1 [[COND1:%.*]], label [[LOOP_3_BACKEDGE]], label [[INTERMEDIATE:%.*]]
-; CHECK:       intermediate:
-; CHECK-NEXT:    switch i32 1, label [[LOOP_2_BACKEDGE]] [
-; CHECK-NEXT:    i32 0, label [[LOOP_3_BACKEDGE]]
-; CHECK-NEXT:    ]
-; CHECK:       loop_3_backedge:
-; CHECK-NEXT:    [[K_NEXT]] = add i32 [[K]], 1
-; CHECK-NEXT:    br i1 [[COND2:%.*]], label [[LOOP_3]], label [[LOOP_2_BACKEDGE]]
-; CHECK:       loop_2_backedge:
-; CHECK-NEXT:    [[J_NEXT]] = add i32 [[J]], 1
-; CHECK-NEXT:    [[C_2:%.*]] = icmp slt i32 [[J_NEXT]], [[N:%.*]]
-; CHECK-NEXT:    br i1 [[C_2]], label [[LOOP_2]], label [[LOOP_1_BACKEDGE]]
-; CHECK:       loop_1_backedge:
-; CHECK-NEXT:    [[I_NEXT]] = add i32 [[I]], 1
-; CHECK-NEXT:    [[C_1:%.*]] = icmp slt i32 [[I_NEXT]], [[N]]
-; CHECK-NEXT:    br i1 [[C_1]], label [[LOOP_1]], label [[EXIT:%.*]]
-; CHECK:       exit:
-; CHECK-NEXT:    [[I_LCSSA:%.*]] = phi i32 [ [[I]], [[LOOP_1_BACKEDGE]] ]
-; CHECK-NEXT:    ret i32 [[I_LCSSA]]
-;
-preheader:
-  br label %loop_1
-
-loop_1:
-  %i = phi i32 [ 0, %preheader ], [ %i.next, %loop_1_backedge ]
-  br label %loop_2
-
-loop_2:
-  %j = phi i32 [ 0, %loop_1 ], [ %j.next, %loop_2_backedge ]
-  br label %loop_3
-
-loop_3:
-  %k = phi i32 [ 0, %loop_2 ], [ %k.next, %loop_3_backedge ]
-  br i1 %cond1, label %loop_3_backedge, label %intermediate
-
-intermediate:
-  switch i32 1, label %loop_2_backedge [i32 0, label %loop_3_backedge]
-
-loop_3_backedge:
-  %k.next = add i32 %k, 1
-  br i1 %cond2, label %loop_3, label %loop_2_backedge
-
-loop_2_backedge:
-  %j.next = add i32 %j, 1
-  %c_2 = icmp slt i32 %j.next, %N
-  br i1 %c_2, label %loop_2, label %loop_1_backedge
-
-loop_1_backedge:
-  %i.next = add i32 %i, 1
-  %c_1 = icmp slt i32 %i.next, %N
-  br i1 %c_1, label %loop_1, label %exit
-
-exit:
-  ret i32 %i
-}
-
-define i32 @intermediate_subloop_branch_from_inner_to_grandparent(i1 %cond1, i1 %cond2, i1 %cond3, i32 %N) {
-; CHECK-LABEL: @intermediate_subloop_branch_from_inner_to_grandparent(
-; CHECK-NEXT:  preheader:
-; CHECK-NEXT:    br label [[LOOP_1:%.*]]
-; CHECK:       loop_1:
-; CHECK-NEXT:    [[I:%.*]] = phi i32 [ 0, [[PREHEADER:%.*]] ], [ [[I_NEXT:%.*]], [[LOOP_1_BACKEDGE:%.*]] ]
-; CHECK-NEXT:    br label [[LOOP_2:%.*]]
-; CHECK:       loop_2:
-; CHECK-NEXT:    [[J:%.*]] = phi i32 [ 0, [[LOOP_1]] ], [ [[J_NEXT:%.*]], [[LOOP_2_BACKEDGE:%.*]] ]
-; CHECK-NEXT:    br label [[LOOP_3:%.*]]
-; CHECK:       loop_3:
-; CHECK-NEXT:    [[K:%.*]] = phi i32 [ 0, [[LOOP_2]] ], [ [[K_NEXT:%.*]], [[LOOP_3_BACKEDGE:%.*]] ]
-; CHECK-NEXT:    br i1 [[COND1:%.*]], label [[LOOP_3_BACKEDGE]], label [[INTERMEDIATE:%.*]]
-; CHECK:       intermediate:
-; CHECK-NEXT:    br label [[INTERMEDIATE_LOOP:%.*]]
-; CHECK:       intermediate_loop:
-; CHECK-NEXT:    br i1 [[COND3:%.*]], label [[INTERMEDIATE_LOOP]], label [[INTERMEDIATE_EXIT:%.*]]
-; CHECK:       intermediate_exit:
-; CHECK-NEXT:    br i1 false, label [[LOOP_3_BACKEDGE]], label [[LOOP_1_BACKEDGE_LOOPEXIT:%.*]]
-; CHECK:       loop_3_backedge:
-; CHECK-NEXT:    [[K_NEXT]] = add i32 [[K]], 1
-; CHECK-NEXT:    br i1 [[COND2:%.*]], label [[LOOP_3]], label [[LOOP_2_BACKEDGE]]
-; CHECK:       loop_2_backedge:
-; CHECK-NEXT:    [[J_NEXT]] = add i32 [[J]], 1
-; CHECK-NEXT:    [[C_2:%.*]] = icmp slt i32 [[J_NEXT]], [[N:%.*]]
-; CHECK-NEXT:    br i1 [[C_2]], label [[LOOP_2]], label [[LOOP_1_BACKEDGE_LOOPEXIT1:%.*]]
-; CHECK:       loop_1_backedge.loopexit:
-; CHECK-NEXT:    br label [[LOOP_1_BACKEDGE]]
-; CHECK:       loop_1_backedge.loopexit1:
-; CHECK-NEXT:    br label [[LOOP_1_BACKEDGE]]
-; CHECK:       loop_1_backedge:
-; CHECK-NEXT:    [[I_NEXT]] = add i32 [[I]], 1
-; CHECK-NEXT:    [[C_1:%.*]] = icmp slt i32 [[I_NEXT]], [[N]]
-; CHECK-NEXT:    br i1 [[C_1]], label [[LOOP_1]], label [[EXIT:%.*]]
-; CHECK:       exit:
-; CHECK-NEXT:    [[I_LCSSA:%.*]] = phi i32 [ [[I]], [[LOOP_1_BACKEDGE]] ]
-; CHECK-NEXT:    ret i32 [[I_LCSSA]]
-;
-preheader:
-  br label %loop_1
-
-loop_1:
-  %i = phi i32 [ 0, %preheader ], [ %i.next, %loop_1_backedge ]
-  br label %loop_2
-
-loop_2:
-  %j = phi i32 [ 0, %loop_1 ], [ %j.next, %loop_2_backedge ]
-  br label %loop_3
-
-loop_3:
-  %k = phi i32 [ 0, %loop_2 ], [ %k.next, %loop_3_backedge ]
-  br i1 %cond1, label %loop_3_backedge, label %intermediate
-
-intermediate:
-  br label %intermediate_loop
-
-intermediate_loop:
-  br i1 %cond3, label %intermediate_loop, label %intermediate_exit
-
-intermediate_exit:
-  br i1 false, label %loop_3_backedge, label %loop_1_backedge
-
-loop_3_backedge:
-  %k.next = add i32 %k, 1
-  br i1 %cond2, label %loop_3, label %loop_2_backedge
-
-loop_2_backedge:
-  %j.next = add i32 %j, 1
-  %c_2 = icmp slt i32 %j.next, %N
-  br i1 %c_2, label %loop_2, label %loop_1_backedge
-
-loop_1_backedge:
-  %i.next = add i32 %i, 1
-  %c_1 = icmp slt i32 %i.next, %N
-  br i1 %c_1, label %loop_1, label %exit
-
-exit:
-  ret i32 %i
-}
-
-define i32 @intermediate_subloop_switch_from_inner_to_grandparent(i1 %cond1, i1 %cond2, i1 %cond3, i32 %N) {
-; CHECK-LABEL: @intermediate_subloop_switch_from_inner_to_grandparent(
-; CHECK-NEXT:  preheader:
-; CHECK-NEXT:    br label [[LOOP_1:%.*]]
-; CHECK:       loop_1:
-; CHECK-NEXT:    [[I:%.*]] = phi i32 [ 0, [[PREHEADER:%.*]] ], [ [[I_NEXT:%.*]], [[LOOP_1_BACKEDGE:%.*]] ]
-; CHECK-NEXT:    br label [[LOOP_2:%.*]]
-; CHECK:       loop_2:
-; CHECK-NEXT:    [[J:%.*]] = phi i32 [ 0, [[LOOP_1]] ], [ [[J_NEXT:%.*]], [[LOOP_2_BACKEDGE:%.*]] ]
-; CHECK-NEXT:    br label [[LOOP_3:%.*]]
-; CHECK:       loop_3:
-; CHECK-NEXT:    [[K:%.*]] = phi i32 [ 0, [[LOOP_2]] ], [ [[K_NEXT:%.*]], [[LOOP_3_BACKEDGE:%.*]] ]
-; CHECK-NEXT:    br i1 [[COND1:%.*]], label [[LOOP_3_BACKEDGE]], label [[INTERMEDIATE:%.*]]
-; CHECK:       intermediate:
-; CHECK-NEXT:    br label [[INTERMEDIATE_LOOP:%.*]]
-; CHECK:       intermediate_loop:
-; CHECK-NEXT:    br i1 [[COND3:%.*]], label [[INTERMEDIATE_LOOP]], label [[INTERMEDIATE_EXIT:%.*]]
-; CHECK:       intermediate_exit:
-; CHECK-NEXT:    switch i32 1, label [[LOOP_1_BACKEDGE_LOOPEXIT:%.*]] [
-; CHECK-NEXT:    i32 0, label [[LOOP_3_BACKEDGE]]
-; CHECK-NEXT:    ]
-; CHECK:       loop_3_backedge:
-; CHECK-NEXT:    [[K_NEXT]] = add i32 [[K]], 1
-; CHECK-NEXT:    br i1 [[COND2:%.*]], label [[LOOP_3]], label [[LOOP_2_BACKEDGE]]
-; CHECK:       loop_2_backedge:
-; CHECK-NEXT:    [[J_NEXT]] = add i32 [[J]], 1
-; CHECK-NEXT:    [[C_2:%.*]] = icmp slt i32 [[J_NEXT]], [[N:%.*]]
-; CHECK-NEXT:    br i1 [[C_2]], label [[LOOP_2]], label [[LOOP_1_BACKEDGE_LOOPEXIT1:%.*]]
-; CHECK:       loop_1_backedge.loopexit:
-; CHECK-NEXT:    br label [[LOOP_1_BACKEDGE]]
-; CHECK:       loop_1_backedge.loopexit1:
-; CHECK-NEXT:    br label [[LOOP_1_BACKEDGE]]
-; CHECK:       loop_1_backedge:
-; CHECK-NEXT:    [[I_NEXT]] = add i32 [[I]], 1
-; CHECK-NEXT:    [[C_1:%.*]] = icmp slt i32 [[I_NEXT]], [[N]]
-; CHECK-NEXT:    br i1 [[C_1]], label [[LOOP_1]], label [[EXIT:%.*]]
-; CHECK:       exit:
-; CHECK-NEXT:    [[I_LCSSA:%.*]] = phi i32 [ [[I]], [[LOOP_1_BACKEDGE]] ]
-; CHECK-NEXT:    ret i32 [[I_LCSSA]]
-;
-preheader:
-  br label %loop_1
-
-loop_1:
-  %i = phi i32 [ 0, %preheader ], [ %i.next, %loop_1_backedge ]
-  br label %loop_2
-
-loop_2:
-  %j = phi i32 [ 0, %loop_1 ], [ %j.next, %loop_2_backedge ]
-  br label %loop_3
-
-loop_3:
-  %k = phi i32 [ 0, %loop_2 ], [ %k.next, %loop_3_backedge ]
-  br i1 %cond1, label %loop_3_backedge, label %intermediate
-
-intermediate:
-  br label %intermediate_loop
-
-intermediate_loop:
-  br i1 %cond3, label %intermediate_loop, label %intermediate_exit
-
-intermediate_exit:
-  switch i32 1, label %loop_1_backedge [i32 0, label %loop_3_backedge]
-
-loop_3_backedge:
-  %k.next = add i32 %k, 1
-  br i1 %cond2, label %loop_3, label %loop_2_backedge
-
-loop_2_backedge:
-  %j.next = add i32 %j, 1
-  %c_2 = icmp slt i32 %j.next, %N
-  br i1 %c_2, label %loop_2, label %loop_1_backedge
-
-loop_1_backedge:
-  %i.next = add i32 %i, 1
-  %c_1 = icmp slt i32 %i.next, %N
-  br i1 %c_1, label %loop_1, label %exit
-
-exit:
-  ret i32 %i
-}
-
-define i32 @intermediate_subloop_branch_from_inner_to_parent(i1 %cond1, i1 %cond2, i1 %cond3, i32 %N) {
-; CHECK-LABEL: @intermediate_subloop_branch_from_inner_to_parent(
-; CHECK-NEXT:  preheader:
-; CHECK-NEXT:    br label [[LOOP_1:%.*]]
-; CHECK:       loop_1:
-; CHECK-NEXT:    [[I:%.*]] = phi i32 [ 0, [[PREHEADER:%.*]] ], [ [[I_NEXT:%.*]], [[LOOP_1_BACKEDGE:%.*]] ]
-; CHECK-NEXT:    br label [[LOOP_2:%.*]]
-; CHECK:       loop_2:
-; CHECK-NEXT:    [[J:%.*]] = phi i32 [ 0, [[LOOP_1]] ], [ [[J_NEXT:%.*]], [[LOOP_2_BACKEDGE:%.*]] ]
-; CHECK-NEXT:    br label [[LOOP_3:%.*]]
-; CHECK:       loop_3:
-; CHECK-NEXT:    [[K:%.*]] = phi i32 [ 0, [[LOOP_2]] ], [ [[K_NEXT:%.*]], [[LOOP_3_BACKEDGE:%.*]] ]
-; CHECK-NEXT:    br i1 [[COND1:%.*]], label [[LOOP_3_BACKEDGE]], label [[INTERMEDIATE:%.*]]
-; CHECK:       intermediate:
-; CHECK-NEXT:    br label [[INTERMEDIATE_LOOP:%.*]]
-; CHECK:       intermediate_loop:
-; CHECK-NEXT:    br i1 [[COND3:%.*]], label [[INTERMEDIATE_LOOP]], label [[INTERMEDIATE_EXIT:%.*]]
-; CHECK:       intermediate_exit:
-; CHECK-NEXT:    br i1 false, label [[LOOP_3_BACKEDGE]], label [[LOOP_2_BACKEDGE]]
-; CHECK:       loop_3_backedge:
-; CHECK-NEXT:    [[K_NEXT]] = add i32 [[K]], 1
-; CHECK-NEXT:    br i1 [[COND2:%.*]], label [[LOOP_3]], label [[LOOP_2_BACKEDGE]]
-; CHECK:       loop_2_backedge:
-; CHECK-NEXT:    [[J_NEXT]] = add i32 [[J]], 1
-; CHECK-NEXT:    [[C_2:%.*]] = icmp slt i32 [[J_NEXT]], [[N:%.*]]
-; CHECK-NEXT:    br i1 [[C_2]], label [[LOOP_2]], label [[LOOP_1_BACKEDGE]]
-; CHECK:       loop_1_backedge:
-; CHECK-NEXT:    [[I_NEXT]] = add i32 [[I]], 1
-; CHECK-NEXT:    [[C_1:%.*]] = icmp slt i32 [[I_NEXT]], [[N]]
-; CHECK-NEXT:    br i1 [[C_1]], label [[LOOP_1]], label [[EXIT:%.*]]
-; CHECK:       exit:
-; CHECK-NEXT:    [[I_LCSSA:%.*]] = phi i32 [ [[I]], [[LOOP_1_BACKEDGE]] ]
-; CHECK-NEXT:    ret i32 [[I_LCSSA]]
-;
-preheader:
-  br label %loop_1
-
-loop_1:
-  %i = phi i32 [ 0, %preheader ], [ %i.next, %loop_1_backedge ]
-  br label %loop_2
-
-loop_2:
-  %j = phi i32 [ 0, %loop_1 ], [ %j.next, %loop_2_backedge ]
-  br label %loop_3
-
-loop_3:
-  %k = phi i32 [ 0, %loop_2 ], [ %k.next, %loop_3_backedge ]
-  br i1 %cond1, label %loop_3_backedge, label %intermediate
-
-intermediate:
-  br label %intermediate_loop
-
-intermediate_loop:
-  br i1 %cond3, label %intermediate_loop, label %intermediate_exit
-
-intermediate_exit:
-  br i1 false, label %loop_3_backedge, label %loop_2_backedge
-
-loop_3_backedge:
-  %k.next = add i32 %k, 1
-  br i1 %cond2, label %loop_3, label %loop_2_backedge
-
-loop_2_backedge:
-  %j.next = add i32 %j, 1
-  %c_2 = icmp slt i32 %j.next, %N
-  br i1 %c_2, label %loop_2, label %loop_1_backedge
-
-loop_1_backedge:
-  %i.next = add i32 %i, 1
-  %c_1 = icmp slt i32 %i.next, %N
-  br i1 %c_1, label %loop_1, label %exit
-
-exit:
-  ret i32 %i
-}
-
-define i32 @intermediate_subloop_switch_from_inner_to_parent(i1 %cond1, i1 %cond2, i1 %cond3, i32 %N) {
-; CHECK-LABEL: @intermediate_subloop_switch_from_inner_to_parent(
-; CHECK-NEXT:  preheader:
-; CHECK-NEXT:    br label [[LOOP_1:%.*]]
-; CHECK:       loop_1:
-; CHECK-NEXT:    [[I:%.*]] = phi i32 [ 0, [[PREHEADER:%.*]] ], [ [[I_NEXT:%.*]], [[LOOP_1_BACKEDGE:%.*]] ]
-; CHECK-NEXT:    br label [[LOOP_2:%.*]]
-; CHECK:       loop_2:
-; CHECK-NEXT:    [[J:%.*]] = phi i32 [ 0, [[LOOP_1]] ], [ [[J_NEXT:%.*]], [[LOOP_2_BACKEDGE:%.*]] ]
-; CHECK-NEXT:    br label [[LOOP_3:%.*]]
-; CHECK:       loop_3:
-; CHECK-NEXT:    [[K:%.*]] = phi i32 [ 0, [[LOOP_2]] ], [ [[K_NEXT:%.*]], [[LOOP_3_BACKEDGE:%.*]] ]
-; CHECK-NEXT:    br i1 [[COND1:%.*]], label [[LOOP_3_BACKEDGE]], label [[INTERMEDIATE:%.*]]
-; CHECK:       intermediate:
-; CHECK-NEXT:    br label [[INTERMEDIATE_LOOP:%.*]]
-; CHECK:       intermediate_loop:
-; CHECK-NEXT:    br i1 [[COND3:%.*]], label [[INTERMEDIATE_LOOP]], label [[INTERMEDIATE_EXIT:%.*]]
-; CHECK:       intermediate_exit:
-; CHECK-NEXT:    switch i32 1, label [[LOOP_2_BACKEDGE]] [
-; CHECK-NEXT:    i32 0, label [[LOOP_3_BACKEDGE]]
-; CHECK-NEXT:    ]
-; CHECK:       loop_3_backedge:
-; CHECK-NEXT:    [[K_NEXT]] = add i32 [[K]], 1
-; CHECK-NEXT:    br i1 [[COND2:%.*]], label [[LOOP_3]], label [[LOOP_2_BACKEDGE]]
-; CHECK:       loop_2_backedge:
-; CHECK-NEXT:    [[J_NEXT]] = add i32 [[J]], 1
-; CHECK-NEXT:    [[C_2:%.*]] = icmp slt i32 [[J_NEXT]], [[N:%.*]]
-; CHECK-NEXT:    br i1 [[C_2]], label [[LOOP_2]], label [[LOOP_1_BACKEDGE]]
-; CHECK:       loop_1_backedge:
-; CHECK-NEXT:    [[I_NEXT]] = add i32 [[I]], 1
-; CHECK-NEXT:    [[C_1:%.*]] = icmp slt i32 [[I_NEXT]], [[N]]
-; CHECK-NEXT:    br i1 [[C_1]], label [[LOOP_1]], label [[EXIT:%.*]]
-; CHECK:       exit:
-; CHECK-NEXT:    [[I_LCSSA:%.*]] = phi i32 [ [[I]], [[LOOP_1_BACKEDGE]] ]
-; CHECK-NEXT:    ret i32 [[I_LCSSA]]
-;
-preheader:
-  br label %loop_1
-
-loop_1:
-  %i = phi i32 [ 0, %preheader ], [ %i.next, %loop_1_backedge ]
-  br label %loop_2
-
-loop_2:
-  %j = phi i32 [ 0, %loop_1 ], [ %j.next, %loop_2_backedge ]
-  br label %loop_3
-
-loop_3:
-  %k = phi i32 [ 0, %loop_2 ], [ %k.next, %loop_3_backedge ]
-  br i1 %cond1, label %loop_3_backedge, label %intermediate
-
-intermediate:
-  br label %intermediate_loop
-
-intermediate_loop:
-  br i1 %cond3, label %intermediate_loop, label %intermediate_exit
-
-intermediate_exit:
-  switch i32 1, label %loop_2_backedge [i32 0, label %loop_3_backedge]
-
-loop_3_backedge:
-  %k.next = add i32 %k, 1
-  br i1 %cond2, label %loop_3, label %loop_2_backedge
-
-loop_2_backedge:
-  %j.next = add i32 %j, 1
-  %c_2 = icmp slt i32 %j.next, %N
-  br i1 %c_2, label %loop_2, label %loop_1_backedge
-
-loop_1_backedge:
-  %i.next = add i32 %i, 1
-  %c_1 = icmp slt i32 %i.next, %N
-  br i1 %c_1, label %loop_1, label %exit
-
-exit:
-  ret i32 %i
-}
-
-define i32 @intermediate_complex_subloop_branch_from_inner_to_parent(i1 %cond1, i1 %cond2, i1 %cond3, i32 %N) {
-; CHECK-LABEL: @intermediate_complex_subloop_branch_from_inner_to_parent(
-; CHECK-NEXT:  preheader:
-; CHECK-NEXT:    br label [[LOOP_1:%.*]]
-; CHECK:       loop_1:
-; CHECK-NEXT:    [[I:%.*]] = phi i32 [ 0, [[PREHEADER:%.*]] ], [ [[I_NEXT:%.*]], [[LOOP_1_BACKEDGE:%.*]] ]
-; CHECK-NEXT:    br label [[LOOP_2:%.*]]
-; CHECK:       loop_2:
-; CHECK-NEXT:    [[J:%.*]] = phi i32 [ 0, [[LOOP_1]] ], [ [[J_NEXT:%.*]], [[LOOP_2_BACKEDGE:%.*]] ]
-; CHECK-NEXT:    br label [[LOOP_3:%.*]]
-; CHECK:       loop_3:
-; CHECK-NEXT:    [[K:%.*]] = phi i32 [ 0, [[LOOP_2]] ], [ [[K_NEXT:%.*]], [[LOOP_3_BACKEDGE:%.*]] ]
-; CHECK-NEXT:    br i1 [[COND1:%.*]], label [[LOOP_3_BACKEDGE]], label [[INTERMEDIATE:%.*]]
-; CHECK:       intermediate:
-; CHECK-NEXT:    br label [[INTERMEDIATE_LOOP:%.*]]
-; CHECK:       intermediate_loop:
-; CHECK-NEXT:    br i1 [[COND3:%.*]], label [[INTERMEDIATE_LOOP_BACKEDGE:%.*]], label [[INTERMEDIATE_BLOCK:%.*]]
-; CHECK:       intermediate_loop.backedge:
-; CHECK-NEXT:    br label [[INTERMEDIATE_LOOP]]
-; CHECK:       intermediate_block:
-; CHECK-NEXT:    br i1 [[COND2:%.*]], label [[INTERMEDIATE_LOOP_BACKEDGE]], label [[INTERMEDIATE_EXIT:%.*]]
-; CHECK:       intermediate_exit:
-; CHECK-NEXT:    br i1 false, label [[LOOP_3_BACKEDGE]], label [[LOOP_2_BACKEDGE]]
-; CHECK:       loop_3_backedge:
-; CHECK-NEXT:    [[K_NEXT]] = add i32 [[K]], 1
-; CHECK-NEXT:    br i1 [[COND2]], label [[LOOP_3]], label [[LOOP_2_BACKEDGE]]
-; CHECK:       loop_2_backedge:
-; CHECK-NEXT:    [[J_NEXT]] = add i32 [[J]], 1
-; CHECK-NEXT:    [[C_2:%.*]] = icmp slt i32 [[J_NEXT]], [[N:%.*]]
-; CHECK-NEXT:    br i1 [[C_2]], label [[LOOP_2]], label [[LOOP_1_BACKEDGE]]
-; CHECK:       loop_1_backedge:
-; CHECK-NEXT:    [[I_NEXT]] = add i32 [[I]], 1
-; CHECK-NEXT:    [[C_1:%.*]] = icmp slt i32 [[I_NEXT]], [[N]]
-; CHECK-NEXT:    br i1 [[C_1]], label [[LOOP_1]], label [[EXIT:%.*]]
-; CHECK:       exit:
-; CHECK-NEXT:    [[I_LCSSA:%.*]] = phi i32 [ [[I]], [[LOOP_1_BACKEDGE]] ]
-; CHECK-NEXT:    ret i32 [[I_LCSSA]]
-;
-preheader:
-  br label %loop_1
-
-loop_1:
-  %i = phi i32 [ 0, %preheader ], [ %i.next, %loop_1_backedge ]
-  br label %loop_2
-
-loop_2:
-  %j = phi i32 [ 0, %loop_1 ], [ %j.next, %loop_2_backedge ]
-  br label %loop_3
-
-loop_3:
-  %k = phi i32 [ 0, %loop_2 ], [ %k.next, %loop_3_backedge ]
-  br i1 %cond1, label %loop_3_backedge, label %intermediate
-
-intermediate:
-  br label %intermediate_loop
-
-intermediate_loop:
-  br i1 %cond3, label %intermediate_loop, label %intermediate_block
-
-intermediate_block:
-  br i1 %cond2, label %intermediate_loop, label %intermediate_exit
-
-intermediate_exit:
-  br i1 false, label %loop_3_backedge, label %loop_2_backedge
-
-loop_3_backedge:
-  %k.next = add i32 %k, 1
-  br i1 %cond2, label %loop_3, label %loop_2_backedge
-
-loop_2_backedge:
-  %j.next = add i32 %j, 1
-  %c_2 = icmp slt i32 %j.next, %N
-  br i1 %c_2, label %loop_2, label %loop_1_backedge
-
-loop_1_backedge:
-  %i.next = add i32 %i, 1
-  %c_1 = icmp slt i32 %i.next, %N
-  br i1 %c_1, label %loop_1, label %exit
-
-exit:
-  ret i32 %i
-}
-
-define i32 @intermediate_complex_subloop_switch_from_inner_to_parent(i1 %cond1, i1 %cond2, i1 %cond3, i32 %N) {
-; CHECK-LABEL: @intermediate_complex_subloop_switch_from_inner_to_parent(
-; CHECK-NEXT:  preheader:
-; CHECK-NEXT:    br label [[LOOP_1:%.*]]
-; CHECK:       loop_1:
-; CHECK-NEXT:    [[I:%.*]] = phi i32 [ 0, [[PREHEADER:%.*]] ], [ [[I_NEXT:%.*]], [[LOOP_1_BACKEDGE:%.*]] ]
-; CHECK-NEXT:    br label [[LOOP_2:%.*]]
-; CHECK:       loop_2:
-; CHECK-NEXT:    [[J:%.*]] = phi i32 [ 0, [[LOOP_1]] ], [ [[J_NEXT:%.*]], [[LOOP_2_BACKEDGE:%.*]] ]
-; CHECK-NEXT:    br label [[LOOP_3:%.*]]
-; CHECK:       loop_3:
-; CHECK-NEXT:    [[K:%.*]] = phi i32 [ 0, [[LOOP_2]] ], [ [[K_NEXT:%.*]], [[LOOP_3_BACKEDGE:%.*]] ]
-; CHECK-NEXT:    br i1 [[COND1:%.*]], label [[LOOP_3_BACKEDGE]], label [[INTERMEDIATE:%.*]]
-; CHECK:       intermediate:
-; CHECK-NEXT:    br label [[INTERMEDIATE_LOOP:%.*]]
-; CHECK:       intermediate_loop:
-; CHECK-NEXT:    br i1 [[COND3:%.*]], label [[INTERMEDIATE_LOOP_BACKEDGE:%.*]], label [[INTERMEDIATE_BLOCK:%.*]]
-; CHECK:       intermediate_loop.backedge:
-; CHECK-NEXT:    br label [[INTERMEDIATE_LOOP]]
-; CHECK:       intermediate_block:
-; CHECK-NEXT:    br i1 [[COND2:%.*]], label [[INTERMEDIATE_LOOP_BACKEDGE]], label [[INTERMEDIATE_EXIT:%.*]]
-; CHECK:       intermediate_exit:
-; CHECK-NEXT:    switch i32 1, label [[LOOP_2_BACKEDGE]] [
-; CHECK-NEXT:    i32 0, label [[LOOP_3_BACKEDGE]]
-; CHECK-NEXT:    ]
-; CHECK:       loop_3_backedge:
-; CHECK-NEXT:    [[K_NEXT]] = add i32 [[K]], 1
-; CHECK-NEXT:    br i1 [[COND2]], label [[LOOP_3]], label [[LOOP_2_BACKEDGE]]
-; CHECK:       loop_2_backedge:
-; CHECK-NEXT:    [[J_NEXT]] = add i32 [[J]], 1
-; CHECK-NEXT:    [[C_2:%.*]] = icmp slt i32 [[J_NEXT]], [[N:%.*]]
-; CHECK-NEXT:    br i1 [[C_2]], label [[LOOP_2]], label [[LOOP_1_BACKEDGE]]
-; CHECK:       loop_1_backedge:
-; CHECK-NEXT:    [[I_NEXT]] = add i32 [[I]], 1
-; CHECK-NEXT:    [[C_1:%.*]] = icmp slt i32 [[I_NEXT]], [[N]]
-; CHECK-NEXT:    br i1 [[C_1]], label [[LOOP_1]], label [[EXIT:%.*]]
-; CHECK:       exit:
-; CHECK-NEXT:    [[I_LCSSA:%.*]] = phi i32 [ [[I]], [[LOOP_1_BACKEDGE]] ]
-; CHECK-NEXT:    ret i32 [[I_LCSSA]]
-;
-preheader:
-  br label %loop_1
-
-loop_1:
-  %i = phi i32 [ 0, %preheader ], [ %i.next, %loop_1_backedge ]
-  br label %loop_2
-
-loop_2:
-  %j = phi i32 [ 0, %loop_1 ], [ %j.next, %loop_2_backedge ]
-  br label %loop_3
-
-loop_3:
-  %k = phi i32 [ 0, %loop_2 ], [ %k.next, %loop_3_backedge ]
-  br i1 %cond1, label %loop_3_backedge, label %intermediate
-
-intermediate:
-  br label %intermediate_loop
-
-intermediate_loop:
-  br i1 %cond3, label %intermediate_loop, label %intermediate_block
-
-intermediate_block:
-  br i1 %cond2, label %intermediate_loop, label %intermediate_exit
-
-intermediate_exit:
-  switch i32 1, label %loop_2_backedge [i32 0, label %loop_3_backedge]
-
-loop_3_backedge:
-  %k.next = add i32 %k, 1
-  br i1 %cond2, label %loop_3, label %loop_2_backedge
-
-loop_2_backedge:
-  %j.next = add i32 %j, 1
-  %c_2 = icmp slt i32 %j.next, %N
-  br i1 %c_2, label %loop_2, label %loop_1_backedge
-
-loop_1_backedge:
-  %i.next = add i32 %i, 1
-  %c_1 = icmp slt i32 %i.next, %N
-  br i1 %c_1, label %loop_1, label %exit
-
-exit:
-  ret i32 %i
-}
-
-
-define i32 @intermediate_complex_subloop_branch_from_inner_to_grandparent(i1 %cond1, i1 %cond2, i1 %cond3, i32 %N) {
-; CHECK-LABEL: @intermediate_complex_subloop_branch_from_inner_to_grandparent(
-; CHECK-NEXT:  preheader:
-; CHECK-NEXT:    br label [[LOOP_1:%.*]]
-; CHECK:       loop_1:
-; CHECK-NEXT:    [[I:%.*]] = phi i32 [ 0, [[PREHEADER:%.*]] ], [ [[I_NEXT:%.*]], [[LOOP_1_BACKEDGE:%.*]] ]
-; CHECK-NEXT:    br label [[LOOP_2:%.*]]
-; CHECK:       loop_2:
-; CHECK-NEXT:    [[J:%.*]] = phi i32 [ 0, [[LOOP_1]] ], [ [[J_NEXT:%.*]], [[LOOP_2_BACKEDGE:%.*]] ]
-; CHECK-NEXT:    br label [[LOOP_3:%.*]]
-; CHECK:       loop_3:
-; CHECK-NEXT:    [[K:%.*]] = phi i32 [ 0, [[LOOP_2]] ], [ [[K_NEXT:%.*]], [[LOOP_3_BACKEDGE:%.*]] ]
-; CHECK-NEXT:    br i1 [[COND1:%.*]], label [[LOOP_3_BACKEDGE]], label [[INTERMEDIATE:%.*]]
-; CHECK:       intermediate:
-; CHECK-NEXT:    br label [[INTERMEDIATE_LOOP:%.*]]
-; CHECK:       intermediate_loop:
-; CHECK-NEXT:    br i1 [[COND3:%.*]], label [[INTERMEDIATE_LOOP_BACKEDGE:%.*]], label [[INTERMEDIATE_BLOCK:%.*]]
-; CHECK:       intermediate_loop.backedge:
-; CHECK-NEXT:    br label [[INTERMEDIATE_LOOP]]
-; CHECK:       intermediate_block:
-; CHECK-NEXT:    br i1 [[COND2:%.*]], label [[INTERMEDIATE_LOOP_BACKEDGE]], label [[INTERMEDIATE_EXIT:%.*]]
-; CHECK:       intermediate_exit:
-; CHECK-NEXT:    br i1 false, label [[LOOP_3_BACKEDGE]], label [[LOOP_1_BACKEDGE_LOOPEXIT:%.*]]
-; CHECK:       loop_3_backedge:
-; CHECK-NEXT:    [[K_NEXT]] = add i32 [[K]], 1
-; CHECK-NEXT:    br i1 [[COND2]], label [[LOOP_3]], label [[LOOP_2_BACKEDGE]]
-; CHECK:       loop_2_backedge:
-; CHECK-NEXT:    [[J_NEXT]] = add i32 [[J]], 1
-; CHECK-NEXT:    [[C_2:%.*]] = icmp slt i32 [[J_NEXT]], [[N:%.*]]
-; CHECK-NEXT:    br i1 [[C_2]], label [[LOOP_2]], label [[LOOP_1_BACKEDGE_LOOPEXIT1:%.*]]
-; CHECK:       loop_1_backedge.loopexit:
-; CHECK-NEXT:    br label [[LOOP_1_BACKEDGE]]
-; CHECK:       loop_1_backedge.loopexit1:
-; CHECK-NEXT:    br label [[LOOP_1_BACKEDGE]]
-; CHECK:       loop_1_backedge:
-; CHECK-NEXT:    [[I_NEXT]] = add i32 [[I]], 1
-; CHECK-NEXT:    [[C_1:%.*]] = icmp slt i32 [[I_NEXT]], [[N]]
-; CHECK-NEXT:    br i1 [[C_1]], label [[LOOP_1]], label [[EXIT:%.*]]
-; CHECK:       exit:
-; CHECK-NEXT:    [[I_LCSSA:%.*]] = phi i32 [ [[I]], [[LOOP_1_BACKEDGE]] ]
-; CHECK-NEXT:    ret i32 [[I_LCSSA]]
-;
-preheader:
-  br label %loop_1
-
-loop_1:
-  %i = phi i32 [ 0, %preheader ], [ %i.next, %loop_1_backedge ]
-  br label %loop_2
-
-loop_2:
-  %j = phi i32 [ 0, %loop_1 ], [ %j.next, %loop_2_backedge ]
-  br label %loop_3
-
-loop_3:
-  %k = phi i32 [ 0, %loop_2 ], [ %k.next, %loop_3_backedge ]
-  br i1 %cond1, label %loop_3_backedge, label %intermediate
-
-intermediate:
-  br label %intermediate_loop
-
-intermediate_loop:
-  br i1 %cond3, label %intermediate_loop, label %intermediate_block
-
-intermediate_block:
-  br i1 %cond2, label %intermediate_loop, label %intermediate_exit
-
-intermediate_exit:
-  br i1 false, label %loop_3_backedge, label %loop_1_backedge
-
-loop_3_backedge:
-  %k.next = add i32 %k, 1
-  br i1 %cond2, label %loop_3, label %loop_2_backedge
-
-loop_2_backedge:
-  %j.next = add i32 %j, 1
-  %c_2 = icmp slt i32 %j.next, %N
-  br i1 %c_2, label %loop_2, label %loop_1_backedge
-
-loop_1_backedge:
-  %i.next = add i32 %i, 1
-  %c_1 = icmp slt i32 %i.next, %N
-  br i1 %c_1, label %loop_1, label %exit
-
-exit:
-  ret i32 %i
-}
-
-define i32 @intermediate_complex_subloop_switch_from_inner_to_grandparent(i1 %cond1, i1 %cond2, i1 %cond3, i32 %N) {
-; CHECK-LABEL: @intermediate_complex_subloop_switch_from_inner_to_grandparent(
-; CHECK-NEXT:  preheader:
-; CHECK-NEXT:    br label [[LOOP_1:%.*]]
-; CHECK:       loop_1:
-; CHECK-NEXT:    [[I:%.*]] = phi i32 [ 0, [[PREHEADER:%.*]] ], [ [[I_NEXT:%.*]], [[LOOP_1_BACKEDGE:%.*]] ]
-; CHECK-NEXT:    br label [[LOOP_2:%.*]]
-; CHECK:       loop_2:
-; CHECK-NEXT:    [[J:%.*]] = phi i32 [ 0, [[LOOP_1]] ], [ [[J_NEXT:%.*]], [[LOOP_2_BACKEDGE:%.*]] ]
-; CHECK-NEXT:    br label [[LOOP_3:%.*]]
-; CHECK:       loop_3:
-; CHECK-NEXT:    [[K:%.*]] = phi i32 [ 0, [[LOOP_2]] ], [ [[K_NEXT:%.*]], [[LOOP_3_BACKEDGE:%.*]] ]
-; CHECK-NEXT:    br i1 [[COND1:%.*]], label [[LOOP_3_BACKEDGE]], label [[INTERMEDIATE:%.*]]
-; CHECK:       intermediate:
-; CHECK-NEXT:    br label [[INTERMEDIATE_LOOP:%.*]]
-; CHECK:       intermediate_loop:
-; CHECK-NEXT:    br i1 [[COND3:%.*]], label [[INTERMEDIATE_LOOP_BACKEDGE:%.*]], label [[INTERMEDIATE_BLOCK:%.*]]
-; CHECK:       intermediate_loop.backedge:
-; CHECK-NEXT:    br label [[INTERMEDIATE_LOOP]]
-; CHECK:       intermediate_block:
-; CHECK-NEXT:    br i1 [[COND2:%.*]], label [[INTERMEDIATE_LOOP_BACKEDGE]], label [[INTERMEDIATE_EXIT:%.*]]
-; CHECK:       intermediate_exit:
-; CHECK-NEXT:    switch i32 1, label [[LOOP_1_BACKEDGE_LOOPEXIT:%.*]] [
-; CHECK-NEXT:    i32 0, label [[LOOP_3_BACKEDGE]]
-; CHECK-NEXT:    ]
-; CHECK:       loop_3_backedge:
-; CHECK-NEXT:    [[K_NEXT]] = add i32 [[K]], 1
-; CHECK-NEXT:    br i1 [[COND2]], label [[LOOP_3]], label [[LOOP_2_BACKEDGE]]
-; CHECK:       loop_2_backedge:
-; CHECK-NEXT:    [[J_NEXT]] = add i32 [[J]], 1
-; CHECK-NEXT:    [[C_2:%.*]] = icmp slt i32 [[J_NEXT]], [[N:%.*]]
-; CHECK-NEXT:    br i1 [[C_2]], label [[LOOP_2]], label [[LOOP_1_BACKEDGE_LOOPEXIT1:%.*]]
-; CHECK:       loop_1_backedge.loopexit:
-; CHECK-NEXT:    br label [[LOOP_1_BACKEDGE]]
-; CHECK:       loop_1_backedge.loopexit1:
-; CHECK-NEXT:    br label [[LOOP_1_BACKEDGE]]
-; CHECK:       loop_1_backedge:
-; CHECK-NEXT:    [[I_NEXT]] = add i32 [[I]], 1
-; CHECK-NEXT:    [[C_1:%.*]] = icmp slt i32 [[I_NEXT]], [[N]]
-; CHECK-NEXT:    br i1 [[C_1]], label [[LOOP_1]], label [[EXIT:%.*]]
-; CHECK:       exit:
-; CHECK-NEXT:    [[I_LCSSA:%.*]] = phi i32 [ [[I]], [[LOOP_1_BACKEDGE]] ]
-; CHECK-NEXT:    ret i32 [[I_LCSSA]]
-;
-preheader:
-  br label %loop_1
-
-loop_1:
-  %i = phi i32 [ 0, %preheader ], [ %i.next, %loop_1_backedge ]
-  br label %loop_2
-
-loop_2:
-  %j = phi i32 [ 0, %loop_1 ], [ %j.next, %loop_2_backedge ]
-  br label %loop_3
-
-loop_3:
-  %k = phi i32 [ 0, %loop_2 ], [ %k.next, %loop_3_backedge ]
-  br i1 %cond1, label %loop_3_backedge, label %intermediate
-
-intermediate:
-  br label %intermediate_loop
-
-intermediate_loop:
-  br i1 %cond3, label %intermediate_loop, label %intermediate_block
-
-intermediate_block:
-  br i1 %cond2, label %intermediate_loop, label %intermediate_exit
-
-intermediate_exit:
-  switch i32 1, label %loop_1_backedge [i32 0, label %loop_3_backedge]
-
-loop_3_backedge:
-  %k.next = add i32 %k, 1
-  br i1 %cond2, label %loop_3, label %loop_2_backedge
-
-loop_2_backedge:
-  %j.next = add i32 %j, 1
-  %c_2 = icmp slt i32 %j.next, %N
-  br i1 %c_2, label %loop_2, label %loop_1_backedge
-
-loop_1_backedge:
-  %i.next = add i32 %i, 1
-  %c_1 = icmp slt i32 %i.next, %N
-  br i1 %c_1, label %loop_1, label %exit
-
-exit:
-  ret i32 %i
-}
-
-define i32 @complex_dead_subloop_branch(i1 %cond1, i1 %cond2, i1 %cond3) {
-; CHECK-LABEL: @complex_dead_subloop_branch(
-; CHECK-NEXT:  entry:
-; CHECK-NEXT:    br label [[LOOP:%.*]]
-; CHECK:       loop:
-; CHECK-NEXT:    br i1 [[COND3:%.*]], label [[LOOP]], label [[EXIT:%.*]]
-; CHECK:       exit:
-; CHECK-NEXT:    [[RESULT_LCSSA:%.*]] = phi i32 [ 0, [[LOOP]] ]
-; CHECK-NEXT:    ret i32 [[RESULT_LCSSA]]
-;
-entry:
-  br label %loop
-
-loop:
-  br i1 true, label %latch, label %subloop
-
-subloop:
-  br i1 %cond1, label %x, label %y
-
-x:
-  br label %subloop_latch
-
-y:
-  br label %subloop_latch
-
-subloop_latch:
-  %dead_phi = phi i32 [ 1, %x ], [ 2, %y ]
-  br i1 %cond2, label %latch, label %subloop
-
-latch:
-  %result = phi i32 [ 0, %loop ], [ %dead_phi, %subloop_latch ]
-  br i1 %cond3, label %loop, label %exit
-
-exit:
-  ret i32 %result
-}
-
-define i32 @complex_dead_subloop_switch(i1 %cond1, i1 %cond2, i1 %cond3) {
-; CHECK-LABEL: @complex_dead_subloop_switch(
-; CHECK-NEXT:  entry:
-; CHECK-NEXT:    br label [[LOOP:%.*]]
-; CHECK:       loop:
-; CHECK-NEXT:    br i1 [[COND3:%.*]], label [[LOOP]], label [[EXIT:%.*]]
-; CHECK:       exit:
-; CHECK-NEXT:    [[RESULT_LCSSA:%.*]] = phi i32 [ 0, [[LOOP]] ]
-; CHECK-NEXT:    ret i32 [[RESULT_LCSSA]]
-;
-entry:
-  br label %loop
-
-loop:
-  switch i32 1, label %latch [ i32 0, label %subloop ]
-
-subloop:
-  br i1 %cond1, label %x, label %y
-
-x:
-  br label %subloop_latch
-
-y:
-  br label %subloop_latch
-
-subloop_latch:
-  %dead_phi = phi i32 [ 1, %x ], [ 2, %y ]
-  br i1 %cond2, label %latch, label %subloop
-
-latch:
-  %result = phi i32 [ 0, %loop ], [ %dead_phi, %subloop_latch ]
-  br i1 %cond3, label %loop, label %exit
-
-exit:
-  ret i32 %result
-}
-
-define void @test_crash_01() {
-; CHECK-LABEL: @test_crash_01(
-; CHECK-NEXT:  bb:
-; CHECK-NEXT:    br label [[BB1:%.*]]
-; CHECK:       bb1:
-; CHECK-NEXT:    br i1 undef, label [[BB17:%.*]], label [[BB2:%.*]]
-; CHECK:       bb2:
-; CHECK-NEXT:    switch i32 0, label [[BB2_SPLIT:%.*]] [
-; CHECK-NEXT:    i32 1, label [[BB19:%.*]]
-; CHECK-NEXT:    ]
-; CHECK:       bb2.split:
-; CHECK-NEXT:    br label [[BB3:%.*]]
-; CHECK:       bb3:
-; CHECK-NEXT:    switch i32 undef, label [[BB16:%.*]] [
-; CHECK-NEXT:    i32 0, label [[BB15:%.*]]
-; CHECK-NEXT:    i32 1, label [[BB14:%.*]]
-; CHECK-NEXT:    i32 2, label [[BB13:%.*]]
-; CHECK-NEXT:    i32 3, label [[BB12:%.*]]
-; CHECK-NEXT:    i32 4, label [[BB11:%.*]]
-; CHECK-NEXT:    i32 5, label [[BB8:%.*]]
-; CHECK-NEXT:    i32 6, label [[BB10:%.*]]
-; CHECK-NEXT:    i32 7, label [[BB9:%.*]]
-; CHECK-NEXT:    i32 8, label [[BB7:%.*]]
-; CHECK-NEXT:    ]
-; CHECK:       bb7:
-; CHECK-NEXT:    unreachable
-; CHECK:       bb8:
-; CHECK-NEXT:    switch i32 undef, label [[BB28:%.*]] [
-; CHECK-NEXT:    i32 0, label [[BB27:%.*]]
-; CHECK-NEXT:    i32 1, label [[BB26:%.*]]
-; CHECK-NEXT:    i32 2, label [[BB23:%.*]]
-; CHECK-NEXT:    i32 3, label [[BB24:%.*]]
-; CHECK-NEXT:    i32 4, label [[BB25:%.*]]
-; CHECK-NEXT:    i32 5, label [[BB29:%.*]]
-; CHECK-NEXT:    i32 6, label [[BB22:%.*]]
-; CHECK-NEXT:    i32 7, label [[BB20:%.*]]
-; CHECK-NEXT:    i32 8, label [[BB21:%.*]]
-; CHECK-NEXT:    ]
-; CHECK:       bb9:
-; CHECK-NEXT:    unreachable
-; CHECK:       bb10:
-; CHECK-NEXT:    unreachable
-; CHECK:       bb11:
-; CHECK-NEXT:    br label [[BB8]]
-; CHECK:       bb12:
-; CHECK-NEXT:    unreachable
-; CHECK:       bb13:
-; CHECK-NEXT:    unreachable
-; CHECK:       bb14:
-; CHECK-NEXT:    unreachable
-; CHECK:       bb15:
-; CHECK-NEXT:    unreachable
-; CHECK:       bb16:
-; CHECK-NEXT:    unreachable
-; CHECK:       bb17:
-; CHECK-NEXT:    ret void
-; CHECK:       bb19:
-; CHECK-NEXT:    ret void
-; CHECK:       bb20:
-; CHECK-NEXT:    unreachable
-; CHECK:       bb21:
-; CHECK-NEXT:    unreachable
-; CHECK:       bb22:
-; CHECK-NEXT:    unreachable
-; CHECK:       bb23:
-; CHECK-NEXT:    unreachable
-; CHECK:       bb24:
-; CHECK-NEXT:    unreachable
-; CHECK:       bb25:
-; CHECK-NEXT:    unreachable
-; CHECK:       bb26:
-; CHECK-NEXT:    unreachable
-; CHECK:       bb27:
-; CHECK-NEXT:    unreachable
-; CHECK:       bb28:
-; CHECK-NEXT:    unreachable
-; CHECK:       bb29:
-; CHECK-NEXT:    br label [[BB3]]
-;
-bb:
-  br label %bb1
-
-bb1:                                              ; preds = %bb
-  br i1 undef, label %bb17, label %bb2
-
-bb2:                                              ; preds = %bb1
-  br label %bb3
-
-bb3:                                              ; preds = %bb6, %bb2
-  br label %bb4
-
-bb4:                                              ; preds = %bb3
-  switch i32 0, label %bb5 [
-  i32 1, label %bb19
-  i32 2, label %bb18
-  ]
-
-bb5:                                              ; preds = %bb4
-  switch i32 undef, label %bb16 [
-  i32 0, label %bb15
-  i32 1, label %bb14
-  i32 2, label %bb13
-  i32 3, label %bb12
-  i32 4, label %bb11
-  i32 5, label %bb8
-  i32 6, label %bb10
-  i32 7, label %bb9
-  i32 8, label %bb7
-  ]
-
-bb6:                                              ; preds = %bb29, %bb18
-  br label %bb3
-
-bb7:                                              ; preds = %bb5
-  unreachable
-
-bb8:                                              ; preds = %bb11, %bb5
-  switch i32 undef, label %bb28 [
-  i32 0, label %bb27
-  i32 1, label %bb26
-  i32 2, label %bb23
-  i32 3, label %bb24
-  i32 4, label %bb25
-  i32 5, label %bb29
-  i32 6, label %bb22
-  i32 7, label %bb20
-  i32 8, label %bb21
-  ]
-
-bb9:                                              ; preds = %bb5
-  unreachable
-
-bb10:                                             ; preds = %bb5
-  unreachable
-
-bb11:                                             ; preds = %bb5
-  br label %bb8
-
-bb12:                                             ; preds = %bb5
-  unreachable
-
-bb13:                                             ; preds = %bb5
-  unreachable
-
-bb14:                                             ; preds = %bb5
-  unreachable
-
-bb15:                                             ; preds = %bb5
-  unreachable
-
-bb16:                                             ; preds = %bb5
-  unreachable
-
-bb17:                                             ; preds = %bb1
-  ret void
-
-bb18:                                             ; preds = %bb4
-  br label %bb6
-
-bb19:                                             ; preds = %bb4
-  ret void
-
-bb20:                                             ; preds = %bb8
-  unreachable
-
-bb21:                                             ; preds = %bb8
-  unreachable
-
-bb22:                                             ; preds = %bb8
-  unreachable
-
-bb23:                                             ; preds = %bb8
-  unreachable
-
-bb24:                                             ; preds = %bb8
-  unreachable
-
-bb25:                                             ; preds = %bb8
-  unreachable
-
-bb26:                                             ; preds = %bb8
-  unreachable
-
-bb27:                                             ; preds = %bb8
-  unreachable
-
-bb28:                                             ; preds = %bb8
-  unreachable
-
-bb29:                                             ; preds = %bb8
-  br label %bb6
-}
diff --git a/llvm/test/Transforms/LoopSimplifyCFG/irreducible_cfg.ll b/llvm/test/Transforms/LoopSimplifyCFG/irreducible_cfg.ll
deleted file mode 100644
index e7c8afc389d..00000000000
--- a/llvm/test/Transforms/LoopSimplifyCFG/irreducible_cfg.ll
+++ /dev/null
@@ -1,51 +0,0 @@
-; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; REQUIRES: asserts
-; RUN: opt -S -enable-loop-simplifycfg-term-folding=true -loop-simplifycfg -debug-only=loop-simplifycfg -verify-loop-info -verify-dom-info -verify-loop-lcssa 2>&1 < %s | FileCheck %s
-; RUN: opt -S -enable-loop-simplifycfg-term-folding=true -passes='require<domtree>,loop(simplify-cfg)' -debug-only=loop-simplifycfg -verify-loop-info -verify-dom-info -verify-loop-lcssa 2>&1 < %s | FileCheck %s
-; RUN: opt -S -enable-loop-simplifycfg-term-folding=true -loop-simplifycfg -enable-mssa-loop-dependency=true -verify-memoryssa -debug-only=loop-simplifycfg -verify-loop-info -verify-dom-info -verify-loop-lcssa 2>&1 < %s | FileCheck %s
-
-target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128-ni:1"
-
-; This test has irreducible CFG, and RPO may be the following:
-; Header, Dead, Irreducible2, Latch, Irreducible3, Irreducible1.
-; As result, we will process Irreducible2 before its predecessor Irreducible1.
-; The current algorithm gets confused in this case. We may support irreducible
-; CFG in the future.
-define void @irreducible_cfg(i1 %cond) {
-; CHECK-LABEL: @irreducible_cfg(
-; CHECK-NEXT:  entry:
-; CHECK-NEXT:    br label [[HEADER:%.*]]
-; CHECK:       header:
-; CHECK-NEXT:    br i1 false, label [[DEAD:%.*]], label [[IRREDUCIBLE1:%.*]]
-; CHECK:       dead:
-; CHECK-NEXT:    br label [[IRREDUCIBLE2:%.*]]
-; CHECK:       irreducible2:
-; CHECK-NEXT:    br i1 [[COND:%.*]], label [[LATCH:%.*]], label [[IRREDUCIBLE3:%.*]]
-; CHECK:       latch:
-; CHECK-NEXT:    br label [[HEADER]]
-; CHECK:       irreducible3:
-; CHECK-NEXT:    br label [[IRREDUCIBLE1]]
-; CHECK:       irreducible1:
-; CHECK-NEXT:    br label [[IRREDUCIBLE2]]
-;
-entry:
-  br label %header
-
-header:                                             ; preds = %latch, %entry
-  br i1 false, label %dead, label %irreducible1
-
-dead:                                          ; preds = %header
-  br label %irreducible2
-
-irreducible2:                                             ; preds = %irreducible1, %dead
-  br i1 %cond, label %latch, label %irreducible3
-
-latch:                                         ; preds = %irreducible2
-  br label %header
-
-irreducible3:                                           ; preds = %irreducible2
-  br label %irreducible1
-
-irreducible1:                                          ; preds = %irreducible3, %header
-  br label %irreducible2
-}
diff --git a/llvm/test/Transforms/LoopSimplifyCFG/lcssa.ll b/llvm/test/Transforms/LoopSimplifyCFG/lcssa.ll
deleted file mode 100644
index 4673628181e..00000000000
--- a/llvm/test/Transforms/LoopSimplifyCFG/lcssa.ll
+++ /dev/null
@@ -1,194 +0,0 @@
-; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; RUN: opt -S -enable-loop-simplifycfg-term-folding=true -loop-simplifycfg -verify-loop-info -verify-dom-info -verify-loop-lcssa < %s | FileCheck %s
-; RUN: opt -S -enable-loop-simplifycfg-term-folding=true -passes='require<domtree>,loop(simplify-cfg)' -verify-loop-info -verify-dom-info -verify-loop-lcssa < %s | FileCheck %s
-; RUN: opt -S -enable-loop-simplifycfg-term-folding=true -loop-simplifycfg -enable-mssa-loop-dependency=true -verify-memoryssa -verify-loop-info -verify-dom-info -verify-loop-lcssa < %s | FileCheck %s
-
-target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
-
-define void @c() {
-; CHECK-LABEL: @c(
-; CHECK-NEXT:  entry:
-; CHECK-NEXT:    br label [[D:%.*]]
-; CHECK:       d.loopexit:
-; CHECK-NEXT:    [[DOTLCSSA:%.*]] = phi i32 [ [[TMP1:%.*]], [[FOR_COND:%.*]] ]
-; CHECK-NEXT:    br label [[D]]
-; CHECK:       d:
-; CHECK-NEXT:    [[TMP0:%.*]] = phi i32 [ undef, [[ENTRY:%.*]] ], [ [[DOTLCSSA]], [[D_LOOPEXIT:%.*]] ]
-; CHECK-NEXT:    br label [[FOR_COND]]
-; CHECK:       for.cond:
-; CHECK-NEXT:    [[TMP1]] = phi i32 [ [[TMP0]], [[D]] ], [ 0, [[IF_END:%.*]] ]
-; CHECK-NEXT:    [[TOBOOL2:%.*]] = icmp eq i32 [[TMP1]], 0
-; CHECK-NEXT:    br i1 [[TOBOOL2]], label [[IF_END]], label [[D_LOOPEXIT]]
-; CHECK:       if.end:
-; CHECK-NEXT:    br label [[FOR_COND]]
-;
-entry:
-  br label %d
-
-d.loopexit:                                       ; preds = %if.end.7, %for.body
-  %.lcssa = phi i32 [ %1, %for.body ], [ 0, %if.end.7 ]
-  br label %d
-
-d:                                                ; preds = %d.loopexit, %entry
-  %0 = phi i32 [ undef, %entry ], [ %.lcssa, %d.loopexit ]
-  br label %for.cond
-
-for.cond:                                         ; preds = %if.end.8, %d
-  %1 = phi i32 [ %0, %d ], [ 0, %if.end.8 ]
-  br label %for.body
-
-for.body:                                         ; preds = %for.cond
-  %tobool2 = icmp eq i32 %1, 0
-  br i1 %tobool2, label %if.end, label %d.loopexit
-
-if.end:                                           ; preds = %for.body
-  br label %if.end.7
-
-if.end.7:                                         ; preds = %if.end
-  br i1 true, label %if.end.8, label %d.loopexit
-
-if.end.8:                                         ; preds = %if.end.7
-  br label %for.cond
-}
-
-define void @test_01() {
-; CHECK-LABEL: @test_01(
-; CHECK-NEXT:  entry:
-; CHECK-NEXT:    br label [[FOR_COND:%.*]]
-; CHECK:       for.cond.loopexit:
-; CHECK-NEXT:    br label [[FOR_COND]]
-; CHECK:       for.cond:
-; CHECK-NEXT:    [[INC41_LCSSA3:%.*]] = phi i16 [ undef, [[FOR_COND_LOOPEXIT:%.*]] ], [ undef, [[ENTRY:%.*]] ]
-; CHECK-NEXT:    switch i32 0, label [[FOR_COND_SPLIT:%.*]] [
-; CHECK-NEXT:    i32 1, label [[FOR_COND_LOOPEXIT]]
-; CHECK-NEXT:    ]
-; CHECK:       for.cond.split:
-; CHECK-NEXT:    [[INC41_LCSSA3_LCSSA:%.*]] = phi i16 [ [[INC41_LCSSA3]], [[FOR_COND]] ]
-; CHECK-NEXT:    br label [[WHILE_COND:%.*]]
-; CHECK:       while.cond:
-; CHECK-NEXT:    [[INC41:%.*]] = phi i16 [ [[INC4:%.*]], [[WHILE_COND]] ], [ [[INC41_LCSSA3_LCSSA]], [[FOR_COND_SPLIT]] ]
-; CHECK-NEXT:    [[INC4]] = add nsw i16 [[INC41]], 1
-; CHECK-NEXT:    br label [[WHILE_COND]]
-;
-entry:
-  br label %for.cond
-
-for.cond.loopexit:                                ; preds = %while.cond
-  %inc41.lcssa = phi i16 [ %inc41, %while.cond ]
-  br label %for.cond
-
-for.cond:                                         ; preds = %for.cond.loopexit, %entry
-  %inc41.lcssa3 = phi i16 [ %inc41.lcssa, %for.cond.loopexit ], [ undef, %entry ]
-  br label %while.cond
-
-while.cond:                                       ; preds = %while.body, %for.cond
-  %inc41 = phi i16 [ %inc4, %while.body ], [ %inc41.lcssa3, %for.cond ]
-  br i1 true, label %while.body, label %for.cond.loopexit
-
-while.body:                                       ; preds = %while.cond
-  %inc4 = add nsw i16 %inc41, 1
-  br label %while.cond
-}
-
-define void @bar() {
-; CHECK-LABEL: @bar(
-; CHECK-NEXT:  bb:
-; CHECK-NEXT:    switch i32 0, label [[BB_SPLIT:%.*]] [
-; CHECK-NEXT:    i32 1, label [[BB10:%.*]]
-; CHECK-NEXT:    ]
-; CHECK:       bb.split:
-; CHECK-NEXT:    br label [[BB1:%.*]]
-; CHECK:       bb1:
-; CHECK-NEXT:    [[TMP:%.*]] = phi i32 [ [[TMP7:%.*]], [[BB6:%.*]] ], [ undef, [[BB_SPLIT]] ]
-; CHECK-NEXT:    switch i32 undef, label [[BB5:%.*]] [
-; CHECK-NEXT:    i32 0, label [[BB6]]
-; CHECK-NEXT:    i32 1, label [[BB8:%.*]]
-; CHECK-NEXT:    ]
-; CHECK:       bb5:
-; CHECK-NEXT:    ret void
-; CHECK:       bb6:
-; CHECK-NEXT:    [[TMP7]] = add i32 undef, 123
-; CHECK-NEXT:    br label [[BB1]]
-; CHECK:       bb8:
-; CHECK-NEXT:    [[TMP9:%.*]] = phi i32 [ [[TMP]], [[BB1]] ]
-; CHECK-NEXT:    [[USE:%.*]] = add i32 [[TMP9]], 1
-; CHECK-NEXT:    ret void
-; CHECK:       bb10:
-; CHECK-NEXT:    ret void
-;
-
-bb:
-  br label %bb1
-
-bb1:                                              ; preds = %bb6, %bb
-  %tmp = phi i32 [ %tmp7, %bb6 ], [ undef, %bb ]
-  br i1 false, label %bb2, label %bb4
-
-bb2:                                              ; preds = %bb1
-  switch i32 undef, label %bb10 [
-  i32 0, label %bb3
-  i32 1, label %bb8
-  ]
-
-bb3:                                              ; preds = %bb2
-  br label %bb6
-
-bb4:                                              ; preds = %bb1
-  switch i32 undef, label %bb5 [
-  i32 0, label %bb6
-  i32 1, label %bb8
-  ]
-
-bb5:                                              ; preds = %bb4
-  ret void
-
-bb6:                                              ; preds = %bb4, %bb3
-  %tmp7 = add i32 undef, 123
-  br label %bb1
-
-bb8:                                              ; preds = %bb4, %bb2
-  %tmp9 = phi i32 [ %tmp, %bb2 ], [ %tmp, %bb4 ]
-  %use = add i32 %tmp9, 1
-  ret void
-
-bb10:                                             ; preds = %bb2
-  ret void
-}
-
-define void @memlcssa() {
-; CHECK-LABEL: @memlcssa(
-; CHECK-NEXT:  entry:
-; CHECK-NEXT:    switch i32 0, label [[ENTRY_SPLIT:%.*]] [
-; CHECK-NEXT:    i32 1, label [[DEFAULT_BB:%.*]]
-; CHECK-NEXT:    ]
-; CHECK:       entry.split:
-; CHECK-NEXT:    br label [[FOR_BODY:%.*]]
-; CHECK:       for.body:
-; CHECK-NEXT:    call void @foo()
-; CHECK-NEXT:    br label [[FOR_BODY]]
-; CHECK:       default.bb:
-; CHECK-NEXT:    unreachable
-;
-entry:
-  br label %for.body
-
-for.body:                                         ; preds = %exit, %entry
-  br label %switch.bb
-
-switch.bb:                                        ; preds = %for.body
-  switch i2 1, label %default.bb [
-  i2 1, label %case.bb
-  ]
-
-case.bb:                                          ; preds = %switch
-  br label %exit
-
-default.bb:                                       ; preds = %switch
-  unreachable
-
-exit:                                             ; preds = %case.bb
-  call void @foo()
-  br label %for.body
-}
-
-declare void @foo()
diff --git a/llvm/test/Transforms/LoopSimplifyCFG/live_block_marking.ll b/llvm/test/Transforms/LoopSimplifyCFG/live_block_marking.ll
deleted file mode 100644
index 853afb2b28a..00000000000
--- a/llvm/test/Transforms/LoopSimplifyCFG/live_block_marking.ll
+++ /dev/null
@@ -1,62 +0,0 @@
-; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; REQUIRES: asserts
-; RUN: opt -S -enable-loop-simplifycfg-term-folding=true -indvars -loop-simplifycfg -verify-loop-info -verify-dom-info -verify-loop-lcssa 2>&1 < %s | FileCheck %s
-; RUN: opt -S -enable-loop-simplifycfg-term-folding=true -passes='require<domtree>,loop(indvars,simplify-cfg)' -verify-loop-info -verify-dom-info -verify-loop-lcssa 2>&1 < %s | FileCheck %s
-; RUN: opt -S -enable-loop-simplifycfg-term-folding=true -indvars -loop-simplifycfg -enable-mssa-loop-dependency=true -verify-memoryssa -verify-loop-info -verify-dom-info -verify-loop-lcssa 2>&1 < %s | FileCheck %s
-
-define void @test(i1 %c) {
-; CHECK-LABEL: @test(
-; CHECK-NEXT:  entry:
-; CHECK-NEXT:    switch i32 0, label [[ENTRY_SPLIT:%.*]] [
-; CHECK-NEXT:    i32 1, label [[DEAD_EXIT:%.*]]
-; CHECK-NEXT:    ]
-; CHECK:       entry.split:
-; CHECK-NEXT:    br label [[OUTER:%.*]]
-; CHECK:       outer:
-; CHECK-NEXT:    br i1 [[C:%.*]], label [[TO_FOLD:%.*]], label [[LATCH:%.*]]
-; CHECK:       to_fold:
-; CHECK-NEXT:    br i1 [[C]], label [[LATCH]], label [[INNER_PREHEADER:%.*]]
-; CHECK:       inner.preheader:
-; CHECK-NEXT:    br label [[INNER:%.*]]
-; CHECK:       inner:
-; CHECK-NEXT:    br i1 false, label [[INNER_LATCH:%.*]], label [[UNDEAD:%.*]]
-; CHECK:       inner_latch:
-; CHECK-NEXT:    br i1 true, label [[INNER]], label [[LATCH_LOOPEXIT:%.*]]
-; CHECK:       undead:
-; CHECK-NEXT:    br label [[LATCH]]
-; CHECK:       latch.loopexit:
-; CHECK-NEXT:    br label [[LATCH]]
-; CHECK:       latch:
-; CHECK-NEXT:    br label [[OUTER]]
-; CHECK:       dead_exit:
-; CHECK-NEXT:    ret void
-;
-
-entry:
-  br label %outer
-
-outer:
-  br i1 %c, label %to_fold, label %latch
-
-to_fold:
-  br i1 %c, label %latch, label %inner
-
-inner:
-  %iv = phi i32 [0, %to_fold], [%iv.next, %inner_latch]
-  %never = icmp sgt i32 %iv, 40
-  br i1 %never, label %inner_latch, label %undead
-
-inner_latch:
-  %iv.next = add i32 %iv, 1
-  %cmp = icmp slt i32 %iv.next, 10
-  br i1 %cmp, label %inner, label %latch
-
-undead:
-  br label %latch
-
-latch:
-  br i1 true, label %outer, label %dead_exit
-
-dead_exit:
-  ret void
-}
diff --git a/llvm/test/Transforms/LoopSimplifyCFG/merge-header.ll b/llvm/test/Transforms/LoopSimplifyCFG/merge-header.ll
deleted file mode 100644
index 91bc44baef9..00000000000
--- a/llvm/test/Transforms/LoopSimplifyCFG/merge-header.ll
+++ /dev/null
@@ -1,36 +0,0 @@
-; RUN: opt -S -loop-simplifycfg < %s | FileCheck %s
-; RUN: opt -S -passes='require<domtree>,loop(simplify-cfg)' < %s | FileCheck %s
-; RUN: opt -S -loop-simplifycfg -enable-mssa-loop-dependency=true -verify-memoryssa < %s | FileCheck %s
-
-; CHECK-LABEL: foo
-; CHECK:      entry:
-; CHECK-NEXT:   br label %[[LOOP:[a-z]+]]
-; CHECK:      [[LOOP]]:
-; CHECK-NEXT:   phi
-; CHECK-NOT:    br label
-; CHECK:        br i1
-define i32 @foo(i32* %P, i64* %Q) {
-entry:
-  br label %outer
-
-outer:                                            ; preds = %outer.latch2, %entry
-  %y.2 = phi i32 [ 0, %entry ], [ %y.inc2, %outer.latch2 ]
-  br label %inner
-
-inner:                                            ; preds = %outer
-  store i32 0, i32* %P
-  store i32 1, i32* %P
-  store i32 2, i32* %P
-  %y.inc2 = add nsw i32 %y.2, 1
-  %exitcond.outer = icmp eq i32 %y.inc2, 3
-  store i32 %y.2, i32* %P
-  br i1 %exitcond.outer, label %exit, label %outer.latch2
-
-outer.latch2:                                     ; preds = %inner
-  %t = sext i32 %y.inc2 to i64
-  store i64 %t, i64* %Q
-  br label %outer
-
-exit:                                             ; preds = %inner
-  ret i32 0
-}
diff --git a/llvm/test/Transforms/LoopSimplifyCFG/mssa_update.ll b/llvm/test/Transforms/LoopSimplifyCFG/mssa_update.ll
deleted file mode 100644
index 73625c5e220..00000000000
--- a/llvm/test/Transforms/LoopSimplifyCFG/mssa_update.ll
+++ /dev/null
@@ -1,40 +0,0 @@
-; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; REQUIRES: asserts
-; RUN: opt -S -enable-loop-simplifycfg-term-folding=true -loop-simplifycfg -verify-loop-info -verify-dom-info -verify-loop-lcssa < %s | FileCheck %s
-; RUN: opt -S -enable-loop-simplifycfg-term-folding=true -passes='require<domtree>,loop(simplify-cfg)' -verify-loop-info -verify-dom-info -verify-loop-lcssa < %s | FileCheck %s
-; RUN: opt -S -enable-loop-simplifycfg-term-folding=true -loop-simplifycfg -enable-mssa-loop-dependency=true -verify-memoryssa -verify-loop-info -verify-dom-info -verify-loop-lcssa < %s | FileCheck %s
-
-target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
-
-; Make sure we update MSSA properly.
-define void @test(i32* %a, i32* %b) {
-; CHECK-LABEL: @test(
-
-entry:
-  br label %for.body
-
-for.body:
-  %i = phi i32 [ 0, %entry ], [ %i.inc, %latch ]
-  br label %switch.bb
-
-switch.bb:
-  switch i2 1, label %default [
-    i2 1, label %case
-  ]
-
-case:
-  br label %latch
-
-default:
-  unreachable
-
-latch:
-  store i32 %i, i32* %a
-  store i32 %i, i32* %b
-  %i.inc = add nsw i32 %i, 1
-  %exitcond = icmp eq i32 %i.inc, 4
-  br i1 %exitcond, label %exit, label %for.body
-
-exit:
-  ret void
-}
diff --git a/llvm/test/Transforms/LoopSimplifyCFG/phi_with_duplicating_inputs.ll b/llvm/test/Transforms/LoopSimplifyCFG/phi_with_duplicating_inputs.ll
deleted file mode 100644
index fc1f5578f10..00000000000
--- a/llvm/test/Transforms/LoopSimplifyCFG/phi_with_duplicating_inputs.ll
+++ /dev/null
@@ -1,41 +0,0 @@
-; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; This is currently failing because of bug in LoopSimplifyCFG. It does not update
-; duplicating Phi inputs properly.
-; REQUIRES: asserts
-; RUN: opt -S -enable-loop-simplifycfg-term-folding=true -loop-simplifycfg -debug-only=loop-simplifycfg -verify-loop-info -verify-dom-info -verify-loop-lcssa 2>&1 < %s | FileCheck %s
-; RUN: opt -S -enable-loop-simplifycfg-term-folding=true -passes='require<domtree>,loop(simplify-cfg)' -debug-only=loop-simplifycfg -verify-loop-info -verify-dom-info -verify-loop-lcssa 2>&1 < %s | FileCheck %s
-; RUN: opt -S -enable-loop-simplifycfg-term-folding=true -loop-simplifycfg -enable-mssa-loop-dependency=true -verify-memoryssa -debug-only=loop-simplifycfg -verify-loop-info -verify-dom-info -verify-loop-lcssa 2>&1 < %s | FileCheck %s
-
-target datalayout = "P40"
-
-@a = external global i16, align 1
-
-define void @f1(i1 %cond) {
-; CHECK-LABEL: @f1(
-; CHECK-NEXT:  entry:
-; CHECK-NEXT:    br label [[FOR_COND:%.*]]
-; CHECK:       for.cond:
-; CHECK-NEXT:    br i1 [[COND:%.*]], label [[IF_THEN:%.*]], label [[FOR_INC:%.*]]
-; CHECK:       if.then:
-; CHECK-NEXT:    [[TMP0:%.*]] = load i16, i16* @a, align 1
-; CHECK-NEXT:    [[TOBOOL:%.*]] = icmp ne i16 [[TMP0]], 0
-; CHECK-NEXT:    br label [[FOR_INC]]
-; CHECK:       for.inc:
-; CHECK-NEXT:    [[C_1:%.*]] = phi i16 [ 2, [[IF_THEN]] ], [ 1, [[FOR_COND]] ]
-; CHECK-NEXT:    br label [[FOR_COND]]
-;
-entry:
-  br label %for.cond
-
-for.cond:
-  br i1 %cond, label %if.then, label %for.inc
-
-if.then:
-  %0 = load i16, i16* @a, align 1
-  %tobool = icmp ne i16 %0, 0
-  br i1 %tobool, label %for.inc, label %for.inc
-
-for.inc:
-  %c.1 = phi i16 [ 2, %if.then ], [ 2, %if.then ], [ 1, %for.cond ]
-  br label %for.cond
-}
diff --git a/llvm/test/Transforms/LoopSimplifyCFG/pr39783.ll b/llvm/test/Transforms/LoopSimplifyCFG/pr39783.ll
deleted file mode 100644
index 9ebcc2a66a9..00000000000
--- a/llvm/test/Transforms/LoopSimplifyCFG/pr39783.ll
+++ /dev/null
@@ -1,110 +0,0 @@
-; REQUIRES: asserts
-; RUN: opt -march=z13 -S -loop-simplifycfg -enable-mssa-loop-dependency -enable-loop-simplifycfg-term-folding -verify-memoryssa 2>&1 < %s | FileCheck %s
-target datalayout = "E-m:e-i1:8:16-i8:8:16-i64:64-f128:64-v128:64-a:8:16-n32:64"
-
-@global = external dso_local local_unnamed_addr global i8, align 2
-@global.1 = external dso_local local_unnamed_addr global i32, align 4
-@global.2 = external dso_local local_unnamed_addr global i32, align 4
-@global.3 = external dso_local local_unnamed_addr global i16, align 2
-@global.4 = external dso_local local_unnamed_addr global i32, align 4
-
-; CHECK-LABEL: @test_01(
-
-define internal fastcc void @test_01() unnamed_addr {
-bb:
-  %tmp = load i32, i32* @global.2, align 4
-  %tmp1 = icmp eq i32 %tmp, 0
-  br i1 %tmp1, label %bb3, label %bb2
-
-bb2:                                              ; preds = %bb
-  br label %bb7
-
-bb3:                                              ; preds = %bb
-  br label %bb4
-
-bb4:                                              ; preds = %bb6, %bb3
-  br i1 true, label %bb5, label %bb6
-
-bb5:                                              ; preds = %bb4
-  store i16 0, i16* @global.3, align 2
-  br label %bb6
-
-bb6:                                              ; preds = %bb5, %bb4
-  br label %bb4
-
-bb7:                                              ; preds = %bb7, %bb2
-  %tmp8 = phi i32 [ 1, %bb7 ], [ 0, %bb2 ]
-  %tmp9 = icmp eq i32 %tmp8, 0
-  br i1 %tmp9, label %bb7, label %bb10
-
-bb10:                                             ; preds = %bb7
-  br label %bb11
-
-bb11:                                             ; preds = %bb13, %bb10
-  %tmp12 = icmp ult i32 %tmp, 6
-  br i1 %tmp12, label %bb13, label %bb14
-
-bb13:                                             ; preds = %bb11
-  store i32 0, i32* @global.1, align 4
-  br label %bb11
-
-bb14:                                             ; preds = %bb11
-  ret void
-}
-
-@global.5 = external dso_local local_unnamed_addr global i16, align 2
-
-declare dso_local void @spam() local_unnamed_addr
-
-declare dso_local void @blam() local_unnamed_addr
-
-declare dso_local i64 @quux.1() local_unnamed_addr
-
-declare dso_local void @bar() local_unnamed_addr
-
-; CHECK-LABEL: @test_02(
-
-define dso_local void @test_02(i8 signext %arg) local_unnamed_addr {
-bb:
-  br label %bb1
-
-bb1:                                              ; preds = %bb16, %bb
-  %tmp = phi i8 [ %arg, %bb ], [ %tmp17, %bb16 ]
-  %tmp2 = load i16, i16* @global.5, align 2
-  %tmp3 = icmp ugt i16 %tmp2, 56
-  br i1 %tmp3, label %bb4, label %bb18
-
-bb4:                                              ; preds = %bb1
-  %tmp5 = tail call i64 @quux.1()
-  %tmp6 = icmp eq i64 %tmp5, 0
-  br i1 %tmp6, label %bb13, label %bb7
-
-bb7:                                              ; preds = %bb4
-  br label %bb8
-
-bb8:                                              ; preds = %bb8, %bb7
-  %tmp9 = phi i32 [ 26, %bb7 ], [ %tmp10, %bb8 ]
-  tail call void @bar()
-  %tmp10 = add nsw i32 %tmp9, -1
-  %tmp11 = icmp eq i32 %tmp10, 12
-  br i1 %tmp11, label %bb12, label %bb8
-
-bb12:                                             ; preds = %bb8
-  br i1 false, label %bb14, label %bb16
-
-bb13:                                             ; preds = %bb4
-  tail call void @spam()
-  br label %bb14
-
-bb14:                                             ; preds = %bb13, %bb12
-  %tmp15 = phi i8 [ -23, %bb12 ], [ %tmp, %bb13 ]
-  tail call void @blam()
-  br label %bb16
-
-bb16:                                             ; preds = %bb14, %bb12
-  %tmp17 = phi i8 [ %tmp15, %bb14 ], [ -23, %bb12 ]
-  br label %bb1
-
-bb18:                                             ; preds = %bb1
-  ret void
-}
diff --git a/llvm/test/Transforms/LoopSimplifyCFG/scev.ll b/llvm/test/Transforms/LoopSimplifyCFG/scev.ll
deleted file mode 100644
index 123c7e6d4a8..00000000000
--- a/llvm/test/Transforms/LoopSimplifyCFG/scev.ll
+++ /dev/null
@@ -1,58 +0,0 @@
-; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; RUN: opt -S -loop-simplifycfg -verify-scev < %s | FileCheck %s
-; RUN: opt -S -loop-simplifycfg -verify-scev -enable-mssa-loop-dependency=true -verify-memoryssa < %s | FileCheck %s
-
-; Verify that the scev information is still valid. Verification should not fail
-
-define void @t_run_test() {
-; CHECK-LABEL: @t_run_test(
-; CHECK-NEXT:  entry:
-; CHECK-NEXT:    br label %[[LOOP_PH:.*]]
-; CHECK:       [[LOOP_PH]]:
-; CHECK-NEXT:    br label %[[LOOP_BODY:.*]]
-; CHECK:       [[LOOP_BODY]]:
-; CHECK-NEXT:    [[IV:%.*]] = phi i32 [ 0, %[[LOOP_PH]] ], [ [[INC:%.*]], %[[LOOP_BODY]] ]
-; CHECK-NEXT:    [[INC]] = add i32 [[IV]], 1
-; CHECK-NEXT:    [[CMP:%.*]] = icmp ult i32 [[INC]], 10
-; CHECK-NEXT:    br i1 [[CMP]], label %[[LOOP_BODY]], label %[[EXIT:.*]]
-; CHECK:       [[EXIT]]:
-; CHECK-NEXT:    br label %[[LOOP_BODY2:.*]]
-; CHECK:       [[LOOP_BODY2]]:
-; CHECK-NEXT:    [[IV2:%.*]] = phi i32 [ 0, %[[EXIT]] ], [ [[INC2:%.*]], %[[LOOP_BODY2]] ]
-; CHECK-NEXT:    [[INC2]] = add i32 [[IV2]], 1
-; CHECK-NEXT:    [[CMP2:%.*]] = icmp ult i32 [[INC2]], 10
-; CHECK-NEXT:    br i1 [[CMP2]], label %[[LOOP_BODY2]], label %[[EXIT2:.*]]
-; CHECK:       [[EXIT2]]:
-; CHECK-NEXT:    ret void
-;
-entry:
-  br label %loop.ph
-
-loop.ph:
-  br label %loop.header
-
-loop.header:
-  %iv = phi i32 [0, %loop.ph], [%inc, %loop.body]
-  br label %loop.body1
-
-loop.body1:
-  br label %loop.body
-
-loop.body:
-  %inc = add i32 %iv, 1
-  %cmp = icmp ult i32 %inc, 10
-  br i1 %cmp, label %loop.header, label %exit
-
-exit:
-  br label %loop.body2
-
-loop.body2:
-  %iv2 = phi i32 [0, %exit], [%inc2, %loop.body2]
-  %inc2 = add i32 %iv2, 1
-  %cmp2 = icmp ult i32 %inc2, 10
-  br i1 %cmp2, label %loop.body2, label %exit2
-
-exit2:
-  ret void
-}
-
diff --git a/llvm/test/Transforms/LoopSimplifyCFG/update_parents.ll b/llvm/test/Transforms/LoopSimplifyCFG/update_parents.ll
deleted file mode 100644
index b222a9f2195..00000000000
--- a/llvm/test/Transforms/LoopSimplifyCFG/update_parents.ll
+++ /dev/null
@@ -1,119 +0,0 @@
-; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; REQUIRES: asserts
-; RUN: opt -S -enable-loop-simplifycfg-term-folding=true -loop-simplifycfg -verify-loop-info -verify-dom-info -verify-loop-lcssa 2>&1 < %s | FileCheck %s
-; RUN: opt -S -enable-loop-simplifycfg-term-folding=true -passes='require<domtree>,loop(simplify-cfg)' -verify-loop-info -verify-dom-info -verify-loop-lcssa 2>&1 < %s | FileCheck %s
-; RUN: opt -S -enable-loop-simplifycfg-term-folding=true -loop-simplifycfg -enable-mssa-loop-dependency=true -verify-memoryssa -verify-loop-info -verify-dom-info -verify-loop-lcssa 2>&1 < %s | FileCheck %s
-
-target triple = "x86_64-unknown-linux-gnu"
-
-define void @test() {
-; CHECK-LABEL: @test(
-; CHECK-NEXT:    br label [[BB1:%.*]]
-; CHECK:       bb1.loopexit:
-; CHECK-NEXT:    br label [[BB1]]
-; CHECK:       bb1:
-; CHECK-NEXT:    br label [[BB2:%.*]]
-; CHECK:       bb2.loopexit:
-; CHECK-NEXT:    br label [[BB2]]
-; CHECK:       bb2:
-; CHECK-NEXT:    switch i32 0, label [[BB2_SPLIT:%.*]] [
-; CHECK-NEXT:    i32 1, label [[BB1_LOOPEXIT:%.*]]
-; CHECK-NEXT:    i32 2, label [[BB2_LOOPEXIT:%.*]]
-; CHECK-NEXT:    ]
-; CHECK:       bb2.split:
-; CHECK-NEXT:    br label [[BB3:%.*]]
-; CHECK:       bb3:
-; CHECK-NEXT:    br label [[BB3]]
-;
-
-  br label %bb1
-
-bb1:                                              ; preds = %bb4, %0
-  br label %bb2
-
-bb2:                                              ; preds = %bb6, %bb1
-  br label %bb3
-
-bb3:                                              ; preds = %bb8, %bb3, %bb2
-  br i1 false, label %bb4, label %bb3
-
-bb4:                                              ; preds = %bb8, %bb3
-  br i1 undef, label %bb1, label %bb6
-
-bb6:                                              ; preds = %bb4
-  br i1 undef, label %bb2, label %bb8
-
-bb8:                                              ; preds = %bb6
-  br i1 true, label %bb4, label %bb3
-}
-
-define void @test_many_subloops(i1 %c) {
-; CHECK-LABEL: @test_many_subloops(
-; CHECK-NEXT:    br label [[BB1:%.*]]
-; CHECK:       bb1.loopexit:
-; CHECK-NEXT:    br label [[BB1]]
-; CHECK:       bb1:
-; CHECK-NEXT:    br label [[BB2:%.*]]
-; CHECK:       bb2.loopexit:
-; CHECK-NEXT:    br label [[BB2]]
-; CHECK:       bb2:
-; CHECK-NEXT:    switch i32 0, label [[BB2_SPLIT:%.*]] [
-; CHECK-NEXT:    i32 1, label [[BB1_LOOPEXIT:%.*]]
-; CHECK-NEXT:    i32 2, label [[BB2_LOOPEXIT:%.*]]
-; CHECK-NEXT:    ]
-; CHECK:       bb2.split:
-; CHECK-NEXT:    br label [[BB3:%.*]]
-; CHECK:       bb3:
-; CHECK-NEXT:    br label [[BB3]]
-;
-
-  br label %bb1
-
-bb1:
-  br label %bb2
-
-bb2:
-  br label %bb3
-
-bb3:
-  br i1 false, label %bb4, label %bb3
-
-bb4:
-  br i1 undef, label %bb1, label %subloop1
-
-subloop1:
-  br i1 %c, label %subloop2, label %subloop11
-
-subloop11:
-  br i1 %c, label %subloop11, label %subloop12
-
-subloop12:
-  br i1 %c, label %subloop12, label %subloop13
-
-subloop13:
-  br i1 %c, label %subloop13, label %subloop1_latch
-
-subloop1_latch:
-  br label %subloop1
-
-subloop2:
-  br i1 %c, label %bb6, label %subloop21
-
-subloop21:
-  br i1 %c, label %subloop21, label %subloop22
-
-subloop22:
-  br i1 %c, label %subloop22, label %subloop23
-
-subloop23:
-  br i1 %c, label %subloop23, label %subloop2_latch
-
-subloop2_latch:
-  br label %subloop2
-
-bb6:
-  br i1 undef, label %bb2, label %bb8
-
-bb8:
-  br i1 true, label %bb4, label %bb3
-}