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| author | Marek Olsak <marek.olsak@amd.com> | 2018-04-10 22:48:23 +0000 |
|---|---|---|
| committer | Marek Olsak <marek.olsak@amd.com> | 2018-04-10 22:48:23 +0000 |
| commit | a9a58fa236ab19b5caae32330d31e30ebdf6751f (patch) | |
| tree | 907bcacd4096bc2131352fe96717b0d2a783929b /llvm/test/Transforms/LoadStoreVectorizer/AMDGPU | |
| parent | 3dc27f1a6914b1fb7dcbc152dc71ea6092f125a8 (diff) | |
| download | bcm5719-llvm-a9a58fa236ab19b5caae32330d31e30ebdf6751f.tar.gz bcm5719-llvm-a9a58fa236ab19b5caae32330d31e30ebdf6751f.zip | |
AMDGPU: enable 128-bit for local addr space under an option
Author: Samuel Pitoiset
ds_read_b128 and ds_write_b128 have been recently enabled
under the amdgpu-ds128 option because the performance benefit
is unclear.
Though, using 128-bit loads/stores for the local address space
appears to introduce regressions in tessellation shaders. Not
sure what is broken, but as ds_read_b128/ds_write_b128 are not
enabled by default, just introduce a global option and enable
128-bit only if requested (until it's fixed/used correctly).
v2: - fix regressions in merge-stores.ll and multiple_tails.ll
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105464
llvm-svn: 329764
Diffstat (limited to 'llvm/test/Transforms/LoadStoreVectorizer/AMDGPU')
| -rw-r--r-- | llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/merge-stores.ll | 3 | ||||
| -rw-r--r-- | llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/multiple_tails.ll | 3 |
2 files changed, 4 insertions, 2 deletions
diff --git a/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/merge-stores.ll b/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/merge-stores.ll index 5eb3b25c1dc..19fc44bb6c8 100644 --- a/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/merge-stores.ll +++ b/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/merge-stores.ll @@ -504,7 +504,8 @@ define amdgpu_kernel void @merge_local_store_2_constants_i32_align_2(i32 addrspa } ; CHECK-LABEL: @merge_local_store_4_constants_i32 -; CHECK: store <4 x i32> <i32 1234, i32 123, i32 456, i32 333>, <4 x i32> addrspace(3)* +; CHECK: store <2 x i32> <i32 456, i32 333>, <2 x i32> addrspace(3)* +; CHECK: store <2 x i32> <i32 1234, i32 123>, <2 x i32> addrspace(3)* define amdgpu_kernel void @merge_local_store_4_constants_i32(i32 addrspace(3)* %out) #0 { %out.gep.1 = getelementptr i32, i32 addrspace(3)* %out, i32 1 %out.gep.2 = getelementptr i32, i32 addrspace(3)* %out, i32 2 diff --git a/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/multiple_tails.ll b/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/multiple_tails.ll index b684ca8c12c..8a78f3d7e9b 100644 --- a/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/multiple_tails.ll +++ b/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/multiple_tails.ll @@ -29,10 +29,11 @@ define amdgpu_kernel void @no_crash(i32 %arg) { ; longest chain vectorized ; CHECK-LABEL: @interleave_get_longest -; CHECK: load <4 x i32> +; CHECK: load <2 x i32> ; CHECK: load i32 ; CHECK: store <2 x i32> zeroinitializer ; CHECK: load i32 +; CHECK: load <2 x i32> ; CHECK: load i32 ; CHECK: load i32 |
