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| author | Farhana Aleen <farhana.aleen@gmail.com> | 2018-03-09 17:41:39 +0000 |
|---|---|---|
| committer | Farhana Aleen <farhana.aleen@gmail.com> | 2018-03-09 17:41:39 +0000 |
| commit | a7cb31123c2526f04e6a587d6ada4084cefe6fb4 (patch) | |
| tree | 0f2e93bca2bbcf7eb638c5a1dad49127172cd5f8 /llvm/test/Transforms/LoadStoreVectorizer/AMDGPU | |
| parent | 91fc4e09499c24e9184853e9a53a953bdea8a356 (diff) | |
| download | bcm5719-llvm-a7cb31123c2526f04e6a587d6ada4084cefe6fb4.tar.gz bcm5719-llvm-a7cb31123c2526f04e6a587d6ada4084cefe6fb4.zip | |
[AMDGPU] Supported ds_read_b128 generation; Widened vector length for local address-space.
Summary: Starting from GCN 2nd generation, ISA supports ds_read_b128 on top of ds_read_b64.
This patch supports ds_read_b128 instruction pattern and generation of this instruction.
In the vectorizer, this patch also widen the vector length so that vectorizer generates
128 bit loads for local address-space which gets translated to ds_read_b128.
Since the performance benefit is not clear; compiler generates ds_read_b128 under -amdgpu-ds128.
Author: FarhanaAleen
Reviewed By: rampitec, arsenm
Subscribers: llvm-commits, AMDGPU
Differential Revision: https://reviews.llvm.org/D44210
llvm-svn: 327153
Diffstat (limited to 'llvm/test/Transforms/LoadStoreVectorizer/AMDGPU')
| -rw-r--r-- | llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/merge-stores.ll | 3 | ||||
| -rw-r--r-- | llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/multiple_tails.ll | 3 |
2 files changed, 2 insertions, 4 deletions
diff --git a/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/merge-stores.ll b/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/merge-stores.ll index 19fc44bb6c8..5eb3b25c1dc 100644 --- a/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/merge-stores.ll +++ b/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/merge-stores.ll @@ -504,8 +504,7 @@ define amdgpu_kernel void @merge_local_store_2_constants_i32_align_2(i32 addrspa } ; CHECK-LABEL: @merge_local_store_4_constants_i32 -; CHECK: store <2 x i32> <i32 456, i32 333>, <2 x i32> addrspace(3)* -; CHECK: store <2 x i32> <i32 1234, i32 123>, <2 x i32> addrspace(3)* +; CHECK: store <4 x i32> <i32 1234, i32 123, i32 456, i32 333>, <4 x i32> addrspace(3)* define amdgpu_kernel void @merge_local_store_4_constants_i32(i32 addrspace(3)* %out) #0 { %out.gep.1 = getelementptr i32, i32 addrspace(3)* %out, i32 1 %out.gep.2 = getelementptr i32, i32 addrspace(3)* %out, i32 2 diff --git a/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/multiple_tails.ll b/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/multiple_tails.ll index 8a78f3d7e9b..b684ca8c12c 100644 --- a/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/multiple_tails.ll +++ b/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/multiple_tails.ll @@ -29,11 +29,10 @@ define amdgpu_kernel void @no_crash(i32 %arg) { ; longest chain vectorized ; CHECK-LABEL: @interleave_get_longest -; CHECK: load <2 x i32> +; CHECK: load <4 x i32> ; CHECK: load i32 ; CHECK: store <2 x i32> zeroinitializer ; CHECK: load i32 -; CHECK: load <2 x i32> ; CHECK: load i32 ; CHECK: load i32 |
