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authorJim Grosbach <grosbach@apple.com>2013-09-04 19:08:44 +0000
committerJim Grosbach <grosbach@apple.com>2013-09-04 19:08:44 +0000
commit13654dd30362503f58f2a665b95b04ea6638618c (patch)
tree666f4752255e39d8241c747ed3f680926dcae55c /llvm/test/Transforms/Internalize/apifile
parentb832d49822a2f4543b73ecdad334f5fa1261c4f4 (diff)
downloadbcm5719-llvm-13654dd30362503f58f2a665b95b04ea6638618c.tar.gz
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ARM: Teach A15 SDOptimizer to properly handle D-reg by-lane.
These instructions, such as vmul.f32, require the second source operand to be in D0-D15 rather than the full D0-D31. When optimizing, make sure to account for that by constraining the register class of a replacement virtual register to be compatible with the virtual register(s) it's replacing. I've been unsuccessful in creating a non-fragile regression test. This issue was detected by the LLVM nightly test suite running on an A15 (Bullet). PR17093: http://llvm.org/bugs/show_bug.cgi?id=17093 llvm-svn: 189972
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