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| author | Matthew Simpson <mssimpso@codeaurora.org> | 2017-04-10 18:34:37 +0000 |
|---|---|---|
| committer | Matthew Simpson <mssimpso@codeaurora.org> | 2017-04-10 18:34:37 +0000 |
| commit | 1468d3e04ee4f93e7951e902afbc74e585243f3f (patch) | |
| tree | b284aae10829b331611f33dd37f565ab2936b716 /llvm/test/Transforms/InterleavedAccess | |
| parent | 0d830ff7bf86e68d53931259af81dfa70bb9935b (diff) | |
| download | bcm5719-llvm-1468d3e04ee4f93e7951e902afbc74e585243f3f.tar.gz bcm5719-llvm-1468d3e04ee4f93e7951e902afbc74e585243f3f.zip | |
[ARM/AArch64] Ensure valid vector element types for interleaved accesses
This patch refactors and strengthens the type checks performed for interleaved
accesses. The primary functional change is to ensure that the interleaved
accesses have valid element types. The added test cases previously failed
because the element type is f128.
Differential Revision: https://reviews.llvm.org/D31817
llvm-svn: 299864
Diffstat (limited to 'llvm/test/Transforms/InterleavedAccess')
| -rw-r--r-- | llvm/test/Transforms/InterleavedAccess/AArch64/interleaved-accesses.ll | 14 | ||||
| -rw-r--r-- | llvm/test/Transforms/InterleavedAccess/ARM/interleaved-accesses.ll | 11 |
2 files changed, 25 insertions, 0 deletions
diff --git a/llvm/test/Transforms/InterleavedAccess/AArch64/interleaved-accesses.ll b/llvm/test/Transforms/InterleavedAccess/AArch64/interleaved-accesses.ll index 779edb56751..a038fd1a411 100644 --- a/llvm/test/Transforms/InterleavedAccess/AArch64/interleaved-accesses.ll +++ b/llvm/test/Transforms/InterleavedAccess/AArch64/interleaved-accesses.ll @@ -760,3 +760,17 @@ define void @store_factor4_wide(<32 x i32>* %ptr, <8 x i32> %v0, <8 x i32> %v1, store <32 x i32> %interleaved.vec, <32 x i32>* %ptr, align 4 ret void } + +define void @load_factor2_fp128(<4 x fp128>* %ptr) { +; NEON-LABEL: @load_factor2_fp128( +; NEON-NOT: @llvm.aarch64.neon +; NEON: ret void +; NO_NEON-LABEL: @load_factor2_fp128( +; NO_NEON-NOT: @llvm.aarch64.neon +; NO_NEON: ret void +; + %interleaved.vec = load <4 x fp128>, <4 x fp128>* %ptr, align 16 + %v0 = shufflevector <4 x fp128> %interleaved.vec, <4 x fp128> undef, <2 x i32> <i32 0, i32 2> + %v1 = shufflevector <4 x fp128> %interleaved.vec, <4 x fp128> undef, <2 x i32> <i32 1, i32 3> + ret void +} diff --git a/llvm/test/Transforms/InterleavedAccess/ARM/interleaved-accesses.ll b/llvm/test/Transforms/InterleavedAccess/ARM/interleaved-accesses.ll index 455ed12c663..5938f9d7321 100644 --- a/llvm/test/Transforms/InterleavedAccess/ARM/interleaved-accesses.ll +++ b/llvm/test/Transforms/InterleavedAccess/ARM/interleaved-accesses.ll @@ -843,3 +843,14 @@ define void @store_factor4_wide(<32 x i32>* %ptr, <8 x i32> %v0, <8 x i32> %v1, store <32 x i32> %interleaved.vec, <32 x i32>* %ptr, align 4 ret void } + +define void @load_factor2_fp128(<4 x fp128>* %ptr) { +; ALL-LABEL: @load_factor2_fp128( +; ALL-NOT: @llvm.arm.neon +; ALL: ret void +; + %interleaved.vec = load <4 x fp128>, <4 x fp128>* %ptr, align 16 + %v0 = shufflevector <4 x fp128> %interleaved.vec, <4 x fp128> undef, <2 x i32> <i32 0, i32 2> + %v1 = shufflevector <4 x fp128> %interleaved.vec, <4 x fp128> undef, <2 x i32> <i32 1, i32 3> + ret void +} |
