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authorCraig Topper <craig.topper@intel.com>2017-06-13 23:30:41 +0000
committerCraig Topper <craig.topper@intel.com>2017-06-13 23:30:41 +0000
commit82e4c2dfd2b5d5e9af287b5a851c7a13f7a6020d (patch)
tree1a8158f4f46b76fb89a44871cf5cb25df02c5f4a /llvm/test/Transforms/InstCombine
parentf51c80559c55070c053169d761dba28845a1280f (diff)
downloadbcm5719-llvm-82e4c2dfd2b5d5e9af287b5a851c7a13f7a6020d.tar.gz
bcm5719-llvm-82e4c2dfd2b5d5e9af287b5a851c7a13f7a6020d.zip
[InstCombine] Add test cases demonstrating failure to handle (select (icmp eq (and X, C1), 0), Y, (or Y, C2)) when the icmp portion gets turned into a truncate and a signed compare with 0.
InstCombine has an optimization that recognizes an and with the sign bit of legal type size and turns it into a truncate and compare that checks the sign bit. But the select handling code doesn't recognize this idiom. llvm-svn: 305338
Diffstat (limited to 'llvm/test/Transforms/InstCombine')
-rw-r--r--llvm/test/Transforms/InstCombine/select-with-bitwise-ops.ll31
1 files changed, 31 insertions, 0 deletions
diff --git a/llvm/test/Transforms/InstCombine/select-with-bitwise-ops.ll b/llvm/test/Transforms/InstCombine/select-with-bitwise-ops.ll
index 68b73af21a8..55ba730599d 100644
--- a/llvm/test/Transforms/InstCombine/select-with-bitwise-ops.ll
+++ b/llvm/test/Transforms/InstCombine/select-with-bitwise-ops.ll
@@ -1,6 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -instcombine -S | FileCheck %s
+target datalayout = "n8:16:32:64"
+
define i32 @select_icmp_eq_and_1_0_or_2(i32 %x, i32 %y) {
; CHECK-LABEL: @select_icmp_eq_and_1_0_or_2(
; CHECK-NEXT: [[AND:%.*]] = shl i32 %x, 1
@@ -295,3 +297,32 @@ define i32 @test67(i16 %x) {
ret i32 %3
}
+define i32 @test68(i32 %x, i32 %y) {
+; CHECK-LABEL: @test68(
+; CHECK-NEXT: [[TMP1:%.*]] = trunc i32 [[X:%.*]] to i8
+; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i8 [[TMP1]], -1
+; CHECK-NEXT: [[OR:%.*]] = or i32 [[Y:%.*]], 2
+; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP]], i32 [[Y]], i32 [[OR]]
+; CHECK-NEXT: ret i32 [[SELECT]]
+;
+ %and = and i32 %x, 128
+ %cmp = icmp eq i32 %and, 0
+ %or = or i32 %y, 2
+ %select = select i1 %cmp, i32 %y, i32 %or
+ ret i32 %select
+}
+
+define i32 @test69(i32 %x, i32 %y) {
+; CHECK-LABEL: @test69(
+; CHECK-NEXT: [[TMP1:%.*]] = trunc i32 [[X:%.*]] to i8
+; CHECK-NEXT: [[CMP:%.*]] = icmp slt i8 [[TMP1]], 0
+; CHECK-NEXT: [[OR:%.*]] = or i32 [[Y:%.*]], 2
+; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP]], i32 [[Y]], i32 [[OR]]
+; CHECK-NEXT: ret i32 [[SELECT]]
+;
+ %and = and i32 %x, 128
+ %cmp = icmp ne i32 %and, 0
+ %or = or i32 %y, 2
+ %select = select i1 %cmp, i32 %y, i32 %or
+ ret i32 %select
+}
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