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| author | David Blaikie <dblaikie@gmail.com> | 2015-02-27 21:17:42 +0000 |
|---|---|---|
| committer | David Blaikie <dblaikie@gmail.com> | 2015-02-27 21:17:42 +0000 |
| commit | a79ac14fa68297f9888bc70a10df5ed9b8864e38 (patch) | |
| tree | 8d8217a8928e3ee599bdde405e2e178b3a55b645 /llvm/test/Transforms/InstCombine/vec_shuffle.ll | |
| parent | 83687fb9e654c9d0086e7f6b728c26fa0b729e71 (diff) | |
| download | bcm5719-llvm-a79ac14fa68297f9888bc70a10df5ed9b8864e38.tar.gz bcm5719-llvm-a79ac14fa68297f9888bc70a10df5ed9b8864e38.zip | |
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction
Essentially the same as the GEP change in r230786.
A similar migration script can be used to update test cases, though a few more
test case improvements/changes were required this time around: (r229269-r229278)
import fileinput
import sys
import re
pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)")
for line in sys.stdin:
sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line))
Reviewers: rafael, dexonsmith, grosser
Differential Revision: http://reviews.llvm.org/D7649
llvm-svn: 230794
Diffstat (limited to 'llvm/test/Transforms/InstCombine/vec_shuffle.ll')
| -rw-r--r-- | llvm/test/Transforms/InstCombine/vec_shuffle.ll | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/llvm/test/Transforms/InstCombine/vec_shuffle.ll b/llvm/test/Transforms/InstCombine/vec_shuffle.ll index eb4e9d6f8c3..164e315c46a 100644 --- a/llvm/test/Transforms/InstCombine/vec_shuffle.ll +++ b/llvm/test/Transforms/InstCombine/vec_shuffle.ll @@ -190,11 +190,11 @@ define void @test14(i16 %conv10) { %tmp = alloca <4 x i16>, align 8 %vecinit6 = insertelement <4 x i16> undef, i16 23, i32 3 store <4 x i16> %vecinit6, <4 x i16>* undef - %tmp1 = load <4 x i16>* undef + %tmp1 = load <4 x i16>, <4 x i16>* undef %vecinit11 = insertelement <4 x i16> undef, i16 %conv10, i32 3 %div = udiv <4 x i16> %tmp1, %vecinit11 store <4 x i16> %div, <4 x i16>* %tmp - %tmp4 = load <4 x i16>* %tmp + %tmp4 = load <4 x i16>, <4 x i16>* %tmp %tmp5 = shufflevector <4 x i16> %tmp4, <4 x i16> undef, <2 x i32> <i32 2, i32 0> %cmp = icmp ule <2 x i16> %tmp5, undef %sext = sext <2 x i1> %cmp to <2 x i16> |
