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| author | Craig Topper <craig.topper@intel.com> | 2017-08-05 20:00:42 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2017-08-05 20:00:42 +0000 |
| commit | 65dd32afbc2aba6975a44fab7c8a4f4f05e104d7 (patch) | |
| tree | 935bdb8b4653b34f40926c7a333c4f3dbedca6e1 /llvm/test/Transforms/InstCombine/select-with-bitwise-ops.ll | |
| parent | 1bbcab9ca59e371f73074c052242f06cdd53038d (diff) | |
| download | bcm5719-llvm-65dd32afbc2aba6975a44fab7c8a4f4f05e104d7.tar.gz bcm5719-llvm-65dd32afbc2aba6975a44fab7c8a4f4f05e104d7.zip | |
[InstCombine] Teach the code that pulls logical operators through constant shifts to handle vector splats too.
llvm-svn: 310185
Diffstat (limited to 'llvm/test/Transforms/InstCombine/select-with-bitwise-ops.ll')
| -rw-r--r-- | llvm/test/Transforms/InstCombine/select-with-bitwise-ops.ll | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/llvm/test/Transforms/InstCombine/select-with-bitwise-ops.ll b/llvm/test/Transforms/InstCombine/select-with-bitwise-ops.ll index 7580fadfd89..24e5f25701a 100644 --- a/llvm/test/Transforms/InstCombine/select-with-bitwise-ops.ll +++ b/llvm/test/Transforms/InstCombine/select-with-bitwise-ops.ll @@ -270,9 +270,9 @@ define i32 @test65(i64 %x) { define <2 x i32> @test65vec(<2 x i64> %x) { ; CHECK-LABEL: @test65vec( -; CHECK-NEXT: [[TMP1:%.*]] = and <2 x i64> [[X:%.*]], <i64 16, i64 16> -; CHECK-NEXT: [[TMP2:%.*]] = lshr exact <2 x i64> [[TMP1]], <i64 3, i64 3> -; CHECK-NEXT: [[TMP3:%.*]] = trunc <2 x i64> [[TMP2]] to <2 x i32> +; CHECK-NEXT: [[TMP1:%.*]] = lshr <2 x i64> [[X:%.*]], <i64 3, i64 3> +; CHECK-NEXT: [[TMP2:%.*]] = trunc <2 x i64> [[TMP1]] to <2 x i32> +; CHECK-NEXT: [[TMP3:%.*]] = and <2 x i32> [[TMP2]], <i32 2, i32 2> ; CHECK-NEXT: [[TMP4:%.*]] = or <2 x i32> [[TMP3]], <i32 40, i32 40> ; CHECK-NEXT: [[TMP5:%.*]] = xor <2 x i32> [[TMP4]], <i32 2, i32 2> ; CHECK-NEXT: ret <2 x i32> [[TMP5]] @@ -299,9 +299,9 @@ define i32 @test66(i64 %x) { define <2 x i32> @test66vec(<2 x i64> %x) { ; CHECK-LABEL: @test66vec( -; CHECK-NEXT: [[TMP1:%.*]] = and <2 x i64> [[X:%.*]], <i64 4294967296, i64 4294967296> -; CHECK-NEXT: [[TMP2:%.*]] = lshr exact <2 x i64> [[TMP1]], <i64 31, i64 31> -; CHECK-NEXT: [[TMP3:%.*]] = trunc <2 x i64> [[TMP2]] to <2 x i32> +; CHECK-NEXT: [[TMP1:%.*]] = lshr <2 x i64> [[X:%.*]], <i64 31, i64 31> +; CHECK-NEXT: [[TMP2:%.*]] = trunc <2 x i64> [[TMP1]] to <2 x i32> +; CHECK-NEXT: [[TMP3:%.*]] = and <2 x i32> [[TMP2]], <i32 2, i32 2> ; CHECK-NEXT: [[TMP4:%.*]] = or <2 x i32> [[TMP3]], <i32 40, i32 40> ; CHECK-NEXT: [[TMP5:%.*]] = xor <2 x i32> [[TMP4]], <i32 2, i32 2> ; CHECK-NEXT: ret <2 x i32> [[TMP5]] @@ -342,8 +342,8 @@ define i32 @test67(i16 %x) { define <2 x i32> @test67vec(<2 x i16> %x) { ; CHECK-LABEL: @test67vec( -; CHECK-NEXT: [[TMP1:%.*]] = and <2 x i16> [[X:%.*]], <i16 4, i16 4> -; CHECK-NEXT: [[TMP2:%.*]] = lshr exact <2 x i16> [[TMP1]], <i16 1, i16 1> +; CHECK-NEXT: [[TMP1:%.*]] = lshr <2 x i16> [[X:%.*]], <i16 1, i16 1> +; CHECK-NEXT: [[TMP2:%.*]] = and <2 x i16> [[TMP1]], <i16 2, i16 2> ; CHECK-NEXT: [[TMP3:%.*]] = or <2 x i16> [[TMP2]], <i16 40, i16 40> ; CHECK-NEXT: [[TMP4:%.*]] = xor <2 x i16> [[TMP3]], <i16 2, i16 2> ; CHECK-NEXT: [[TMP5:%.*]] = zext <2 x i16> [[TMP4]] to <2 x i32> |
