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| author | Alexey Bataev <a.bataev@hotmail.com> | 2017-12-12 15:54:49 +0000 |
|---|---|---|
| committer | Alexey Bataev <a.bataev@hotmail.com> | 2017-12-12 15:54:49 +0000 |
| commit | fb68c48a8201a5d6066994699e098b267d4e418c (patch) | |
| tree | 29c88494ffb5ea06fefc90e8f772b7314f78b4f1 /llvm/test/Transforms/InstCombine/multiple-uses-load-bitcast-select.ll | |
| parent | 9ed84c8ae85a6274afc8c266dc662bd9e5a9fa21 (diff) | |
| download | bcm5719-llvm-fb68c48a8201a5d6066994699e098b267d4e418c.tar.gz bcm5719-llvm-fb68c48a8201a5d6066994699e098b267d4e418c.zip | |
[InstCombine] Fix PR35618: Instcombine hangs on single minmax load bitcast.
Summary:
If we have pattern `store (load(bitcast(select (cmp(V1, V2), &V1,
&V2)))), bitcast)`, but the load is used in other instructions, it leads
to looping in InstCombiner. Patch adds additional check that all users
of the load instructions are stores and then replaces all uses of load
instruction by the new one with new type.
Reviewers: RKSimon, spatel, majnemer
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D41072
llvm-svn: 320488
Diffstat (limited to 'llvm/test/Transforms/InstCombine/multiple-uses-load-bitcast-select.ll')
| -rw-r--r-- | llvm/test/Transforms/InstCombine/multiple-uses-load-bitcast-select.ll | 30 |
1 files changed, 30 insertions, 0 deletions
diff --git a/llvm/test/Transforms/InstCombine/multiple-uses-load-bitcast-select.ll b/llvm/test/Transforms/InstCombine/multiple-uses-load-bitcast-select.ll new file mode 100644 index 00000000000..28509df6d2f --- /dev/null +++ b/llvm/test/Transforms/InstCombine/multiple-uses-load-bitcast-select.ll @@ -0,0 +1,30 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py +; RUN: opt < %s -instcombine -S -data-layout="E-m:e-i1:8:16-i8:8:16-i64:64-f128:64-v128:64-a:8:16-n32:64" | FileCheck %s + +define void @PR35618(i64* %st1, double* %st2) { +; CHECK-LABEL: @PR35618( +; CHECK-NEXT: [[Y1:%.*]] = alloca double, align 8 +; CHECK-NEXT: [[Z1:%.*]] = alloca double, align 8 +; CHECK-NEXT: [[LD1:%.*]] = load double, double* [[Y1]], align 8 +; CHECK-NEXT: [[LD2:%.*]] = load double, double* [[Z1]], align 8 +; CHECK-NEXT: [[TMP10:%.*]] = fcmp olt double [[LD1]], [[LD2]] +; CHECK-NEXT: [[TMP121:%.*]] = select i1 [[TMP10]], double [[LD1]], double [[LD2]] +; CHECK-NEXT: [[TMP1:%.*]] = bitcast i64* [[ST1:%.*]] to double* +; CHECK-NEXT: store double [[TMP121]], double* [[TMP1]], align 8 +; CHECK-NEXT: store double [[TMP121]], double* [[ST2:%.*]], align 8 +; CHECK-NEXT: ret void +; + %y1 = alloca double + %z1 = alloca double + %ld1 = load double, double* %y1 + %ld2 = load double, double* %z1 + %tmp10 = fcmp olt double %ld1, %ld2 + %sel = select i1 %tmp10, double* %y1, double* %z1 + %tmp11 = bitcast double* %sel to i64* + %tmp12 = load i64, i64* %tmp11 + store i64 %tmp12, i64* %st1 + %bc = bitcast double* %st2 to i64* + store i64 %tmp12, i64* %bc + ret void +} + |
