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| author | Sanjay Patel <spatel@rotateright.com> | 2016-08-19 22:33:26 +0000 |
|---|---|---|
| committer | Sanjay Patel <spatel@rotateright.com> | 2016-08-19 22:33:26 +0000 |
| commit | fa7de606c439d90665ef25f0c6d447a9476c2fc6 (patch) | |
| tree | bb58c6b6c98cbe020ff90e16d54ec27d8332e622 /llvm/test/Transforms/InstCombine/icmp.ll | |
| parent | a7d6fc9618aaee28fbbe2324ee8f6168e551d64f (diff) | |
| download | bcm5719-llvm-fa7de606c439d90665ef25f0c6d447a9476c2fc6.tar.gz bcm5719-llvm-fa7de606c439d90665ef25f0c6d447a9476c2fc6.zip | |
[InstCombine] use m_APInt to allow icmp (shl X, Y), C folds for splat constant vectors, part 1
This is a partial enablement (move the ConstantInt guard down) because there are many
different folds here and one of the later ones will require reworking 'isSignBitCheck'.
llvm-svn: 279339
Diffstat (limited to 'llvm/test/Transforms/InstCombine/icmp.ll')
| -rw-r--r-- | llvm/test/Transforms/InstCombine/icmp.ll | 28 |
1 files changed, 16 insertions, 12 deletions
diff --git a/llvm/test/Transforms/InstCombine/icmp.ll b/llvm/test/Transforms/InstCombine/icmp.ll index b15a960c0db..e1b58393f79 100644 --- a/llvm/test/Transforms/InstCombine/icmp.ll +++ b/llvm/test/Transforms/InstCombine/icmp.ll @@ -1183,11 +1183,9 @@ define i1 @icmp_shl_nsw_eq(i32 %x) { ret i1 %cmp } -; FIXME: Vectors should fold the same way. define <2 x i1> @icmp_shl_nsw_eq_vec(<2 x i32> %x) { ; CHECK-LABEL: @icmp_shl_nsw_eq_vec( -; CHECK-NEXT: [[MUL:%.*]] = shl nsw <2 x i32> %x, <i32 5, i32 5> -; CHECK-NEXT: [[CMP:%.*]] = icmp eq <2 x i32> [[MUL]], zeroinitializer +; CHECK-NEXT: [[CMP:%.*]] = icmp eq <2 x i32> %x, zeroinitializer ; CHECK-NEXT: ret <2 x i1> [[CMP]] ; %mul = shl nsw <2 x i32> %x, <i32 5, i32 5> @@ -1206,11 +1204,10 @@ define i1 @icmp_shl_eq(i32 %x) { ret i1 %cmp } -; FIXME: Vectors should fold the same way. define <2 x i1> @icmp_shl_eq_vec(<2 x i32> %x) { ; CHECK-LABEL: @icmp_shl_eq_vec( -; CHECK-NEXT: [[MUL:%.*]] = shl <2 x i32> %x, <i32 5, i32 5> -; CHECK-NEXT: [[CMP:%.*]] = icmp eq <2 x i32> [[MUL]], zeroinitializer +; CHECK-NEXT: [[MUL_MASK:%.*]] = and <2 x i32> %x, <i32 134217727, i32 134217727> +; CHECK-NEXT: [[CMP:%.*]] = icmp eq <2 x i32> [[MUL_MASK]], zeroinitializer ; CHECK-NEXT: ret <2 x i1> [[CMP]] ; %mul = shl <2 x i32> %x, <i32 5, i32 5> @@ -1228,11 +1225,9 @@ define i1 @icmp_shl_nsw_ne(i32 %x) { ret i1 %cmp } -; FIXME: Vectors should fold the same way. define <2 x i1> @icmp_shl_nsw_ne_vec(<2 x i32> %x) { ; CHECK-LABEL: @icmp_shl_nsw_ne_vec( -; CHECK-NEXT: [[MUL:%.*]] = shl nsw <2 x i32> %x, <i32 7, i32 7> -; CHECK-NEXT: [[CMP:%.*]] = icmp ne <2 x i32> [[MUL]], zeroinitializer +; CHECK-NEXT: [[CMP:%.*]] = icmp ne <2 x i32> %x, zeroinitializer ; CHECK-NEXT: ret <2 x i1> [[CMP]] ; %mul = shl nsw <2 x i32> %x, <i32 7, i32 7> @@ -1251,11 +1246,10 @@ define i1 @icmp_shl_ne(i32 %x) { ret i1 %cmp } -; FIXME: Vectors should fold the same way. define <2 x i1> @icmp_shl_ne_vec(<2 x i32> %x) { ; CHECK-LABEL: @icmp_shl_ne_vec( -; CHECK-NEXT: [[MUL:%.*]] = shl <2 x i32> %x, <i32 7, i32 7> -; CHECK-NEXT: [[CMP:%.*]] = icmp ne <2 x i32> [[MUL]], zeroinitializer +; CHECK-NEXT: [[MUL_MASK:%.*]] = and <2 x i32> %x, <i32 33554431, i32 33554431> +; CHECK-NEXT: [[CMP:%.*]] = icmp ne <2 x i32> [[MUL_MASK]], zeroinitializer ; CHECK-NEXT: ret <2 x i1> [[CMP]] ; %mul = shl <2 x i32> %x, <i32 7, i32 7> @@ -1263,6 +1257,16 @@ define <2 x i1> @icmp_shl_ne_vec(<2 x i32> %x) { ret <2 x i1> %cmp } +define <2 x i1> @icmp_shl_nuw_ne_vec(<2 x i32> %x) { +; CHECK-LABEL: @icmp_shl_nuw_ne_vec( +; CHECK-NEXT: [[CMP:%.*]] = icmp ne <2 x i32> %x, <i32 2, i32 2> +; CHECK-NEXT: ret <2 x i1> [[CMP]] +; + %shl = shl nuw <2 x i32> %x, <i32 7, i32 7> + %cmp = icmp ne <2 x i32> %shl, <i32 256, i32 256> + ret <2 x i1> %cmp +} + ; If the (mul x, C) preserved the sign and this is sign test, ; compare the LHS operand instead define i1 @icmp_mul_nsw(i32 %x) { |
