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author | Sanjay Patel <spatel@rotateright.com> | 2016-11-22 22:05:48 +0000 |
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committer | Sanjay Patel <spatel@rotateright.com> | 2016-11-22 22:05:48 +0000 |
commit | e359eaaf708e227eeeaf3f4a9640e5cde0f3c05a (patch) | |
tree | 47bd8a4315d352018517d37c89c2e9dd60e6d22e /llvm/test/Transforms/InstCombine/bitcast.ll | |
parent | eda365cf807c22ad939dd6d3017cf6a3679675b6 (diff) | |
download | bcm5719-llvm-e359eaaf708e227eeeaf3f4a9640e5cde0f3c05a.tar.gz bcm5719-llvm-e359eaaf708e227eeeaf3f4a9640e5cde0f3c05a.zip |
[InstCombine] change bitwise logic type to eliminate bitcasts
In PR27925:
https://llvm.org/bugs/show_bug.cgi?id=27925
...we proposed adding this fold to eliminate a bitcast. In D20774, there was
some concern about changing the type of a bitwise op as well as creating
bitcasts that might not be free for a target. However, if we're strictly
eliminating an instruction (by limiting this to one-use ops), then we should
be able to do this in InstCombine.
But we're cautiously restricting the transform for now to vector types to
avoid possible backend problems. A transform to make sure the logic op is
legal for the target should be added to reverse this transform and improve
codegen.
Differential Revision: https://reviews.llvm.org/D26641
llvm-svn: 287707
Diffstat (limited to 'llvm/test/Transforms/InstCombine/bitcast.ll')
-rw-r--r-- | llvm/test/Transforms/InstCombine/bitcast.ll | 29 |
1 files changed, 25 insertions, 4 deletions
diff --git a/llvm/test/Transforms/InstCombine/bitcast.ll b/llvm/test/Transforms/InstCombine/bitcast.ll index 8d8c25a1095..49cb5618831 100644 --- a/llvm/test/Transforms/InstCombine/bitcast.ll +++ b/llvm/test/Transforms/InstCombine/bitcast.ll @@ -74,10 +74,8 @@ define <2 x i32> @or_bitcast_int_to_vec(i64 %a) { define <4 x i32> @bitcasts_and_bitcast(<4 x i32> %a, <8 x i16> %b) { ; CHECK-LABEL: @bitcasts_and_bitcast( -; CHECK-NEXT: [[BC1:%.*]] = bitcast <4 x i32> %a to <2 x i64> -; CHECK-NEXT: [[BC2:%.*]] = bitcast <8 x i16> %b to <2 x i64> -; CHECK-NEXT: [[AND:%.*]] = and <2 x i64> [[BC2]], [[BC1]] -; CHECK-NEXT: [[BC3:%.*]] = bitcast <2 x i64> [[AND]] to <4 x i32> +; CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i16> %b to <4 x i32> +; CHECK-NEXT: [[BC3:%.*]] = and <4 x i32> [[TMP1]], %a ; CHECK-NEXT: ret <4 x i32> [[BC3]] ; %bc1 = bitcast <4 x i32> %a to <2 x i64> @@ -87,6 +85,27 @@ define <4 x i32> @bitcasts_and_bitcast(<4 x i32> %a, <8 x i16> %b) { ret <4 x i32> %bc3 } +; The destination must have an integer element type. +; FIXME: We can still eliminate one bitcast in this test by doing the logic op +; in the type of the input that has an integer element type. + +define <4 x float> @bitcasts_and_bitcast_to_fp(<4 x float> %a, <8 x i16> %b) { +; CHECK-LABEL: @bitcasts_and_bitcast_to_fp( +; CHECK-NEXT: [[BC1:%.*]] = bitcast <4 x float> %a to <2 x i64> +; CHECK-NEXT: [[BC2:%.*]] = bitcast <8 x i16> %b to <2 x i64> +; CHECK-NEXT: [[AND:%.*]] = and <2 x i64> [[BC2]], [[BC1]] +; CHECK-NEXT: [[BC3:%.*]] = bitcast <2 x i64> [[AND]] to <4 x float> +; CHECK-NEXT: ret <4 x float> [[BC3]] +; + %bc1 = bitcast <4 x float> %a to <2 x i64> + %bc2 = bitcast <8 x i16> %b to <2 x i64> + %and = and <2 x i64> %bc2, %bc1 + %bc3 = bitcast <2 x i64> %and to <4 x float> + ret <4 x float> %bc3 +} + +; FIXME: Transform limited from changing vector op to integer op to avoid codegen problems. + define i128 @bitcast_or_bitcast(i128 %a, <2 x i64> %b) { ; CHECK-LABEL: @bitcast_or_bitcast( ; CHECK-NEXT: [[BC1:%.*]] = bitcast i128 %a to <2 x i64> @@ -100,6 +119,8 @@ define i128 @bitcast_or_bitcast(i128 %a, <2 x i64> %b) { ret i128 %bc2 } +; FIXME: Transform limited from changing integer op to vector op to avoid codegen problems. + define <4 x i32> @bitcast_xor_bitcast(<4 x i32> %a, i128 %b) { ; CHECK-LABEL: @bitcast_xor_bitcast( ; CHECK-NEXT: [[BC1:%.*]] = bitcast <4 x i32> %a to i128 |