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author | Reid Spencer <rspencer@reidspencer.com> | 2007-03-23 20:48:34 +0000 |
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committer | Reid Spencer <rspencer@reidspencer.com> | 2007-03-23 20:48:34 +0000 |
commit | ea8b07ee6badc731c52a0e1668c7a8eacf9a3b1d (patch) | |
tree | 9c0b8d2ca1fb929ef8028f6689ee28114e409e83 /llvm/test/Transforms/InstCombine/apint-add2.ll | |
parent | 6d39206bc2bd818180b798483188899716410554 (diff) | |
download | bcm5719-llvm-ea8b07ee6badc731c52a0e1668c7a8eacf9a3b1d.tar.gz bcm5719-llvm-ea8b07ee6badc731c52a0e1668c7a8eacf9a3b1d.zip |
Add test case for testing InstCombine with arbitrary precision integer
types. These tests mimic the integer test cases in the normal InstCombine
test suite but use "strange" integer bit widths.
Most tests written by Zhou Sheng, a few by me.
llvm-svn: 35284
Diffstat (limited to 'llvm/test/Transforms/InstCombine/apint-add2.ll')
-rw-r--r-- | llvm/test/Transforms/InstCombine/apint-add2.ll | 56 |
1 files changed, 56 insertions, 0 deletions
diff --git a/llvm/test/Transforms/InstCombine/apint-add2.ll b/llvm/test/Transforms/InstCombine/apint-add2.ll new file mode 100644 index 00000000000..f60e3bea1ec --- /dev/null +++ b/llvm/test/Transforms/InstCombine/apint-add2.ll @@ -0,0 +1,56 @@ +; This test makes sure that add instructions are properly eliminated. +; This test is for Integer BitWidth > 64 && BitWidth <= 1024. + +; RUN: llvm-as < %s | opt -instcombine -disable-output && +; RUN: llvm-as < %s | opt -instcombine | llvm-dis | \ +; RUN: grep -v OK | not grep add + +implementation + +define i111 @test1(i111 %x) { + %tmp.2 = shl i111 1, 110 + %tmp.4 = xor i111 %x, %tmp.2 + ;; Add of sign bit -> xor of sign bit. + %tmp.6 = add i111 %tmp.4, %tmp.2 + ret i111 %tmp.6 +} + +define i65 @test2(i65 %x) { + %tmp.0 = shl i65 1, 64 + %tmp.2 = xor i65 %x, %tmp.0 + ;; Add of sign bit -> xor of sign bit. + %tmp.4 = add i65 %tmp.2, %tmp.0 + ret i65 %tmp.4 +} + +define i1024 @test3(i1024 %x) { + %tmp.0 = shl i1024 1, 1023 + %tmp.2 = xor i1024 %x, %tmp.0 + ;; Add of sign bit -> xor of sign bit. + %tmp.4 = add i1024 %tmp.2, %tmp.0 + ret i1024 %tmp.4 +} + +define i128 @test4(i128 %x) { + ;; If we have ADD(XOR(AND(X, 0xFF), 0xF..F80), 0x80), it's a sext. + %tmp.5 = shl i128 1, 127 + %tmp.1 = ashr i128 %tmp.5, 120 + %tmp.2 = xor i128 %x, %tmp.1 + %tmp.4 = add i128 %tmp.2, %tmp.5 + ret i128 %tmp.4 +} + +define i99 @test5(i99 %x) { + ;; If we have ADD(XOR(AND(X, 0xFF), 0x80), 0xF..F80), it's a sext. + %X = and i99 %x, 562949953421311 + %tmp.2 = xor i99 %X, 281474976710656 + %tmp.4 = add i99 %tmp.2, -281474976710656 + ret i99 %tmp.4 +} + +define i77 @test6(i77 %x) { + ;; (x & 254)+1 -> (x & 254)|1 + %tmp.2 = and i77 %x, 562949953421310 + %tmp.4 = add i77 %tmp.2, 1 + ret i77 %tmp.4 +} |