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| author | Sanjay Patel <spatel@rotateright.com> | 2016-10-27 15:02:45 +0000 |
|---|---|---|
| committer | Sanjay Patel <spatel@rotateright.com> | 2016-10-27 15:02:45 +0000 |
| commit | d5b8d64d4b5143a160f291b5f98f40d0fb32003d (patch) | |
| tree | bd40f4d72836ce76c58356f3faebe875046035f6 /llvm/test/Transforms/InstCombine/abs_abs.ll | |
| parent | 807f732ce84dd2f4f253ae4bda4b8a49ef79906a (diff) | |
| download | bcm5719-llvm-d5b8d64d4b5143a160f291b5f98f40d0fb32003d.tar.gz bcm5719-llvm-d5b8d64d4b5143a160f291b5f98f40d0fb32003d.zip | |
[InstCombine] add tests for missing folds of vector abs/nabs/min/max
llvm-svn: 285299
Diffstat (limited to 'llvm/test/Transforms/InstCombine/abs_abs.ll')
| -rw-r--r-- | llvm/test/Transforms/InstCombine/abs_abs.ll | 43 |
1 files changed, 42 insertions, 1 deletions
diff --git a/llvm/test/Transforms/InstCombine/abs_abs.ll b/llvm/test/Transforms/InstCombine/abs_abs.ll index de10fd180a7..10aec3678fb 100644 --- a/llvm/test/Transforms/InstCombine/abs_abs.ll +++ b/llvm/test/Transforms/InstCombine/abs_abs.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; RUN: opt < %s -instcombine -S | FileCheck %s define i32 @abs_abs_x01(i32 %x) { @@ -15,6 +16,26 @@ define i32 @abs_abs_x01(i32 %x) { ; CHECK-NEXT: ret i32 [[SEL]] } +; FIXME - vectors should get the same folds +define <2 x i32> @abs_abs_x01_vec(<2 x i32> %x) { +; CHECK-LABEL: @abs_abs_x01_vec( +; CHECK-NEXT: [[CMP:%.*]] = icmp sgt <2 x i32> %x, <i32 -1, i32 -1> +; CHECK-NEXT: [[SUB:%.*]] = sub nsw <2 x i32> zeroinitializer, %x +; CHECK-NEXT: [[COND:%.*]] = select <2 x i1> [[CMP]], <2 x i32> %x, <2 x i32> [[SUB]] +; CHECK-NEXT: [[CMP1:%.*]] = icmp sgt <2 x i32> [[COND]], <i32 -1, i32 -1> +; CHECK-NEXT: [[SUB16:%.*]] = sub nsw <2 x i32> zeroinitializer, [[COND]] +; CHECK-NEXT: [[COND18:%.*]] = select <2 x i1> [[CMP1]], <2 x i32> [[COND]], <2 x i32> [[SUB16]] +; CHECK-NEXT: ret <2 x i32> [[COND18]] +; + %cmp = icmp sgt <2 x i32> %x, <i32 -1, i32 -1> + %sub = sub nsw <2 x i32> zeroinitializer, %x + %cond = select <2 x i1> %cmp, <2 x i32> %x, <2 x i32> %sub + %cmp1 = icmp sgt <2 x i32> %cond, <i32 -1, i32 -1> + %sub16 = sub nsw <2 x i32> zeroinitializer, %cond + %cond18 = select <2 x i1> %cmp1, <2 x i32> %cond, <2 x i32> %sub16 + ret <2 x i32> %cond18 +} + define i32 @abs_abs_x02(i32 %x) { %cmp = icmp sgt i32 %x, 0 %sub = sub nsw i32 0, %x @@ -60,6 +81,26 @@ define i32 @abs_abs_x04(i32 %x) { ; CHECK-NEXT: ret i32 [[SEL]] } +; FIXME - vectors should get the same folds +define <2 x i32> @abs_abs_x04_vec(<2 x i32> %x) { +; CHECK-LABEL: @abs_abs_x04_vec( +; CHECK-NEXT: [[CMP:%.*]] = icmp slt <2 x i32> %x, <i32 1, i32 1> +; CHECK-NEXT: [[SUB:%.*]] = sub nsw <2 x i32> zeroinitializer, %x +; CHECK-NEXT: [[COND:%.*]] = select <2 x i1> [[CMP]], <2 x i32> [[SUB]], <2 x i32> %x +; CHECK-NEXT: [[CMP1:%.*]] = icmp sgt <2 x i32> [[COND]], <i32 -1, i32 -1> +; CHECK-NEXT: [[SUB16:%.*]] = sub nsw <2 x i32> zeroinitializer, [[COND]] +; CHECK-NEXT: [[COND18:%.*]] = select <2 x i1> [[CMP1]], <2 x i32> [[COND]], <2 x i32> [[SUB16]] +; CHECK-NEXT: ret <2 x i32> [[COND18]] +; + %cmp = icmp slt <2 x i32> %x, <i32 1, i32 1> + %sub = sub nsw <2 x i32> zeroinitializer, %x + %cond = select <2 x i1> %cmp, <2 x i32> %sub, <2 x i32> %x + %cmp1 = icmp sgt <2 x i32> %cond, <i32 -1, i32 -1> + %sub16 = sub nsw <2 x i32> zeroinitializer, %cond + %cond18 = select <2 x i1> %cmp1, <2 x i32> %cond, <2 x i32> %sub16 + ret <2 x i32> %cond18 +} + define i32 @abs_abs_x05(i32 %x) { %cmp = icmp sgt i32 %x, -1 %sub = sub nsw i32 0, %x @@ -958,4 +999,4 @@ define i32 @nabs_abs_x16(i32 %x) { ; CHECK-NEXT: [[NEG:%[a-z0-9]+]] = sub nsw i32 0, %x ; CHECK-NEXT: [[SEL:%[a-z0-9]+]] = select i1 [[CMP]], i32 %x, i32 [[NEG]] ; CHECK-NEXT: ret i32 [[SEL]] -}
\ No newline at end of file +} |
