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author | Sam Parker <sam.parker@arm.com> | 2019-06-06 08:56:26 +0000 |
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committer | Sam Parker <sam.parker@arm.com> | 2019-06-06 08:56:26 +0000 |
commit | 7cc580f5e95e7e5dd84db2c276f58709258cd120 (patch) | |
tree | 767ec67006d21df6b87a8d653494c020711cae17 /llvm/test/Transforms/IndVarSimplify | |
parent | 54eeb3f40ab1f68619083cfce3e0dff2521b7cef (diff) | |
download | bcm5719-llvm-7cc580f5e95e7e5dd84db2c276f58709258cd120.tar.gz bcm5719-llvm-7cc580f5e95e7e5dd84db2c276f58709258cd120.zip |
[SCEV] Use wrap flags in InsertBinop
If the given SCEVExpr has no (un)signed flags attached to it, transfer
these to the resulting instruction or use them to find an existing
instruction.
Differential Revision: https://reviews.llvm.org/D61934
llvm-svn: 362687
Diffstat (limited to 'llvm/test/Transforms/IndVarSimplify')
-rw-r--r-- | llvm/test/Transforms/IndVarSimplify/lftr.ll | 2 | ||||
-rw-r--r-- | llvm/test/Transforms/IndVarSimplify/loop_evaluate_1.ll | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/llvm/test/Transforms/IndVarSimplify/lftr.ll b/llvm/test/Transforms/IndVarSimplify/lftr.ll index ae50f5a33e2..114e4ae8e88 100644 --- a/llvm/test/Transforms/IndVarSimplify/lftr.ll +++ b/llvm/test/Transforms/IndVarSimplify/lftr.ll @@ -202,7 +202,7 @@ define void @test_udiv_as_shift(i8* %a, i8 %n) nounwind uwtable ssp { ; CHECK: loop.preheader: ; CHECK-NEXT: [[TMP0:%.*]] = add i8 [[N]], 3 ; CHECK-NEXT: [[TMP1:%.*]] = lshr i8 [[TMP0]], 2 -; CHECK-NEXT: [[TMP2:%.*]] = add i8 [[TMP1]], 1 +; CHECK-NEXT: [[TMP2:%.*]] = add nuw nsw i8 [[TMP1]], 1 ; CHECK-NEXT: br label [[LOOP:%.*]] ; CHECK: loop: ; CHECK-NEXT: [[I1:%.*]] = phi i8 [ [[I1_INC:%.*]], [[LOOP]] ], [ 0, [[LOOP_PREHEADER]] ] diff --git a/llvm/test/Transforms/IndVarSimplify/loop_evaluate_1.ll b/llvm/test/Transforms/IndVarSimplify/loop_evaluate_1.ll index 5d2c8c7209f..3e2e0451375 100644 --- a/llvm/test/Transforms/IndVarSimplify/loop_evaluate_1.ll +++ b/llvm/test/Transforms/IndVarSimplify/loop_evaluate_1.ll @@ -25,7 +25,7 @@ loopexit: ; preds = %loopentry ; CHECK-LABEL: @test2 ; CHECK: [[VAR1:%.+]] = add i32 %arg, -11 ; CHECK: [[VAR2:%.+]] = lshr i32 [[VAR1]], 1 -; CHECK: [[VAR3:%.+]] = add i32 [[VAR2]], 1 +; CHECK: [[VAR3:%.+]] = add nuw i32 [[VAR2]], 1 ; CHECK: [[VAR4:%.+]] = phi i32 [ 0, %bb ], [ [[VAR3]], %bb1.preheader ] ; CHECK: ret i32 [[VAR4]] define i32 @test2(i32 %arg) { |