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author | Hao Liu <Hao.Liu@arm.com> | 2015-06-08 06:39:56 +0000 |
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committer | Hao Liu <Hao.Liu@arm.com> | 2015-06-08 06:39:56 +0000 |
commit | 32c0539691886d27abd8891641bb496a67f74747 (patch) | |
tree | eb4e17aecea36fcb4bb3d0dda607ca89b1a66088 /llvm/test/Transforms/FunctionAttrs | |
parent | 7d80640f2530140840c4ba0e7d45f424f1c42bd8 (diff) | |
download | bcm5719-llvm-32c0539691886d27abd8891641bb496a67f74747.tar.gz bcm5719-llvm-32c0539691886d27abd8891641bb496a67f74747.zip |
[LoopVectorize] Teach Loop Vectorizor about interleaved memory accesses.
Interleaved memory accesses are grouped and vectorized into vector load/store and shufflevector.
E.g. for (i = 0; i < N; i+=2) {
a = A[i]; // load of even element
b = A[i+1]; // load of odd element
... // operations on a, b, c, d
A[i] = c; // store of even element
A[i+1] = d; // store of odd element
}
The loads of even and odd elements are identified as an interleave load group, which will be transfered into vectorized IRs like:
%wide.vec = load <8 x i32>, <8 x i32>* %ptr
%vec.even = shufflevector <8 x i32> %wide.vec, <8 x i32> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
%vec.odd = shufflevector <8 x i32> %wide.vec, <8 x i32> undef, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
The stores of even and odd elements are identified as an interleave store group, which will be transfered into vectorized IRs like:
%interleaved.vec = shufflevector <4 x i32> %vec.even, %vec.odd, <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7>
store <8 x i32> %interleaved.vec, <8 x i32>* %ptr
This optimization is currently disabled by defaut. To try it by adding '-enable-interleaved-mem-accesses=true'.
llvm-svn: 239291
Diffstat (limited to 'llvm/test/Transforms/FunctionAttrs')
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