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| author | David Blaikie <dblaikie@gmail.com> | 2015-02-27 21:17:42 +0000 |
|---|---|---|
| committer | David Blaikie <dblaikie@gmail.com> | 2015-02-27 21:17:42 +0000 |
| commit | a79ac14fa68297f9888bc70a10df5ed9b8864e38 (patch) | |
| tree | 8d8217a8928e3ee599bdde405e2e178b3a55b645 /llvm/test/Transforms/FunctionAttrs/optnone-simple.ll | |
| parent | 83687fb9e654c9d0086e7f6b728c26fa0b729e71 (diff) | |
| download | bcm5719-llvm-a79ac14fa68297f9888bc70a10df5ed9b8864e38.tar.gz bcm5719-llvm-a79ac14fa68297f9888bc70a10df5ed9b8864e38.zip | |
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction
Essentially the same as the GEP change in r230786.
A similar migration script can be used to update test cases, though a few more
test case improvements/changes were required this time around: (r229269-r229278)
import fileinput
import sys
import re
pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)")
for line in sys.stdin:
sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line))
Reviewers: rafael, dexonsmith, grosser
Differential Revision: http://reviews.llvm.org/D7649
llvm-svn: 230794
Diffstat (limited to 'llvm/test/Transforms/FunctionAttrs/optnone-simple.ll')
| -rw-r--r-- | llvm/test/Transforms/FunctionAttrs/optnone-simple.ll | 24 |
1 files changed, 12 insertions, 12 deletions
diff --git a/llvm/test/Transforms/FunctionAttrs/optnone-simple.ll b/llvm/test/Transforms/FunctionAttrs/optnone-simple.ll index 9d0f8e3710a..beaa588da50 100644 --- a/llvm/test/Transforms/FunctionAttrs/optnone-simple.ll +++ b/llvm/test/Transforms/FunctionAttrs/optnone-simple.ll @@ -15,8 +15,8 @@ entry: %b.addr = alloca i32, align 4 store i32 %a, i32* %a.addr, align 4 store i32 %b, i32* %b.addr, align 4 - %0 = load i32* %a.addr, align 4 - %1 = load i32* %b.addr, align 4 + %0 = load i32, i32* %a.addr, align 4 + %1 = load i32, i32* %b.addr, align 4 %add = add nsw i32 %0, %1 ret i32 %add } @@ -33,8 +33,8 @@ entry: %b.addr = alloca i32, align 4 store i32 %a, i32* %a.addr, align 4 store i32 %b, i32* %b.addr, align 4 - %0 = load i32* %a.addr, align 4 - %1 = load i32* %b.addr, align 4 + %0 = load i32, i32* %a.addr, align 4 + %1 = load i32, i32* %b.addr, align 4 %add = add nsw i32 %0, %1 ret i32 %add } @@ -57,8 +57,8 @@ entry: %b.addr = alloca float, align 4 store float %a, float* %a.addr, align 4 store float %b, float* %b.addr, align 4 - %0 = load float* %a.addr, align 4 - %1 = load float* %b.addr, align 4 + %0 = load float, float* %a.addr, align 4 + %1 = load float, float* %b.addr, align 4 %sub = fsub float %0, %1 ret float %sub } @@ -75,8 +75,8 @@ entry: %b.addr = alloca float, align 4 store float %a, float* %a.addr, align 4 store float %b, float* %b.addr, align 4 - %0 = load float* %a.addr, align 4 - %1 = load float* %b.addr, align 4 + %0 = load float, float* %a.addr, align 4 + %1 = load float, float* %b.addr, align 4 %sub = fsub float %0, %1 ret float %sub } @@ -100,8 +100,8 @@ entry: %b.addr = alloca <4 x float>, align 16 store <4 x float> %a, <4 x float>* %a.addr, align 16 store <4 x float> %b, <4 x float>* %b.addr, align 16 - %0 = load <4 x float>* %a.addr, align 16 - %1 = load <4 x float>* %b.addr, align 16 + %0 = load <4 x float>, <4 x float>* %a.addr, align 16 + %1 = load <4 x float>, <4 x float>* %b.addr, align 16 %mul = fmul <4 x float> %0, %1 ret <4 x float> %mul } @@ -118,8 +118,8 @@ entry: %b.addr = alloca <4 x float>, align 16 store <4 x float> %a, <4 x float>* %a.addr, align 16 store <4 x float> %b, <4 x float>* %b.addr, align 16 - %0 = load <4 x float>* %a.addr, align 16 - %1 = load <4 x float>* %b.addr, align 16 + %0 = load <4 x float>, <4 x float>* %a.addr, align 16 + %1 = load <4 x float>, <4 x float>* %b.addr, align 16 %mul = fmul <4 x float> %0, %1 ret <4 x float> %mul } |
