[CodeGenPrepare] Remove load-based heuristic

Summary:
Both the hardware and LLVM have changed since 2012.
Now, load-based heuristic don't show big differences any more on OoO cores.

There is no notable regressons and improvements on spec2000/2006. (Cortex-A57, Core i5).

Reviewers: spatel, zansari
    
Differential Revision: http://reviews.llvm.org/D16836

llvm-svn: 261809

1 files changed, 2 insertions, 7 deletions

diff --git a/llvm/test/Transforms/CodeGenPrepare/X86/select.ll b/llvm/test/Transforms/CodeGenPrepare/X86/select.ll
index a26938ad5ee..15c0772b144 100644
--- a/llvm/test/Transforms/CodeGenPrepare/X86/select.ll
+++ b/llvm/test/Transforms/CodeGenPrepare/X86/select.ll
@@ -2,8 +2,7 @@
 
 target triple = "x86_64-unknown-unknown"
 
-; Nothing to sink here, but this gets converted to a branch to
-; avoid stalling an out-of-order CPU on a predictable branch.
+; Nothing to sink and convert here.
 
 define i32 @no_sink(double %a, double* %b, i32 %x, i32 %y)  {
 entry:
@@ -15,11 +14,7 @@ entry:
 ; CHECK-LABEL: @no_sink(
 ; CHECK:    %load = load double, double* %b, align 8
 ; CHECK:    %cmp = fcmp olt double %load, %a
-; CHECK:    br i1 %cmp, label %select.end, label %select.false
-; CHECK:  select.false:
-; CHECK:    br label %select.end
-; CHECK:  select.end:
-; CHECK:    %sel = phi i32 [ %x, %entry ], [ %y, %select.false ] 
+; CHECK:    %sel = select i1 %cmp, i32 %x, i32 %y
 ; CHECK:    ret i32 %sel
 }