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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-08-29 01:13:41 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-08-29 01:13:41 +0000 |
| commit | 8ec5c1004265f5da323dfc3b2fe929c0557804c8 (patch) | |
| tree | ed4e7ccdd02a5194fa63028a3e9fcbe4be96cc48 /llvm/test/TableGen | |
| parent | e4a7f0182d4017593504982d72725c6fefa5c903 (diff) | |
| download | bcm5719-llvm-8ec5c1004265f5da323dfc3b2fe929c0557804c8.tar.gz bcm5719-llvm-8ec5c1004265f5da323dfc3b2fe929c0557804c8.zip | |
GlobalISel/TableGen: Handle setcc patterns
This is a special case because one node maps to two different G_
instructions, and the operand order is changed.
This mostly enables G_FCMP for AMDPGPU. G_ICMP is still manually
selected for now since it has the SALU and VALU complication to deal
with.
llvm-svn: 370280
Diffstat (limited to 'llvm/test/TableGen')
| -rw-r--r-- | llvm/test/TableGen/Common/GlobalISelEmitterCommon.td | 1 | ||||
| -rw-r--r-- | llvm/test/TableGen/GlobalISelEmitter-setcc.td | 24 |
2 files changed, 25 insertions, 0 deletions
diff --git a/llvm/test/TableGen/Common/GlobalISelEmitterCommon.td b/llvm/test/TableGen/Common/GlobalISelEmitterCommon.td index 2e3332c1390..f96e0fec760 100644 --- a/llvm/test/TableGen/Common/GlobalISelEmitterCommon.td +++ b/llvm/test/TableGen/Common/GlobalISelEmitterCommon.td @@ -7,6 +7,7 @@ def GPR32 : RegisterClass<"MyTarget", [i32], 32, (add R0)>; def GPR32Op : RegisterOperand<GPR32>; def F0 : Register<"f0"> { let Namespace = "MyTarget"; } def FPR32 : RegisterClass<"MyTarget", [f32], 32, (add F0)>; +def FPR32Op : RegisterOperand<FPR32>; def p0 : PtrValueType <i32, 0>; class I<dag OOps, dag IOps, list<dag> Pat> diff --git a/llvm/test/TableGen/GlobalISelEmitter-setcc.td b/llvm/test/TableGen/GlobalISelEmitter-setcc.td new file mode 100644 index 00000000000..1bad1754f64 --- /dev/null +++ b/llvm/test/TableGen/GlobalISelEmitter-setcc.td @@ -0,0 +1,24 @@ +// RUN: llvm-tblgen -gen-global-isel -warn-on-skipped-patterns -optimize-match-table=false -I %p/../../include -I %p/Common %s -o - 2> %t < %s | FileCheck -check-prefix=GISEL %s +// RUN: FileCheck -DFILE=%s -check-prefix=ERR %s < %t + +include "llvm/Target/Target.td" +include "GlobalISelEmitterCommon.td" + +// GISEL: GIM_Try +// GISEL: GIM_CheckNumOperands, /*MI*/0, /*Expected*/4, +// GISEL-NEXT: GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_FCMP, +// GISEL: GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_OEQ, +def FCMPOEQ : I<(outs GPR32:$dst), (ins FPR32Op:$src0, FPR32:$src1), + [(set GPR32:$dst, (i32 (setcc f32:$src0, f32:$src1, SETOEQ)))]>; + +// GISEL: GIM_Try +// GISEL: GIM_CheckNumOperands, /*MI*/0, /*Expected*/4, +// GISEL-NEXT: GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_ICMP, +// GISEL: GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ, +def ICMPEQ : I<(outs GPR32:$dst), (ins GPR32Op:$src0, GPR32:$src1), + [(set GPR32:$dst, (i32 (setcc i32:$src0, i32:$src1, SETEQ)))]>; + +// Check there is an error if not a CondCode operand. +// ERR: [[FILE]]:[[@LINE+1]]:1: warning: Skipped pattern: Unable to handle CondCode +def FCMP_NOTCC : I<(outs GPR32:$dst), (ins FPR32Op:$src0, FPR32:$src1), + [(set GPR32:$dst, (i32 (setcc f32:$src0, f32:$src1, i32)))]>; |

