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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-09-19 16:26:14 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-09-19 16:26:14 +0000 |
| commit | 3ecab8e4555aee0b4aa10c413696a67f55948c39 (patch) | |
| tree | 312b6fd8b3a9ebc14217e7e19a00d428e3f3f8ff /llvm/test/TableGen | |
| parent | e0900f285bb532790ed494df901f87c5c8b904da (diff) | |
| download | bcm5719-llvm-3ecab8e4555aee0b4aa10c413696a67f55948c39.tar.gz bcm5719-llvm-3ecab8e4555aee0b4aa10c413696a67f55948c39.zip | |
Reapply r372285 "GlobalISel: Don't materialize immarg arguments to intrinsics"
This reverts r372314, reapplying r372285 and the commits which depend
on it (r372286-r372293, and r372296-r372297)
This was missing one switch to getTargetConstant in an untested case.
llvm-svn: 372338
Diffstat (limited to 'llvm/test/TableGen')
| -rw-r--r-- | llvm/test/TableGen/immarg.td | 31 |
1 files changed, 31 insertions, 0 deletions
diff --git a/llvm/test/TableGen/immarg.td b/llvm/test/TableGen/immarg.td new file mode 100644 index 00000000000..407f06c3a40 --- /dev/null +++ b/llvm/test/TableGen/immarg.td @@ -0,0 +1,31 @@ +// RUN: llvm-tblgen -gen-global-isel -optimize-match-table=false -I %p/Common -I %p/../../include %s -o - < %s | FileCheck -check-prefix=GISEL %s + +include "llvm/Target/Target.td" +include "GlobalISelEmitterCommon.td" + +let TargetPrefix = "mytarget" in { +def int_mytarget_sleep0 : Intrinsic<[], [llvm_i32_ty], [ImmArg<0>]>; +def int_mytarget_sleep1 : Intrinsic<[], [llvm_i32_ty], [ImmArg<0>]>; +} + +// GISEL: GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS, +// GISEL-NEXT: // MIs[0] Operand 0 +// GISEL-NEXT: GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::mytarget_sleep0, +// GISEL-NEXT: // MIs[0] src +// GISEL-NEXT: GIM_CheckIsImm, /*MI*/0, /*Op*/1, +// GISEL-NEXT: // (intrinsic_void {{[0-9]+}}:{ *:[iPTR] }, (timm:{ *:[i32] }):$src) => (SLEEP0 (timm:{ *:[i32] }):$src) +// GISEL-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::SLEEP0, +// GISEL-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src +def SLEEP0 : I<(outs), (ins i32imm:$src), + [(int_mytarget_sleep0 timm:$src)] +>; + +// Test for situation which was crashing in ARM patterns. +def p_imm : Operand<i32>; +def SLEEP1 : I<(outs), (ins p_imm:$src), []>; + +// FIXME: This should not crash, but should it work or be an error? +// def : Pat < +// (int_mytarget_sleep1 timm:$src), +// (SLEEP1 imm:$src) +// >; |

