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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-08-15 18:58:25 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-08-15 18:58:25 +0000 |
| commit | 1f2b727298de19a4e6de3fe28886628cec996b9b (patch) | |
| tree | 06f2d75fdc635560d5feb45cf73f65343585cbe5 /llvm/test/TableGen | |
| parent | d202899431e49484d907608dbe74fa6d708bb07b (diff) | |
| download | bcm5719-llvm-1f2b727298de19a4e6de3fe28886628cec996b9b.tar.gz bcm5719-llvm-1f2b727298de19a4e6de3fe28886628cec996b9b.zip | |
MVT: Add v3i16/v3f16 vectors
AMDGPU has some buffer intrinsics which theoretically could use
this. Some of the generated tables include the 3 and 4 element vector
versions of these rounded to 64-bits, which is ambiguous. Add these to
help the table disambiguate these.
Assertion change is for the path odd sized vectors now take for R600.
v3i16 is widened to v4i16, which then needs to be promoted to v4i32.
llvm-svn: 369038
Diffstat (limited to 'llvm/test/TableGen')
| -rw-r--r-- | llvm/test/TableGen/intrinsic-varargs.td | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/test/TableGen/intrinsic-varargs.td b/llvm/test/TableGen/intrinsic-varargs.td index ae0d9062860..05572eda8fd 100644 --- a/llvm/test/TableGen/intrinsic-varargs.td +++ b/llvm/test/TableGen/intrinsic-varargs.td @@ -25,7 +25,7 @@ class Intrinsic<string name, list<LLVMType> param_types = []> { } // isVoid needs to match the definition in ValueTypes.td -def isVoid : ValueType<0, 127>; // Produces no value +def isVoid : ValueType<0, 129>; // Produces no value def llvm_vararg_ty : LLVMType<isVoid>; // this means vararg here // CHECK: /* 0 */ 0, 29, 0, |
