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| author | Chris Lattner <sabre@nondot.org> | 2011-04-15 05:18:47 +0000 |
|---|---|---|
| committer | Chris Lattner <sabre@nondot.org> | 2011-04-15 05:18:47 +0000 |
| commit | 0ab5e2cdedba59b4f81152d72d70e1796f796834 (patch) | |
| tree | 2b0d5d1a27ca9c3a382b2c0ed091fd7aebc857cc /llvm/test/TableGen | |
| parent | b5e3e9dd27dce1b3bb10c4f453cea84a0b35bbca (diff) | |
| download | bcm5719-llvm-0ab5e2cdedba59b4f81152d72d70e1796f796834.tar.gz bcm5719-llvm-0ab5e2cdedba59b4f81152d72d70e1796f796834.zip | |
Fix a ton of comment typos found by codespell. Patch by
Luis Felipe Strano Moraes!
llvm-svn: 129558
Diffstat (limited to 'llvm/test/TableGen')
| -rw-r--r-- | llvm/test/TableGen/TargetInstrInfo.td | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/test/TableGen/TargetInstrInfo.td b/llvm/test/TableGen/TargetInstrInfo.td index 146ef6fd768..6c39d5ce57c 100644 --- a/llvm/test/TableGen/TargetInstrInfo.td +++ b/llvm/test/TableGen/TargetInstrInfo.td @@ -110,7 +110,7 @@ def SHL32rCL : Inst<(ops R32:$dst, R32:$src), [(set R32:$dst, (shl R32:$src, CL))]>; // The RTL list is a list, allowing complex instructions to be defined easily. -// Temporary 'internal' registers can be used to break instructions appart. +// Temporary 'internal' registers can be used to break instructions apart. let isTwoAddress = 1 in def XOR32mi : Inst<(ops addr:$addr, imm32:$imm), "xor $dst, $src2", 0x81, MRM6m, |
