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| author | Nate Begeman <natebegeman@mac.com> | 2004-10-08 02:49:24 +0000 |
|---|---|---|
| committer | Nate Begeman <natebegeman@mac.com> | 2004-10-08 02:49:24 +0000 |
| commit | b58dd6799f4bed89a072d60f2e0cfae478592098 (patch) | |
| tree | e9a50d0bffe1eb6b98917ba09e45caaef8b4a813 /llvm/test/Regression/Transforms/InstCombine/add.ll | |
| parent | 3e0a20ebb8a20649ed075cf13a96a7186a957381 (diff) | |
| download | bcm5719-llvm-b58dd6799f4bed89a072d60f2e0cfae478592098.tar.gz bcm5719-llvm-b58dd6799f4bed89a072d60f2e0cfae478592098.zip | |
Implement logical and with an immediate that consists of a contiguous block
of one or more 1 bits (may wrap from least significant bit to most
significant bit) as the rlwinm rather than andi., andis., or some longer
instructons sequence.
int andn4(int z) { return z & -4; }
int clearhi(int z) { return z & 0x0000FFFF; }
int clearlo(int z) { return z & 0xFFFF0000; }
int clearmid(int z) { return z & 0x00FFFF00; }
int clearwrap(int z) { return z & 0xFF0000FF; }
_andn4:
rlwinm r3, r3, 0, 0, 29
blr
_clearhi:
rlwinm r3, r3, 0, 16, 31
blr
_clearlo:
rlwinm r3, r3, 0, 0, 15
blr
_clearmid:
rlwinm r3, r3, 0, 8, 23
blr
_clearwrap:
rlwinm r3, r3, 0, 24, 7
blr
llvm-svn: 16832
Diffstat (limited to 'llvm/test/Regression/Transforms/InstCombine/add.ll')
0 files changed, 0 insertions, 0 deletions
