[ARMv8] Implement the NEON instructions VRINT{N, X, A, Z, M, P}.

llvm-svn: 186688

4 files changed, 124 insertions, 0 deletions

diff --git a/llvm/test/MC/ARM/neon-v8.s b/llvm/test/MC/ARM/neon-v8.s
index 06a22f7c4fd..429c8e3c087 100644
--- a/llvm/test/MC/ARM/neon-v8.s
+++ b/llvm/test/MC/ARM/neon-v8.s
@@ -44,3 +44,40 @@ vcvtp.s32.f32	q4, q15
 @ CHECK: vcvtp.s32.f32	q4, q15 @ encoding: [0x6e,0x82,0xbb,0xf3]
 vcvtp.u32.f32	q9, q8
 @ CHECK: vcvtp.u32.f32	q9, q8 @ encoding: [0xe0,0x22,0xfb,0xf3]
+
+vrintn.f32 d3, d0
+@ CHECK: vrintn.f32 d3, d0 @ encoding: [0x00,0x34,0xba,0xf3]
+vrintn.f32 q1, q4
+@ CHECK: vrintn.f32 q1, q4 @ encoding: [0x48,0x24,0xba,0xf3]
+vrintx.f32 d5, d12
+@ CHECK: vrintx.f32 d5, d12 @ encoding: [0x8c,0x54,0xba,0xf3]
+vrintx.f32 q0, q3
+@ CHECK: vrintx.f32 q0, q3 @ encoding: [0xc6,0x04,0xba,0xf3]
+vrinta.f32 d3, d0
+@ CHECK: vrinta.f32 d3, d0 @ encoding: [0x00,0x35,0xba,0xf3]
+vrinta.f32 q8, q2
+@ CHECK: vrinta.f32 q8, q2 @ encoding: [0x44,0x05,0xfa,0xf3]
+vrintz.f32 d12, d18
+@ CHECK: vrintz.f32 d12, d18 @ encoding: [0xa2,0xc5,0xba,0xf3]
+vrintz.f32 q9, q4
+@ CHECK: vrintz.f32 q9, q4 @ encoding: [0xc8,0x25,0xfa,0xf3]
+vrintm.f32 d3, d0
+@ CHECK: vrintm.f32 d3, d0 @ encoding: [0x80,0x36,0xba,0xf3]
+vrintm.f32 q1, q4
+@ CHECK: vrintm.f32 q1, q4 @ encoding: [0xc8,0x26,0xba,0xf3]
+vrintp.f32 d3, d0
+@ CHECK: vrintp.f32 d3, d0 @ encoding: [0x80,0x37,0xba,0xf3]
+vrintp.f32 q1, q4
+@ CHECK: vrintp.f32 q1, q4 @ encoding: [0xc8,0x27,0xba,0xf3]
+
+@ test the aliases of vrint
+vrintn.f32.f32 d3, d0
+@ CHECK: vrintn.f32 d3, d0 @ encoding: [0x00,0x34,0xba,0xf3]
+vrintx.f32.f32 q0, q3
+@ CHECK: vrintx.f32 q0, q3 @ encoding: [0xc6,0x04,0xba,0xf3]
+vrinta.f32.f32 d3, d0
+@ CHECK: vrinta.f32 d3, d0 @ encoding: [0x00,0x35,0xba,0xf3]
+vrintz.f32.f32 q9, q4
+@ CHECK: vrintz.f32 q9, q4 @ encoding: [0xc8,0x25,0xfa,0xf3]
+vrintp.f32.f32 q1, q4
+@ CHECK: vrintp.f32 q1, q4 @ encoding: [0xc8,0x27,0xba,0xf3]
diff --git a/llvm/test/MC/ARM/thumb-neon-v8.s b/llvm/test/MC/ARM/thumb-neon-v8.s
index df40238757c..5b327810f85 100644
--- a/llvm/test/MC/ARM/thumb-neon-v8.s
+++ b/llvm/test/MC/ARM/thumb-neon-v8.s
@@ -44,3 +44,40 @@ vcvtp.s32.f32	q4, q15
 @ CHECK: vcvtp.s32.f32	q4, q15 @ encoding: [0xbb,0xff,0x6e,0x82]
 vcvtp.u32.f32	q9, q8
 @ CHECK: vcvtp.u32.f32	q9, q8 @ encoding: [0xfb,0xff,0xe0,0x22]
+
+vrintn.f32 d3, d0
+@ CHECK: vrintn.f32 d3, d0 @ encoding: [0xba,0xff,0x00,0x34]
+vrintn.f32 q1, q4
+@ CHECK: vrintn.f32 q1, q4 @ encoding: [0xba,0xff,0x48,0x24]
+vrintx.f32 d5, d12
+@ CHECK: vrintx.f32 d5, d12 @ encoding: [0xba,0xff,0x8c,0x54]
+vrintx.f32 q0, q3
+@ CHECK: vrintx.f32 q0, q3 @ encoding: [0xba,0xff,0xc6,0x04]
+vrinta.f32 d3, d0
+@ CHECK: vrinta.f32 d3, d0 @ encoding: [0xba,0xff,0x00,0x35]
+vrinta.f32 q8, q2
+@ CHECK: vrinta.f32 q8, q2 @ encoding: [0xfa,0xff,0x44,0x05]
+vrintz.f32 d12, d18
+@ CHECK: vrintz.f32 d12, d18 @ encoding: [0xba,0xff,0xa2,0xc5]
+vrintz.f32 q9, q4
+@ CHECK: vrintz.f32 q9, q4 @ encoding: [0xfa,0xff,0xc8,0x25]
+vrintm.f32 d3, d0
+@ CHECK: vrintm.f32 d3, d0 @ encoding: [0xba,0xff,0x80,0x36]
+vrintm.f32 q1, q4
+@ CHECK: vrintm.f32 q1, q4 @ encoding: [0xba,0xff,0xc8,0x26]
+vrintp.f32 d3, d0
+@ CHECK: vrintp.f32 d3, d0 @ encoding: [0xba,0xff,0x80,0x37]
+vrintp.f32 q1, q4
+@ CHECK: vrintp.f32 q1, q4 @ encoding: [0xba,0xff,0xc8,0x27]
+
+@ test the aliases of vrint
+vrintn.f32.f32 d3, d0
+@ CHECK: vrintn.f32 d3, d0 @ encoding: [0xba,0xff,0x00,0x34]
+vrintx.f32.f32 q0, q3
+@ CHECK: vrintx.f32 q0, q3 @ encoding: [0xba,0xff,0xc6,0x04]
+vrinta.f32.f32 d3, d0
+@ CHECK: vrinta.f32 d3, d0 @ encoding: [0xba,0xff,0x00,0x35]
+vrintz.f32.f32 q9, q4
+@ CHECK: vrintz.f32 q9, q4 @ encoding: [0xfa,0xff,0xc8,0x25]
+vrintp.f32.f32 q1, q4
+@ CHECK: vrintp.f32 q1, q4 @ encoding: [0xba,0xff,0xc8,0x27]
diff --git a/llvm/test/MC/Disassembler/ARM/neon-v8.txt b/llvm/test/MC/Disassembler/ARM/neon-v8.txt
index 4e9bf3f7def..8c6e6898b94 100644
--- a/llvm/test/MC/Disassembler/ARM/neon-v8.txt
+++ b/llvm/test/MC/Disassembler/ARM/neon-v8.txt
@@ -44,3 +44,28 @@
 # CHECK: vcvtp.s32.f32	q4, q15
 0xe0 0x22 0xfb 0xf3
 # CHECK: vcvtp.u32.f32	q9, q8
+
+0x00 0x34 0xba 0xf3
+# CHECK: vrintn.f32 d3, d0
+0x48 0x24 0xba 0xf3
+# CHECK: vrintn.f32 q1, q4
+0x8c 0x54 0xba 0xf3
+# CHECK: vrintx.f32 d5, d12
+0xc6 0x04 0xba 0xf3
+# CHECK: vrintx.f32 q0, q3
+0x00 0x35 0xba 0xf3
+# CHECK: vrinta.f32 d3, d0
+0x44 0x05 0xfa 0xf3
+# CHECK: vrinta.f32 q8, q2
+0xa2 0xc5 0xba 0xf3
+# CHECK: vrintz.f32 d12, d18
+0xc8 0x25 0xfa 0xf3
+# CHECK: vrintz.f32 q9, q4
+0x80 0x36 0xba 0xf3
+# CHECK: vrintm.f32 d3, d0
+0xc8 0x26 0xba 0xf3
+# CHECK: vrintm.f32 q1, q4
+0x80 0x37 0xba 0xf3
+# CHECK: vrintp.f32 d3, d0
+0xc8 0x27 0xba 0xf3
+# CHECK: vrintp.f32 q1, q4
diff --git a/llvm/test/MC/Disassembler/ARM/thumb-neon-v8.txt b/llvm/test/MC/Disassembler/ARM/thumb-neon-v8.txt
index f025b8b2ab8..27c09ea0f82 100644
--- a/llvm/test/MC/Disassembler/ARM/thumb-neon-v8.txt
+++ b/llvm/test/MC/Disassembler/ARM/thumb-neon-v8.txt
@@ -44,3 +44,28 @@
 # CHECK: vcvtp.s32.f32	q4, q15
 0xfb 0xff 0xe0 0x22
 # CHECK: vcvtp.u32.f32	q9, q8
+
+0xba 0xff 0x00 0x34
+# CHECK: vrintn.f32 d3, d0
+0xba 0xff 0x48 0x24
+# CHECK: vrintn.f32 q1, q4
+0xba 0xff 0x8c 0x54
+# CHECK: vrintx.f32 d5, d12
+0xba 0xff 0xc6 0x04
+# CHECK: vrintx.f32 q0, q3
+0xba 0xff 0x00 0x35
+# CHECK: vrinta.f32 d3, d0
+0xfa 0xff 0x44 0x05
+# CHECK: vrinta.f32 q8, q2
+0xba 0xff 0xa2 0xc5
+# CHECK: vrintz.f32 d12, d18
+0xfa 0xff 0xc8 0x25
+# CHECK: vrintz.f32 q9, q4
+0xba 0xff 0x80 0x36
+# CHECK: vrintm.f32 d3, d0
+0xba 0xff 0xc8 0x26
+# CHECK: vrintm.f32 q1, q4
+0xba 0xff 0x80 0x37
+# CHECK: vrintp.f32 d3, d0
+0xba 0xff 0xc8 0x27
+# CHECK: vrintp.f32 q1, q4