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| author | Tim Northover <tnorthover@apple.com> | 2014-05-24 12:42:26 +0000 |
|---|---|---|
| committer | Tim Northover <tnorthover@apple.com> | 2014-05-24 12:42:26 +0000 |
| commit | cc08e1fe1b3feef12a1eba31f8afcc3bbefc733e (patch) | |
| tree | 944d86a337d00e62dbc49d2ff0aad7925472afa7 /llvm/test/MC | |
| parent | f6ee78cfb7869dba4f797cbc0573bf02beac7810 (diff) | |
| download | bcm5719-llvm-cc08e1fe1b3feef12a1eba31f8afcc3bbefc733e.tar.gz bcm5719-llvm-cc08e1fe1b3feef12a1eba31f8afcc3bbefc733e.zip | |
AArch64/ARM64: remove AArch64 from tree prior to renaming ARM64.
I'm doing this in two phases for a better "git blame" record. This
commit removes the previous AArch64 backend and redirects all
functionality to ARM64. It also deduplicates test-lines and removes
orphaned AArch64 tests.
The next step will be "git mv ARM64 AArch64" and rewire most of the
tests.
Hopefully LLVM is still functional, though it would be even better if
no-one ever had to care because the rename happens straight
afterwards.
llvm-svn: 209576
Diffstat (limited to 'llvm/test/MC')
84 files changed, 4 insertions, 724 deletions
diff --git a/llvm/test/MC/AArch64/adrp-relocation.s b/llvm/test/MC/AArch64/adrp-relocation.s index 6c7fbf5b872..03b930d5397 100644 --- a/llvm/test/MC/AArch64/adrp-relocation.s +++ b/llvm/test/MC/AArch64/adrp-relocation.s @@ -1,4 +1,3 @@ -// RUN: llvm-mc -triple=aarch64-linux-gnu -filetype=obj -o - %s| llvm-readobj -r - | FileCheck %s // RUN: llvm-mc -triple=arm64-linux-gnu -filetype=obj -o - %s| llvm-readobj -r - | FileCheck %s .text // These should produce an ADRP/ADD pair to calculate the address of diff --git a/llvm/test/MC/AArch64/basic-a64-diagnostics.s b/llvm/test/MC/AArch64/basic-a64-diagnostics.s index 213dc00f0a6..c6cb6b01f8a 100644 --- a/llvm/test/MC/AArch64/basic-a64-diagnostics.s +++ b/llvm/test/MC/AArch64/basic-a64-diagnostics.s @@ -1,5 +1,3 @@ -// RUN: not llvm-mc -triple aarch64-none-linux-gnu < %s 2> %t -// RUN: FileCheck --check-prefix=CHECK-ERROR --check-prefix=CHECK-ERROR-AARCH64 < %t %s // RUN: not llvm-mc -triple arm64-none-linux-gnu < %s 2> %t // RUN: FileCheck --check-prefix=CHECK-ERROR --check-prefix=CHECK-ERROR-ARM64 < %t %s diff --git a/llvm/test/MC/AArch64/basic-a64-instructions.s b/llvm/test/MC/AArch64/basic-a64-instructions.s index 9a4ec81aae9..72156bc9c51 100644 --- a/llvm/test/MC/AArch64/basic-a64-instructions.s +++ b/llvm/test/MC/AArch64/basic-a64-instructions.s @@ -1,4 +1,3 @@ -// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+fp-armv8 < %s | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-AARCH64 // RUN: llvm-mc -triple arm64-none-linux-gnu -show-encoding -mattr=+fp-armv8 < %s | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-ARM64 .globl _func @@ -128,7 +127,6 @@ _func: // CHECK: adds w19, w17, w1, uxtx // encoding: [0x33,0x62,0x21,0x2b] // CHECK: adds w2, w5, w1, sxtb #1 // encoding: [0xa2,0x84,0x21,0x2b] // CHECK: adds w26, wsp, w19, sxth // encoding: [0xfa,0xa3,0x33,0x2b] -// CHECK-AARCH64: adds wzr, w2, w3, sxtw // encoding: [0x5f,0xc0,0x23,0x2b] // CHECK-ARM64: cmn w2, w3, sxtw // encoding: [0x5f,0xc0,0x23,0x2b] // CHECK: adds w2, w3, w5, sxtx // encoding: [0x62,0xe0,0x25,0x2b] @@ -257,7 +255,6 @@ _func: // CHECK: sub sp, x3, x7, lsl #4 // encoding: [0x7f,0x70,0x27,0xcb] // CHECK: add w2, wsp, w3, lsl #1 // encoding: [0xe2,0x47,0x23,0x0b] // CHECK: cmp wsp, w9 // encoding: [0xff,0x43,0x29,0x6b] -// CHECK-AARCH64: adds wzr, wsp, w3, lsl #4 // encoding: [0xff,0x53,0x23,0x2b] // CHECK-ARM64: cmn wsp, w3, lsl #4 // encoding: [0xff,0x53,0x23,0x2b] // CHECK: subs x3, sp, x9, lsl #2 // encoding: [0xe3,0x6b,0x29,0xeb] @@ -352,8 +349,6 @@ _func: // A relocation check (default to lo12, which is the only sane relocation anyway really) add x0, x4, #:lo12:var -// CHECK-AARCH64: add x0, x4, #:lo12:var // encoding: [0x80'A',A,A,0x91'A'] -// CHECK-AARCH64: // fixup A - offset: 0, value: :lo12:var, kind: fixup_a64_add_lo12 // CHECK-ARM64: add x0, x4, :lo12:var // encoding: [0x80,0bAAAAAA00,0b00AAAAAA,0x91] // CHECK-ARM64: // fixup A - offset: 0, value: :lo12:var, kind: fixup_arm64_add_imm12 @@ -489,7 +484,6 @@ _func: sub w4, w6, wzr // CHECK: sub w3, w5, w7 // encoding: [0xa3,0x00,0x07,0x4b] // CHECK: sub wzr, w3, w5 // encoding: [0x7f,0x00,0x05,0x4b] -// CHECK-AARCH64: sub w20, wzr, w4 // encoding: [0xf4,0x03,0x04,0x4b] // CHECK-ARM64: neg w20, w4 // encoding: [0xf4,0x03,0x04,0x4b] // CHECK: sub w4, w6, wzr // encoding: [0xc4,0x00,0x1f,0x4b] @@ -520,7 +514,6 @@ _func: sub x4, x6, xzr // CHECK: sub x3, x5, x7 // encoding: [0xa3,0x00,0x07,0xcb] // CHECK: sub xzr, x3, x5 // encoding: [0x7f,0x00,0x05,0xcb] -// CHECK-AARCH64: sub x20, xzr, x4 // encoding: [0xf4,0x03,0x04,0xcb] // CHECK-ARM64: neg x20, x4 // encoding: [0xf4,0x03,0x04,0xcb] // CHECK: sub x4, x6, xzr // encoding: [0xc4,0x00,0x1f,0xcb] @@ -551,7 +544,6 @@ _func: subs w4, w6, wzr // CHECK: subs w3, w5, w7 // encoding: [0xa3,0x00,0x07,0x6b] // CHECK: {{subs wzr,|cmp}} w3, w5 // encoding: [0x7f,0x00,0x05,0x6b] -// CHECK-AARCH64: subs w20, wzr, w4 // encoding: [0xf4,0x03,0x04,0x6b] // CHECK-ARM64: negs w20, w4 // encoding: [0xf4,0x03,0x04,0x6b] // CHECK: subs w4, w6, wzr // encoding: [0xc4,0x00,0x1f,0x6b] @@ -582,7 +574,6 @@ _func: subs x4, x6, xzr // CHECK: subs x3, x5, x7 // encoding: [0xa3,0x00,0x07,0xeb] // CHECK: {{subs xzr,|cmp}} x3, x5 // encoding: [0x7f,0x00,0x05,0xeb] -// CHECK-AARCH64: subs x20, xzr, x4 // encoding: [0xf4,0x03,0x04,0xeb] // CHECK-ARM64: negs x20, x4 // encoding: [0xf4,0x03,0x04,0xeb] // CHECK: subs x4, x6, xzr // encoding: [0xc4,0x00,0x1f,0xeb] @@ -722,9 +713,6 @@ _func: neg w29, w30 neg w30, wzr neg wzr, w0 -// CHECK-AARCH64: sub w29, wzr, w30 // encoding: [0xfd,0x03,0x1e,0x4b] -// CHECK-AARCH64: sub w30, wzr, wzr // encoding: [0xfe,0x03,0x1f,0x4b] -// CHECK-AARCH64: sub wzr, wzr, w0 // encoding: [0xff,0x03,0x00,0x4b] // CHECK-ARM64: neg w29, w30 // encoding: [0xfd,0x03,0x1e,0x4b] // CHECK-ARM64: neg w30, wzr // encoding: [0xfe,0x03,0x1f,0x4b] // CHECK-ARM64: neg wzr, w0 // encoding: [0xff,0x03,0x00,0x4b] @@ -732,9 +720,6 @@ _func: neg w28, w27, lsl #0 neg w26, w25, lsl #29 neg w24, w23, lsl #31 -// CHECK-AARCH64: sub w28, wzr, w27 // encoding: [0xfc,0x03,0x1b,0x4b] -// CHECK-AARCH64: neg w26, w25, lsl #29 // encoding: [0xfa,0x77,0x19,0x4b] -// CHECK-AARCH64: neg w24, w23, lsl #31 // encoding: [0xf8,0x7f,0x17,0x4b] // CHECK-ARM64: neg w28, w27 // encoding: [0xfc,0x03,0x1b,0x4b] // CHECK-ARM64: neg w26, w25, lsl #29 // encoding: [0xfa,0x77,0x19,0x4b] @@ -757,9 +742,6 @@ _func: neg x29, x30 neg x30, xzr neg xzr, x0 -// CHECK-AARCH64: sub x29, xzr, x30 // encoding: [0xfd,0x03,0x1e,0xcb] -// CHECK-AARCH64: sub x30, xzr, xzr // encoding: [0xfe,0x03,0x1f,0xcb] -// CHECK-AARCH64: sub xzr, xzr, x0 // encoding: [0xff,0x03,0x00,0xcb] // CHECK-ARM64: neg x29, x30 // encoding: [0xfd,0x03,0x1e,0xcb] // CHECK-ARM64: neg x30, xzr // encoding: [0xfe,0x03,0x1f,0xcb] // CHECK-ARM64: neg xzr, x0 // encoding: [0xff,0x03,0x00,0xcb] @@ -767,9 +749,6 @@ _func: neg x28, x27, lsl #0 neg x26, x25, lsl #29 neg x24, x23, lsl #31 -// CHECK-AARCH64: sub x28, xzr, x27 // encoding: [0xfc,0x03,0x1b,0xcb] -// CHECK-AARCH64: neg x26, x25, lsl #29 // encoding: [0xfa,0x77,0x19,0xcb] -// CHECK-AARCH64: neg x24, x23, lsl #31 // encoding: [0xf8,0x7f,0x17,0xcb] // CHECK-ARM64: neg x28, x27 // encoding: [0xfc,0x03,0x1b,0xcb] // CHECK-ARM64: neg x26, x25, lsl #29 // encoding: [0xfa,0x77,0x19,0xcb] @@ -792,9 +771,6 @@ _func: negs w29, w30 negs w30, wzr negs wzr, w0 -// CHECK-AARCH64: subs w29, wzr, w30 // encoding: [0xfd,0x03,0x1e,0x6b] -// CHECK-AARCH64: subs w30, wzr, wzr // encoding: [0xfe,0x03,0x1f,0x6b] -// CHECK-AARCH64: subs wzr, wzr, w0 // encoding: [0xff,0x03,0x00,0x6b] // CHECK-ARM64: negs w29, w30 // encoding: [0xfd,0x03,0x1e,0x6b] // CHECK-ARM64: negs w30, wzr // encoding: [0xfe,0x03,0x1f,0x6b] // CHECK-ARM64: cmp wzr, w0 // encoding: [0xff,0x03,0x00,0x6b] @@ -802,9 +778,6 @@ _func: negs w28, w27, lsl #0 negs w26, w25, lsl #29 negs w24, w23, lsl #31 -// CHECK-AARCH64: subs w28, wzr, w27 // encoding: [0xfc,0x03,0x1b,0x6b] -// CHECK-AARCH64: negs w26, w25, lsl #29 // encoding: [0xfa,0x77,0x19,0x6b] -// CHECK-AARCH64: negs w24, w23, lsl #31 // encoding: [0xf8,0x7f,0x17,0x6b] // CHECK-ARM64: negs w28, w27 // encoding: [0xfc,0x03,0x1b,0x6b] // CHECK-ARM64: negs w26, w25, lsl #29 // encoding: [0xfa,0x77,0x19,0x6b] @@ -827,9 +800,6 @@ _func: negs x29, x30 negs x30, xzr negs xzr, x0 -// CHECK-AARCH64: subs x29, xzr, x30 // encoding: [0xfd,0x03,0x1e,0xeb] -// CHECK-AARCH64: subs x30, xzr, xzr // encoding: [0xfe,0x03,0x1f,0xeb] -// CHECK-AARCH64: subs xzr, xzr, x0 // encoding: [0xff,0x03,0x00,0xeb] // CHECK-ARM64: negs x29, x30 // encoding: [0xfd,0x03,0x1e,0xeb] // CHECK-ARM64: negs x30, xzr // encoding: [0xfe,0x03,0x1f,0xeb] // CHECK-ARM64: cmp xzr, x0 // encoding: [0xff,0x03,0x00,0xeb] @@ -837,9 +807,6 @@ _func: negs x28, x27, lsl #0 negs x26, x25, lsl #29 negs x24, x23, lsl #31 -// CHECK-AARCH64: subs x28, xzr, x27 // encoding: [0xfc,0x03,0x1b,0xeb] -// CHECK-AARCH64: negs x26, x25, lsl #29 // encoding: [0xfa,0x77,0x19,0xeb] -// CHECK-AARCH64: negs x24, x23, lsl #31 // encoding: [0xf8,0x7f,0x17,0xeb] // CHECK-ARM64: negs x28, x27 // encoding: [0xfc,0x03,0x1b,0xeb] // CHECK-ARM64: negs x26, x25, lsl #29 // encoding: [0xfa,0x77,0x19,0xeb] @@ -970,10 +937,6 @@ _func: sbfm x3, x4, #63, #63 sbfm wzr, wzr, #31, #31 sbfm w12, w9, #0, #0 -// CHECK-AARCH64: sbfm x1, x2, #3, #4 // encoding: [0x41,0x10,0x43,0x93] -// CHECK-AARCH64: sbfm x3, x4, #63, #63 // encoding: [0x83,0xfc,0x7f,0x93] -// CHECK-AARCH64: sbfm wzr, wzr, #31, #31 // encoding: [0xff,0x7f,0x1f,0x13] -// CHECK-AARCH64: sbfm w12, w9, #0, #0 // encoding: [0x2c,0x01,0x00,0x13] // CHECK-ARM64: sbfx x1, x2, #3, #2 // encoding: [0x41,0x10,0x43,0x93] // CHECK-ARM64: asr x3, x4, #63 // encoding: [0x83,0xfc,0x7f,0x93] @@ -984,10 +947,6 @@ _func: ubfm xzr, x4, #0, #0 ubfm x4, xzr, #63, #5 ubfm x5, x6, #12, #63 -// CHECK-AARCH64: ubfm x4, x5, #12, #10 // encoding: [0xa4,0x28,0x4c,0xd3] -// CHECK-AARCH64: ubfm xzr, x4, #0, #0 // encoding: [0x9f,0x00,0x40,0xd3] -// CHECK-AARCH64: ubfm x4, xzr, #63, #5 // encoding: [0xe4,0x17,0x7f,0xd3] -// CHECK-AARCH64: ubfm x5, x6, #12, #63 // encoding: [0xc5,0xfc,0x4c,0xd3] // CHECK-ARM64: ubfiz x4, x5, #52, #11 // encoding: [0xa4,0x28,0x4c,0xd3] // CHECK-ARM64: ubfx xzr, x4, #0, #1 // encoding: [0x9f,0x00,0x40,0xd3] // CHECK-ARM64: ubfiz x4, xzr, #1, #6 // encoding: [0xe4,0x17,0x7f,0xd3] @@ -997,10 +956,6 @@ _func: bfm xzr, x4, #0, #0 bfm x4, xzr, #63, #5 bfm x5, x6, #12, #63 -// CHECK-AARCH64: bfm x4, x5, #12, #10 // encoding: [0xa4,0x28,0x4c,0xb3] -// CHECK-AARCH64: bfm xzr, x4, #0, #0 // encoding: [0x9f,0x00,0x40,0xb3] -// CHECK-AARCH64: bfm x4, xzr, #63, #5 // encoding: [0xe4,0x17,0x7f,0xb3] -// CHECK-AARCH64: bfm x5, x6, #12, #63 // encoding: [0xc5,0xfc,0x4c,0xb3] // CHECK-ARM64: bfi x4, x5, #52, #11 // encoding: [0xa4,0x28,0x4c,0xb3] // CHECK-ARM64: bfxil xzr, x4, #0, #1 // encoding: [0x9f,0x00,0x40,0xb3] // CHECK-ARM64: bfi x4, xzr, #1, #6 // encoding: [0xe4,0x17,0x7f,0xb3] @@ -1063,10 +1018,8 @@ _func: sbfiz xzr, xzr, #10, #11 // CHECK: {{sbfiz|sbfx}} w9, w10, #0, #1 // encoding: [0x49,0x01,0x00,0x13] // CHECK: sbfiz x2, x3, #63, #1 // encoding: [0x62,0x00,0x41,0x93] -// CHECK-AARCH64: sbfiz x19, x20, #0, #64 // encoding: [0x93,0xfe,0x40,0x93] // CHECK-ARM64: asr x19, x20, #0 // encoding: [0x93,0xfe,0x40,0x93] // CHECK: sbfiz x9, x10, #5, #59 // encoding: [0x49,0xe9,0x7b,0x93] -// CHECK-AARCH64: sbfiz w9, w10, #0, #32 // encoding: [0x49,0x7d,0x00,0x13] // CHECK-ARM64: asr w9, w10, #0 // encoding: [0x49,0x7d,0x00,0x13] // CHECK: sbfiz w11, w12, #31, #1 // encoding: [0x8b,0x01,0x01,0x13] // CHECK: sbfiz w13, w14, #29, #3 // encoding: [0xcd,0x09,0x03,0x13] @@ -1081,17 +1034,11 @@ _func: sbfx w13, w14, #29, #3 sbfx xzr, xzr, #10, #11 // CHECK: sbfx w9, w10, #0, #1 // encoding: [0x49,0x01,0x00,0x13] -// CHECK-AARCH64: sbfx x2, x3, #63, #1 // encoding: [0x62,0xfc,0x7f,0x93] // CHECK-ARM64: asr x2, x3, #63 // encoding: [0x62,0xfc,0x7f,0x93] -// CHECK-AARCH64: sbfx x19, x20, #0, #64 // encoding: [0x93,0xfe,0x40,0x93] // CHECK-ARM64: asr x19, x20, #0 // encoding: [0x93,0xfe,0x40,0x93] -// CHECK-AARCH64: sbfx x9, x10, #5, #59 // encoding: [0x49,0xfd,0x45,0x93] // CHECK-ARM64: asr x9, x10, #5 // encoding: [0x49,0xfd,0x45,0x93] -// CHECK-AARCH64: sbfx w9, w10, #0, #32 // encoding: [0x49,0x7d,0x00,0x13] // CHECK-ARM64: asr w9, w10, #0 // encoding: [0x49,0x7d,0x00,0x13] -// CHECK-AARCH64: sbfx w11, w12, #31, #1 // encoding: [0x8b,0x7d,0x1f,0x13] // CHECK-ARM64: asr w11, w12, #31 // encoding: [0x8b,0x7d,0x1f,0x13] -// CHECK-AARCH64: sbfx w13, w14, #29, #3 // encoding: [0xcd,0x7d,0x1d,0x13] // CHECK-ARM64: asr w13, w14, #29 // encoding: [0xcd,0x7d,0x1d,0x13] // CHECK: sbfx xzr, xzr, #10, #11 // encoding: [0xff,0x53,0x4a,0x93] @@ -1103,14 +1050,6 @@ _func: bfi w11, w12, #31, #1 bfi w13, w14, #29, #3 bfi xzr, xzr, #10, #11 -// CHECK-AARCH64: bfi w9, w10, #0, #1 // encoding: [0x49,0x01,0x00,0x33] -// CHECK-AARCH64: bfi x2, x3, #63, #1 // encoding: [0x62,0x00,0x41,0xb3] -// CHECK-AARCH64: bfi x19, x20, #0, #64 // encoding: [0x93,0xfe,0x40,0xb3] -// CHECK-AARCH64: bfi x9, x10, #5, #59 // encoding: [0x49,0xe9,0x7b,0xb3] -// CHECK-AARCH64: bfi w9, w10, #0, #32 // encoding: [0x49,0x7d,0x00,0x33] -// CHECK-AARCH64: bfi w11, w12, #31, #1 // encoding: [0x8b,0x01,0x01,0x33] -// CHECK-AARCH64: bfi w13, w14, #29, #3 // encoding: [0xcd,0x09,0x03,0x33] -// CHECK-AARCH64: bfi xzr, xzr, #10, #11 // encoding: [0xff,0x2b,0x76,0xb3] // CHECK-ARM64: bfxil w9, w10, #0, #1 // encoding: [0x49,0x01,0x00,0x33] // CHECK-ARM64: bfi x2, x3, #63, #1 // encoding: [0x62,0x00,0x41,0xb3] @@ -1146,14 +1085,6 @@ _func: ubfiz w11, w12, #31, #1 ubfiz w13, w14, #29, #3 ubfiz xzr, xzr, #10, #11 -// CHECK-AARCH64: ubfiz w9, w10, #0, #1 // encoding: [0x49,0x01,0x00,0x53] -// CHECK-AARCH64: ubfiz x2, x3, #63, #1 // encoding: [0x62,0x00,0x41,0xd3] -// CHECK-AARCH64: ubfiz x19, x20, #0, #64 // encoding: [0x93,0xfe,0x40,0xd3] -// CHECK-AARCH64: ubfiz x9, x10, #5, #59 // encoding: [0x49,0xe9,0x7b,0xd3] -// CHECK-AARCH64: ubfiz w9, w10, #0, #32 // encoding: [0x49,0x7d,0x00,0x53] -// CHECK-AARCH64: ubfiz w11, w12, #31, #1 // encoding: [0x8b,0x01,0x01,0x53] -// CHECK-AARCH64: ubfiz w13, w14, #29, #3 // encoding: [0xcd,0x09,0x03,0x53] -// CHECK-AARCH64: ubfiz xzr, xzr, #10, #11 // encoding: [0xff,0x2b,0x76,0xd3] // CHECK-ARM64: ubfx w9, w10, #0, #1 // encoding: [0x49,0x01,0x00,0x53] // CHECK-ARM64: lsl x2, x3, #63 // encoding: [0x62,0x00,0x41,0xd3] @@ -1172,14 +1103,6 @@ _func: ubfx w11, w12, #31, #1 ubfx w13, w14, #29, #3 ubfx xzr, xzr, #10, #11 -// CHECK-AARCH64: ubfx w9, w10, #0, #1 // encoding: [0x49,0x01,0x00,0x53] -// CHECK-AARCH64: ubfx x2, x3, #63, #1 // encoding: [0x62,0xfc,0x7f,0xd3] -// CHECK-AARCH64: ubfx x19, x20, #0, #64 // encoding: [0x93,0xfe,0x40,0xd3] -// CHECK-AARCH64: ubfx x9, x10, #5, #59 // encoding: [0x49,0xfd,0x45,0xd3] -// CHECK-AARCH64: ubfx w9, w10, #0, #32 // encoding: [0x49,0x7d,0x00,0x53] -// CHECK-AARCH64: ubfx w11, w12, #31, #1 // encoding: [0x8b,0x7d,0x1f,0x53] -// CHECK-AARCH64: ubfx w13, w14, #29, #3 // encoding: [0xcd,0x7d,0x1d,0x53] -// CHECK-AARCH64: ubfx xzr, xzr, #10, #11 // encoding: [0xff,0x53,0x4a,0xd3] // CHECK-ARM64: ubfx w9, w10, #0, #1 // encoding: [0x49,0x01,0x00,0x53] // CHECK-ARM64: lsr x2, x3, #63 // encoding: [0x62,0xfc,0x7f,0xd3] @@ -1197,14 +1120,6 @@ _func: cbz x5, lbl cbnz x2, lbl cbnz x26, lbl -// CHECK-AARCH64: cbz w5, lbl // encoding: [0x05'A',A,A,0x34'A'] -// CHECK-AARCH64: // fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr -// CHECK-AARCH64: cbz x5, lbl // encoding: [0x05'A',A,A,0xb4'A'] -// CHECK-AARCH64: // fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr -// CHECK-AARCH64: cbnz x2, lbl // encoding: [0x02'A',A,A,0xb5'A'] -// CHECK-AARCH64: // fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr -// CHECK-AARCH64: cbnz x26, lbl // encoding: [0x1a'A',A,A,0xb5'A'] -// CHECK-AARCH64: // fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr // CHECK-ARM64: cbz w5, lbl // encoding: [0bAAA00101,A,A,0x34] // CHECK-ARM64: // fixup A - offset: 0, value: lbl, kind: fixup_arm64_pcrel_branch19 // CHECK-ARM64: cbz x5, lbl // encoding: [0bAAA00101,A,A,0xb4] @@ -1216,10 +1131,6 @@ _func: cbz wzr, lbl cbnz xzr, lbl -// CHECK-AARCH64: cbz wzr, lbl // encoding: [0x1f'A',A,A,0x34'A'] -// CHECK-AARCH64: // fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr -// CHECK-AARCH64: cbnz xzr, lbl // encoding: [0x1f'A',A,A,0xb5'A'] -// CHECK-AARCH64: // fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr // CHECK-ARM64: cbz wzr, lbl // encoding: [0bAAA11111,A,A,0x34] // CHECK-ARM64: // fixup A - offset: 0, value: lbl, kind: fixup_arm64_pcrel_branch19 @@ -1256,40 +1167,6 @@ _func: b.gt lbl b.le lbl b.al lbl -// CHECK-AARCH64: b.eq lbl // encoding: [A,A,A,0x54'A'] -// CHECK-AARCH64: // fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr -// CHECK-AARCH64: b.ne lbl // encoding: [0x01'A',A,A,0x54'A'] -// CHECK-AARCH64: // fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr -// CHECK-AARCH64: b.hs lbl // encoding: [0x02'A',A,A,0x54'A'] -// CHECK-AARCH64: // fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr -// CHECK-AARCH64: b.hs lbl // encoding: [0x02'A',A,A,0x54'A'] -// CHECK-AARCH64: // fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr -// CHECK-AARCH64: b.lo lbl // encoding: [0x03'A',A,A,0x54'A'] -// CHECK-AARCH64: // fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr -// CHECK-AARCH64: b.lo lbl // encoding: [0x03'A',A,A,0x54'A'] -// CHECK-AARCH64: // fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr -// CHECK-AARCH64: b.mi lbl // encoding: [0x04'A',A,A,0x54'A'] -// CHECK-AARCH64: // fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr -// CHECK-AARCH64: b.pl lbl // encoding: [0x05'A',A,A,0x54'A'] -// CHECK-AARCH64: // fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr -// CHECK-AARCH64: b.vs lbl // encoding: [0x06'A',A,A,0x54'A'] -// CHECK-AARCH64: // fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr -// CHECK-AARCH64: b.vc lbl // encoding: [0x07'A',A,A,0x54'A'] -// CHECK-AARCH64: // fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr -// CHECK-AARCH64: b.hi lbl // encoding: [0x08'A',A,A,0x54'A'] -// CHECK-AARCH64: // fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr -// CHECK-AARCH64: b.ls lbl // encoding: [0x09'A',A,A,0x54'A'] -// CHECK-AARCH64: // fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr -// CHECK-AARCH64: b.ge lbl // encoding: [0x0a'A',A,A,0x54'A'] -// CHECK-AARCH64: // fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr -// CHECK-AARCH64: b.lt lbl // encoding: [0x0b'A',A,A,0x54'A'] -// CHECK-AARCH64: // fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr -// CHECK-AARCH64: b.gt lbl // encoding: [0x0c'A',A,A,0x54'A'] -// CHECK-AARCH64: // fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr -// CHECK-AARCH64: b.le lbl // encoding: [0x0d'A',A,A,0x54'A'] -// CHECK-AARCH64: // fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr -// CHECK-AARCH64: b.al lbl // encoding: [0x0e'A',A,A,0x54'A'] -// CHECK-AARCH64: // fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr // CHECK-ARM64: b.eq lbl // encoding: [0bAAA00000,A,A,0x54] // CHECK-ARM64: // fixup A - offset: 0, value: lbl, kind: fixup_arm64_pcrel_branch19 @@ -1344,40 +1221,6 @@ _func: bgt lbl ble lbl bal lbl -// CHECK-AARCH64: b.eq lbl // encoding: [A,A,A,0x54'A'] -// CHECK-AARCH64: // fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr -// CHECK-AARCH64: b.ne lbl // encoding: [0x01'A',A,A,0x54'A'] -// CHECK-AARCH64: // fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr -// CHECK-AARCH64: b.hs lbl // encoding: [0x02'A',A,A,0x54'A'] -// CHECK-AARCH64: // fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr -// CHECK-AARCH64: b.hs lbl // encoding: [0x02'A',A,A,0x54'A'] -// CHECK-AARCH64: // fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr -// CHECK-AARCH64: b.lo lbl // encoding: [0x03'A',A,A,0x54'A'] -// CHECK-AARCH64: // fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr -// CHECK-AARCH64: b.lo lbl // encoding: [0x03'A',A,A,0x54'A'] -// CHECK-AARCH64: // fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr -// CHECK-AARCH64: b.mi lbl // encoding: [0x04'A',A,A,0x54'A'] -// CHECK-AARCH64: // fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr -// CHECK-AARCH64: b.pl lbl // encoding: [0x05'A',A,A,0x54'A'] -// CHECK-AARCH64: // fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr -// CHECK-AARCH64: b.vs lbl // encoding: [0x06'A',A,A,0x54'A'] -// CHECK-AARCH64: // fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr -// CHECK-AARCH64: b.vc lbl // encoding: [0x07'A',A,A,0x54'A'] -// CHECK-AARCH64: // fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr -// CHECK-AARCH64: b.hi lbl // encoding: [0x08'A',A,A,0x54'A'] -// CHECK-AARCH64: // fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr -// CHECK-AARCH64: b.ls lbl // encoding: [0x09'A',A,A,0x54'A'] -// CHECK-AARCH64: // fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr -// CHECK-AARCH64: b.ge lbl // encoding: [0x0a'A',A,A,0x54'A'] -// CHECK-AARCH64: // fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr -// CHECK-AARCH64: b.lt lbl // encoding: [0x0b'A',A,A,0x54'A'] -// CHECK-AARCH64: // fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr -// CHECK-AARCH64: b.gt lbl // encoding: [0x0c'A',A,A,0x54'A'] -// CHECK-AARCH64: // fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr -// CHECK-AARCH64: b.le lbl // encoding: [0x0d'A',A,A,0x54'A'] -// CHECK-AARCH64: // fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr -// CHECK-AARCH64: b.al lbl // encoding: [0x0e'A',A,A,0x54'A'] -// CHECK-AARCH64: // fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr b.eq #0 b.lt #-4 @@ -2342,12 +2185,6 @@ _func: ldr w3, here ldr x29, there ldrsw xzr, everywhere -// CHECK-AARCH64: ldr w3, here // encoding: [0x03'A',A,A,0x18'A'] -// CHECK-AARCH64: // fixup A - offset: 0, value: here, kind: fixup_a64_ld_prel -// CHECK-AARCH64: ldr x29, there // encoding: [0x1d'A',A,A,0x58'A'] -// CHECK-AARCH64: // fixup A - offset: 0, value: there, kind: fixup_a64_ld_prel -// CHECK-AARCH64: ldrsw xzr, everywhere // encoding: [0x1f'A',A,A,0x98'A'] -// CHECK-AARCH64: // fixup A - offset: 0, value: everywhere, kind: fixup_a64_ld_prel // CHECK-ARM64: ldr w3, here // encoding: [0bAAA00011,A,A,0x18] // CHECK-ARM64: // fixup A - offset: 0, value: here, kind: fixup_arm64_ldr_pcrel_imm19 @@ -2359,12 +2196,6 @@ _func: ldr s0, who_knows ldr d0, i_dont ldr q0, there_must_be_a_better_way -// CHECK-AARCH64: ldr s0, who_knows // encoding: [A,A,A,0x1c'A'] -// CHECK-AARCH64: // fixup A - offset: 0, value: who_knows, kind: fixup_a64_ld_prel -// CHECK-AARCH64: ldr d0, i_dont // encoding: [A,A,A,0x5c'A'] -// CHECK-AARCH64: // fixup A - offset: 0, value: i_dont, kind: fixup_a64_ld_prel -// CHECK-AARCH64: ldr q0, there_must_be_a_better_way // encoding: [A,A,A,0x9c'A'] -// CHECK-AARCH64: // fixup A - offset: 0, value: there_must_be_a_better_way, kind: fixup_a64_ld_prel // CHECK-ARM64: ldr s0, who_knows // encoding: [0bAAA00000,A,A,0x1c] // CHECK-ARM64: // fixup A - offset: 0, value: who_knows, kind: fixup_arm64_ldr_pcrel_imm19 @@ -2380,10 +2211,6 @@ _func: prfm pldl1strm, nowhere prfm #22, somewhere -// CHECK-AARCH64: prfm pldl1strm, nowhere // encoding: [0x01'A',A,A,0xd8'A'] -// CHECK-AARCH64: // fixup A - offset: 0, value: nowhere, kind: fixup_a64_ld_prel -// CHECK-AARCH64: prfm #22, somewhere // encoding: [0x16'A',A,A,0xd8'A'] -// CHECK-AARCH64: // fixup A - offset: 0, value: somewhere, kind: fixup_a64_ld_prel // CHECK-ARM64: prfm pldl1strm, nowhere // encoding: [0bAAA00001,A,A,0xd8] // CHECK-ARM64: // fixup A - offset: 0, value: nowhere, kind: fixup_arm64_ldr_pcrel_imm19 @@ -2603,18 +2430,6 @@ _func: ldrsw x15, [x5, #:lo12:sym] ldr x15, [x5, #:lo12:sym] ldr q3, [x2, #:lo12:sym] -// CHECK-AARCH64: str x15, [x5, #:lo12:sym] // encoding: [0xaf'A',A,A,0xf9'A'] -// CHECK-AARCH64: // fixup A - offset: 0, value: :lo12:sym, kind: fixup_a64_ldst64_lo12 -// CHECK-AARCH64: ldrb w15, [x5, #:lo12:sym] // encoding: [0xaf'A',A,0x40'A',0x39'A'] -// CHECK-AARCH64: // fixup A - offset: 0, value: :lo12:sym, kind: fixup_a64_ldst8_lo12 -// CHECK-AARCH64: ldrsh x15, [x5, #:lo12:sym] // encoding: [0xaf'A',A,0x80'A',0x79'A'] -// CHECK-AARCH64: // fixup A - offset: 0, value: :lo12:sym, kind: fixup_a64_ldst16_lo12 -// CHECK-AARCH64: ldrsw x15, [x5, #:lo12:sym] // encoding: [0xaf'A',A,0x80'A',0xb9'A'] -// CHECK-AARCH64: // fixup A - offset: 0, value: :lo12:sym, kind: fixup_a64_ldst32_lo12 -// CHECK-AARCH64: ldr x15, [x5, #:lo12:sym] // encoding: [0xaf'A',A,0x40'A',0xf9'A'] -// CHECK-AARCH64: // fixup A - offset: 0, value: :lo12:sym, kind: fixup_a64_ldst64_lo12 -// CHECK-AARCH64: ldr q3, [x2, #:lo12:sym] // encoding: [0x43'A',A,0xc0'A',0x3d'A'] -// CHECK-AARCH64: // fixup A - offset: 0, value: :lo12:sym, kind: fixup_a64_ldst128_lo12 // CHECK-ARM64: str x15, [x5, :lo12:sym] // encoding: [0xaf,0bAAAAAA00,0b00AAAAAA,0xf9] // CHECK-ARM64: // fixup A - offset: 0, value: :lo12:sym, kind: fixup_arm64_ldst_imm12_scale8 @@ -3507,10 +3322,6 @@ _func: movz x2, #:abs_g0:sym movk w3, #:abs_g0_nc:sym -// CHECK-AARCH64: movz x2, #:abs_g0:sym // encoding: [0x02'A',A,0x80'A',0xd2'A'] -// CHECK-AARCH64-NEXT: // fixup A - offset: 0, value: :abs_g0:sym, kind: fixup_a64_movw_uabs_g0 -// CHECK-AARCH64: movk w3, #:abs_g0_nc:sym // encoding: [0x03'A',A,0x80'A',0x72'A'] -// CHECK-AARCH64-NEXT: // fixup A - offset: 0, value: :abs_g0_nc:sym, kind: fixup_a64_movw_uabs_g0_nc // CHECK-ARM64: movz x2, #:abs_g0:sym // encoding: [0bAAA00010,A,0b100AAAAA,0xd2] // CHECK-ARM64-NEXT: // fixup A - offset: 0, value: :abs_g0:sym, kind: fixup_arm64_movw @@ -3519,10 +3330,6 @@ _func: movz x4, #:abs_g1:sym movk w5, #:abs_g1_nc:sym -// CHECK-AARCH64: movz x4, #:abs_g1:sym // encoding: [0x04'A',A,0xa0'A',0xd2'A'] -// CHECK-AARCH64-NEXT: // fixup A - offset: 0, value: :abs_g1:sym, kind: fixup_a64_movw_uabs_g1 -// CHECK-AARCH64: movk w5, #:abs_g1_nc:sym // encoding: [0x05'A',A,0xa0'A',0x72'A'] -// CHECK-AARCH64-NEXT: // fixup A - offset: 0, value: :abs_g1_nc:sym, kind: fixup_a64_movw_uabs_g1_nc // CHECK-ARM64: movz x4, #:abs_g1:sym // encoding: [0bAAA00100,A,0b101AAAAA,0xd2] // CHECK-ARM64-NEXT: // fixup A - offset: 0, value: :abs_g1:sym, kind: fixup_arm64_movw @@ -3531,10 +3338,6 @@ _func: movz x6, #:abs_g2:sym movk x7, #:abs_g2_nc:sym -// CHECK-AARCH64: movz x6, #:abs_g2:sym // encoding: [0x06'A',A,0xc0'A',0xd2'A'] -// CHECK-AARCH64-NEXT: // fixup A - offset: 0, value: :abs_g2:sym, kind: fixup_a64_movw_uabs_g2 -// CHECK-AARCH64: movk x7, #:abs_g2_nc:sym // encoding: [0x07'A',A,0xc0'A',0xf2'A'] -// CHECK-AARCH64-NEXT: // fixup A - offset: 0, value: :abs_g2_nc:sym, kind: fixup_a64_movw_uabs_g2_nc // CHECK-ARM64: movz x6, #:abs_g2:sym // encoding: [0bAAA00110,A,0b110AAAAA,0xd2] // CHECK-ARM64-NEXT: // fixup A - offset: 0, value: :abs_g2:sym, kind: fixup_arm64_movw @@ -3543,10 +3346,6 @@ _func: movz x8, #:abs_g3:sym movk x9, #:abs_g3:sym -// CHECK-AARCH64: movz x8, #:abs_g3:sym // encoding: [0x08'A',A,0xe0'A',0xd2'A'] -// CHECK-AARCH64-NEXT: // fixup A - offset: 0, value: :abs_g3:sym, kind: fixup_a64_movw_uabs_g3 -// CHECK-AARCH64: movk x9, #:abs_g3:sym // encoding: [0x09'A',A,0xe0'A',0xf2'A'] -// CHECK-AARCH64-NEXT: // fixup A - offset: 0, value: :abs_g3:sym, kind: fixup_a64_movw_uabs_g3 // CHECK-ARM64: movz x8, #:abs_g3:sym // encoding: [0bAAA01000,A,0b111AAAAA,0xd2] // CHECK-ARM64-NEXT: // fixup A - offset: 0, value: :abs_g3:sym, kind: fixup_arm64_movw @@ -3558,14 +3357,6 @@ _func: movz x19, #:abs_g0_s:sym movn w10, #:abs_g0_s:sym movz w25, #:abs_g0_s:sym -// CHECK-AARCH64: movn x30, #:abs_g0_s:sym // encoding: [0x1e'A',A,0x80'A',0x92'A'] -// CHECK-AARCH64-NEXT: // fixup A - offset: 0, value: :abs_g0_s:sym, kind: fixup_a64_movw_sabs_g0 -// CHECK-AARCH64: movz x19, #:abs_g0_s:sym // encoding: [0x13'A',A,0x80'A',0x92'A'] -// CHECK-AARCH64-NEXT: // fixup A - offset: 0, value: :abs_g0_s:sym, kind: fixup_a64_movw_sabs_g0 -// CHECK-AARCH64: movn w10, #:abs_g0_s:sym // encoding: [0x0a'A',A,0x80'A',0x12'A'] -// CHECK-AARCH64-NEXT: // fixup A - offset: 0, value: :abs_g0_s:sym, kind: fixup_a64_movw_sabs_g0 -// CHECK-AARCH64: movz w25, #:abs_g0_s:sym // encoding: [0x19'A',A,0x80'A',0x12'A'] -// CHECK-AARCH64-NEXT: // fixup A - offset: 0, value: :abs_g0_s:sym, kind: fixup_a64_movw_sabs_g0 // CHECK-ARM64: movn x30, #:abs_g0_s:sym // encoding: [0bAAA11110,A,0b100AAAAA,0x92] // CHECK-ARM64-NEXT: // fixup A - offset: 0, value: :abs_g0_s:sym, kind: fixup_arm64_movw @@ -3580,14 +3371,6 @@ _func: movz x19, #:abs_g1_s:sym movn w10, #:abs_g1_s:sym movz w25, #:abs_g1_s:sym -// CHECK-AARCH64: movn x30, #:abs_g1_s:sym // encoding: [0x1e'A',A,0xa0'A',0x92'A'] -// CHECK-AARCH64-NEXT: // fixup A - offset: 0, value: :abs_g1_s:sym, kind: fixup_a64_movw_sabs_g1 -// CHECK-AARCH64: movz x19, #:abs_g1_s:sym // encoding: [0x13'A',A,0xa0'A',0x92'A'] -// CHECK-AARCH64-NEXT: // fixup A - offset: 0, value: :abs_g1_s:sym, kind: fixup_a64_movw_sabs_g1 -// CHECK-AARCH64: movn w10, #:abs_g1_s:sym // encoding: [0x0a'A',A,0xa0'A',0x12'A'] -// CHECK-AARCH64-NEXT: // fixup A - offset: 0, value: :abs_g1_s:sym, kind: fixup_a64_movw_sabs_g1 -// CHECK-AARCH64: movz w25, #:abs_g1_s:sym // encoding: [0x19'A',A,0xa0'A',0x12'A'] -// CHECK-AARCH64-NEXT: // fixup A - offset: 0, value: :abs_g1_s:sym, kind: fixup_a64_movw_sabs_g1 // CHECK-ARM64: movn x30, #:abs_g1_s:sym // encoding: [0bAAA11110,A,0b101AAAAA,0x92] // CHECK-ARM64-NEXT: // fixup A - offset: 0, value: :abs_g1_s:sym, kind: fixup_arm64_movw @@ -3600,10 +3383,6 @@ _func: movn x30, #:abs_g2_s:sym movz x19, #:abs_g2_s:sym -// CHECK-AARCH64: movn x30, #:abs_g2_s:sym // encoding: [0x1e'A',A,0xc0'A',0x92'A'] -// CHECK-AARCH64-NEXT: // fixup A - offset: 0, value: :abs_g2_s:sym, kind: fixup_a64_movw_sabs_g2 -// CHECK-AARCH64: movz x19, #:abs_g2_s:sym // encoding: [0x13'A',A,0xc0'A',0x92'A'] -// CHECK-AARCH64-NEXT: // fixup A - offset: 0, value: :abs_g2_s:sym, kind: fixup_a64_movw_sabs_g2 // CHECK-ARM64: movn x30, #:abs_g2_s:sym // encoding: [0bAAA11110,A,0b110AAAAA,0x92] // CHECK-ARM64-NEXT: // fixup A - offset: 0, value: :abs_g2_s:sym, kind: fixup_arm64_movw @@ -3616,10 +3395,6 @@ _func: adr x2, loc adr xzr, loc - // CHECK-AARCH64: adr x2, loc // encoding: [0x02'A',A,A,0x10'A'] - // CHECK-AARCH64: // fixup A - offset: 0, value: loc, kind: fixup_a64_adr_prel - // CHECK-AARCH64: adr xzr, loc // encoding: [0x1f'A',A,A,0x10'A'] - // CHECK-AARCH64: // fixup A - offset: 0, value: loc, kind: fixup_a64_adr_prel // CHECK-ARM64: adr x2, loc // encoding: [0x02'A',A,A,0x10'A'] // CHECK-ARM64: // fixup A - offset: 0, value: loc, kind: fixup_arm64_pcrel_adr_imm21 @@ -3627,8 +3402,6 @@ _func: // CHECK-ARM64: // fixup A - offset: 0, value: loc, kind: fixup_arm64_pcrel_adr_imm21 adrp x29, loc - // CHECK-AARCH64: adrp x29, loc // encoding: [0x1d'A',A,A,0x90'A'] - // CHECK-AARCH64: // fixup A - offset: 0, value: loc, kind: fixup_a64_adr_prel_page // CHECK-ARM64: adrp x29, loc // encoding: [0x1d'A',A,A,0x90'A'] // CHECK-ARM64: // fixup A - offset: 0, value: loc, kind: fixup_arm64_pcrel_adrp_imm21 @@ -5008,12 +4781,6 @@ _func: tbz x5, #0, somewhere tbz xzr, #63, elsewhere tbnz x5, #45, nowhere -// CHECK-AARCH64: tbz x5, #0, somewhere // encoding: [0x05'A',A,A,0x36'A'] -// CHECK-AARCH64: // fixup A - offset: 0, value: somewhere, kind: fixup_a64_tstbr -// CHECK-AARCH64: tbz xzr, #63, elsewhere // encoding: [0x1f'A',A,0xf8'A',0xb6'A'] -// CHECK-AARCH64: // fixup A - offset: 0, value: elsewhere, kind: fixup_a64_tstbr -// CHECK-AARCH64: tbnz x5, #45, nowhere // encoding: [0x05'A',A,0x68'A',0xb7'A'] -// CHECK-AARCH64: // fixup A - offset: 0, value: nowhere, kind: fixup_a64_tstbr // CHECK-ARM64: tbz w5, #0, somewhere // encoding: [0bAAA00101,A,0b00000AAA,0x36] // CHECK-ARM64: // fixup A - offset: 0, value: somewhere, kind: fixup_arm64_pcrel_branch14 @@ -5026,12 +4793,6 @@ _func: tbnz w3, #2, there tbnz wzr, #31, nowhere tbz w5, #12, anywhere -// CHECK-AARCH64: tbnz w3, #2, there // encoding: [0x03'A',A,0x10'A',0x37'A'] -// CHECK-AARCH64: // fixup A - offset: 0, value: there, kind: fixup_a64_tstbr -// CHECK-AARCH64: tbnz wzr, #31, nowhere // encoding: [0x1f'A',A,0xf8'A',0x37'A'] -// CHECK-AARCH64: // fixup A - offset: 0, value: nowhere, kind: fixup_a64_tstbr -// CHECK-AARCH64: tbz w5, #12, anywhere // encoding: [0x05'A',A,0x60'A',0x36'A'] -// CHECK-AARCH64: // fixup A - offset: 0, value: anywhere, kind: fixup_a64_tstbr // CHECK-ARM64: tbnz w3, #2, there // encoding: [0bAAA00011,A,0b00010AAA,0x37] // CHECK-ARM64: // fixup A - offset: 0, value: there, kind: fixup_arm64_pcrel_branch14 @@ -5046,10 +4807,6 @@ _func: b somewhere bl elsewhere -// CHECK-AARCH64: b somewhere // encoding: [A,A,A,0x14'A'] -// CHECK-AARCH64: // fixup A - offset: 0, value: somewhere, kind: fixup_a64_uncondbr -// CHECK-AARCH64: bl elsewhere // encoding: [A,A,A,0x94'A'] -// CHECK-AARCH64: // fixup A - offset: 0, value: elsewhere, kind: fixup_a64_call // CHECK-ARM64: b somewhere // encoding: [A,A,A,0b000101AA] // CHECK-ARM64: // fixup A - offset: 0, value: somewhere, kind: fixup_arm64_pcrel_branch26 diff --git a/llvm/test/MC/AArch64/basic-pic.s b/llvm/test/MC/AArch64/basic-pic.s index c3317f35d3b..6bb6aaa7de1 100644 --- a/llvm/test/MC/AArch64/basic-pic.s +++ b/llvm/test/MC/AArch64/basic-pic.s @@ -1,4 +1,3 @@ -// RUN: llvm-mc -triple=aarch64-none-linux-gnu -filetype=obj %s -o -| llvm-objdump -r - | FileCheck %s // RUN: llvm-mc -triple=arm64-none-linux-gnu -filetype=obj %s -o -| llvm-objdump -r - | FileCheck %s // CHECK: RELOCATION RECORDS FOR [.rela.text] diff --git a/llvm/test/MC/AArch64/elf-extern.s b/llvm/test/MC/AArch64/elf-extern.s index 23cb4bd46c7..3d84bde052f 100644 --- a/llvm/test/MC/AArch64/elf-extern.s +++ b/llvm/test/MC/AArch64/elf-extern.s @@ -1,4 +1,3 @@ -// RUN: llvm-mc < %s -triple=aarch64-none-linux-gnu -filetype=obj | llvm-readobj -r | FileCheck %s // RUN: llvm-mc < %s -triple=arm64-none-linux-gnu -filetype=obj | llvm-readobj -r | FileCheck %s // External symbols are a different concept to global variables but should still diff --git a/llvm/test/MC/AArch64/elf-objdump.s b/llvm/test/MC/AArch64/elf-objdump.s index 2d134ff5862..b69926efbc2 100644 --- a/llvm/test/MC/AArch64/elf-objdump.s +++ b/llvm/test/MC/AArch64/elf-objdump.s @@ -1,5 +1,4 @@ // 64 bit little endian -// RUN: llvm-mc -filetype=obj -triple aarch64-none-linux-gnu %s -o - | llvm-objdump -d - // RUN: llvm-mc -filetype=obj -triple arm64-none-linux-gnu %s -o - | llvm-objdump -d - // We just want to see if llvm-objdump works at all. diff --git a/llvm/test/MC/AArch64/elf-reloc-addend.s b/llvm/test/MC/AArch64/elf-reloc-addend.s deleted file mode 100644 index 8d575fb8b92..00000000000 --- a/llvm/test/MC/AArch64/elf-reloc-addend.s +++ /dev/null @@ -1,10 +0,0 @@ -// RUN: llvm-mc -triple=aarch64-linux-gnu -filetype=obj -o - %s | llvm-objdump -triple=aarch64-linux-gnu -r - | FileCheck %s - -// RUN: llvm-mc -triple=arm64-linux-gnu -filetype=obj -o - %s | llvm-objdump -triple=aarch64-linux-gnu -r - | FileCheck %s - - add x0, x4, #:lo12:sym -// CHECK: 0 R_AARCH64_ADD_ABS_LO12_NC sym - add x3, x5, #:lo12:sym+1 -// CHECK: 4 R_AARCH64_ADD_ABS_LO12_NC sym+1 - add x3, x5, #:lo12:sym-1 -// CHECK: 8 R_AARCH64_ADD_ABS_LO12_NC sym-1 diff --git a/llvm/test/MC/AArch64/elf-reloc-addsubimm.s b/llvm/test/MC/AArch64/elf-reloc-addsubimm.s index a64249e8b8f..cc5c3f7f25b 100644 --- a/llvm/test/MC/AArch64/elf-reloc-addsubimm.s +++ b/llvm/test/MC/AArch64/elf-reloc-addsubimm.s @@ -1,6 +1,3 @@ -// RUN: llvm-mc -triple=aarch64-none-linux-gnu -filetype=obj %s -o - | \ -// RUN: llvm-readobj -r | FileCheck -check-prefix=OBJ %s - // RUN: llvm-mc -triple=arm64-none-linux-gnu -filetype=obj %s -o - | \ // RUN: llvm-readobj -r | FileCheck -check-prefix=OBJ %s diff --git a/llvm/test/MC/AArch64/elf-reloc-ldrlit.s b/llvm/test/MC/AArch64/elf-reloc-ldrlit.s index 55ba5f8b748..3554ef3ae42 100644 --- a/llvm/test/MC/AArch64/elf-reloc-ldrlit.s +++ b/llvm/test/MC/AArch64/elf-reloc-ldrlit.s @@ -1,6 +1,3 @@ -// RUN: llvm-mc -triple=aarch64-none-linux-gnu -filetype=obj %s -o - | \ -// RUN: llvm-readobj -r | FileCheck -check-prefix=OBJ %s - // RUN: llvm-mc -triple=arm64-none-linux-gnu -filetype=obj %s -o - | \ // RUN: llvm-readobj -r | FileCheck -check-prefix=OBJ %s diff --git a/llvm/test/MC/AArch64/elf-reloc-ldstunsimm.s b/llvm/test/MC/AArch64/elf-reloc-ldstunsimm.s index faf2c459a65..196f65fd299 100644 --- a/llvm/test/MC/AArch64/elf-reloc-ldstunsimm.s +++ b/llvm/test/MC/AArch64/elf-reloc-ldstunsimm.s @@ -1,6 +1,3 @@ -// RUN: llvm-mc -triple=aarch64-none-linux-gnu -mattr=+fp-armv8 -filetype=obj %s -o - | \ -// RUN: llvm-readobj -r | FileCheck -check-prefix=OBJ %s - // RUN: llvm-mc -triple=arm64-none-linux-gnu -mattr=+fp-armv8 -filetype=obj %s -o - | \ // RUN: llvm-readobj -r | FileCheck -check-prefix=OBJ %s diff --git a/llvm/test/MC/AArch64/elf-reloc-movw.s b/llvm/test/MC/AArch64/elf-reloc-movw.s index 29f89443c33..dc7dbb0c156 100644 --- a/llvm/test/MC/AArch64/elf-reloc-movw.s +++ b/llvm/test/MC/AArch64/elf-reloc-movw.s @@ -1,6 +1,3 @@ -// RUN: llvm-mc -triple=aarch64-none-linux-gnu -filetype=obj %s -o - | \ -// RUN: llvm-readobj -r | FileCheck -check-prefix=OBJ %s - // RUN: llvm-mc -triple=arm64-none-linux-gnu -filetype=obj %s -o - | \ // RUN: llvm-readobj -r | FileCheck -check-prefix=OBJ %s diff --git a/llvm/test/MC/AArch64/elf-reloc-pcreladdressing.s b/llvm/test/MC/AArch64/elf-reloc-pcreladdressing.s index ee9b2073694..652011318c3 100644 --- a/llvm/test/MC/AArch64/elf-reloc-pcreladdressing.s +++ b/llvm/test/MC/AArch64/elf-reloc-pcreladdressing.s @@ -1,7 +1,4 @@ -// RUN: llvm-mc -triple=aarch64-none-linux-gnu -filetype=obj %s -o - | \ -// RUN: llvm-readobj -r | FileCheck -check-prefix=OBJ %s - - // RUN: llvm-mc -triple=arm64-none-linux-gnu -filetype=obj %s -o - | \ +// RUN: llvm-mc -triple=arm64-none-linux-gnu -filetype=obj %s -o - | \ // RUN: llvm-readobj -r | FileCheck -check-prefix=OBJ %s adr x2, some_label diff --git a/llvm/test/MC/AArch64/elf-reloc-tstb.s b/llvm/test/MC/AArch64/elf-reloc-tstb.s index 370b9ee126a..9cbe3a53fb7 100644 --- a/llvm/test/MC/AArch64/elf-reloc-tstb.s +++ b/llvm/test/MC/AArch64/elf-reloc-tstb.s @@ -1,6 +1,3 @@ -// RUN: llvm-mc -triple=aarch64-none-linux-gnu -filetype=obj %s -o - | \ -// RUN: llvm-readobj -r | FileCheck -check-prefix=OBJ %s - // RUN: llvm-mc -triple=arm64-none-linux-gnu -filetype=obj %s -o - | \ // RUN: llvm-readobj -r | FileCheck -check-prefix=OBJ %s diff --git a/llvm/test/MC/AArch64/elf-reloc-uncondbrimm.s b/llvm/test/MC/AArch64/elf-reloc-uncondbrimm.s index 69b0a2fcb61..8f3915afab7 100644 --- a/llvm/test/MC/AArch64/elf-reloc-uncondbrimm.s +++ b/llvm/test/MC/AArch64/elf-reloc-uncondbrimm.s @@ -1,6 +1,3 @@ -// RUN: llvm-mc -triple=aarch64-none-linux-gnu -filetype=obj %s -o - | \ -// RUN: llvm-readobj -r | FileCheck -check-prefix=OBJ %s - // RUN: llvm-mc -triple=arm64-none-linux-gnu -filetype=obj %s -o - | \ // RUN: llvm-readobj -r | FileCheck -check-prefix=OBJ %s diff --git a/llvm/test/MC/AArch64/gicv3-regs-diagnostics.s b/llvm/test/MC/AArch64/gicv3-regs-diagnostics.s index c8843123541..6f4f5ee66c6 100644 --- a/llvm/test/MC/AArch64/gicv3-regs-diagnostics.s +++ b/llvm/test/MC/AArch64/gicv3-regs-diagnostics.s @@ -1,4 +1,3 @@ -// RUN: not llvm-mc -triple aarch64-none-linux-gnu < %s 2>&1 | FileCheck %s // RUN: not llvm-mc -triple arm64-none-linux-gnu < %s 2>&1 | FileCheck %s // Write-only diff --git a/llvm/test/MC/AArch64/gicv3-regs.s b/llvm/test/MC/AArch64/gicv3-regs.s index 470fc4667f7..b9eac1a5695 100644 --- a/llvm/test/MC/AArch64/gicv3-regs.s +++ b/llvm/test/MC/AArch64/gicv3-regs.s @@ -1,4 +1,3 @@ - // RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding < %s | FileCheck %s // RUN: llvm-mc -triple arm64-none-linux-gnu -show-encoding < %s | FileCheck %s mrs x8, icc_iar1_el1 diff --git a/llvm/test/MC/AArch64/inline-asm-modifiers.s b/llvm/test/MC/AArch64/inline-asm-modifiers.s index c12ebf4636b..33d5bf519f9 100644 --- a/llvm/test/MC/AArch64/inline-asm-modifiers.s +++ b/llvm/test/MC/AArch64/inline-asm-modifiers.s @@ -1,4 +1,3 @@ -// RUN: llvm-mc -triple=aarch64-none-linux-gnu -filetype=obj -mattr=+fp-armv8 < %s | llvm-objdump -r - | FileCheck %s // RUN: llvm-mc -triple=arm64-none-linux-gnu -filetype=obj -mattr=+fp-armv8 < %s | llvm-objdump -r - | FileCheck %s .file "<stdin>" diff --git a/llvm/test/MC/AArch64/jump-table.s b/llvm/test/MC/AArch64/jump-table.s index 3fe9bc58cdd..439ecd90de3 100644 --- a/llvm/test/MC/AArch64/jump-table.s +++ b/llvm/test/MC/AArch64/jump-table.s @@ -1,4 +1,3 @@ -// RUN: llvm-mc < %s -triple=aarch64-none-linux-gnu -filetype=obj | llvm-readobj -r | FileCheck %s // RUN: llvm-mc < %s -triple=arm64-none-linux-gnu -filetype=obj | llvm-readobj -r | FileCheck %s .file "<stdin>" diff --git a/llvm/test/MC/AArch64/lit.local.cfg b/llvm/test/MC/AArch64/lit.local.cfg index 8378712e9cf..17a6b7ab033 100644 --- a/llvm/test/MC/AArch64/lit.local.cfg +++ b/llvm/test/MC/AArch64/lit.local.cfg @@ -1,3 +1,3 @@ targets = set(config.root.targets_to_build.split()) -if 'AArch64' not in targets or 'ARM64' not in targets: - config.unsupported = True
\ No newline at end of file +if 'ARM64' not in targets: + config.unsupported = True diff --git a/llvm/test/MC/AArch64/mapping-across-sections.s b/llvm/test/MC/AArch64/mapping-across-sections.s index 14336382bed..00b324cb826 100644 --- a/llvm/test/MC/AArch64/mapping-across-sections.s +++ b/llvm/test/MC/AArch64/mapping-across-sections.s @@ -1,4 +1,3 @@ -// RUN: llvm-mc -triple=aarch64-none-linux-gnu -filetype=obj < %s | llvm-objdump -t - | FileCheck %s // RUN: llvm-mc -triple=arm64-none-linux-gnu -filetype=obj < %s | llvm-objdump -t - | FileCheck %s .text diff --git a/llvm/test/MC/AArch64/mapping-within-section.s b/llvm/test/MC/AArch64/mapping-within-section.s index b80721ac652..f515cb9a5c0 100644 --- a/llvm/test/MC/AArch64/mapping-within-section.s +++ b/llvm/test/MC/AArch64/mapping-within-section.s @@ -1,4 +1,3 @@ -// RUN: llvm-mc -triple=aarch64-none-linux-gnu -filetype=obj < %s | llvm-objdump -t - | FileCheck %s // RUN: llvm-mc -triple=arm64-none-linux-gnu -filetype=obj < %s | llvm-objdump -t - | FileCheck %s .text diff --git a/llvm/test/MC/AArch64/neon-2velem.s b/llvm/test/MC/AArch64/neon-2velem.s index 567f2289217..04841d0164f 100644 --- a/llvm/test/MC/AArch64/neon-2velem.s +++ b/llvm/test/MC/AArch64/neon-2velem.s @@ -1,4 +1,3 @@ -// RUN: llvm-mc -triple=aarch64 -mattr=+neon -show-encoding < %s | FileCheck %s // RUN: llvm-mc -triple=arm64 -mattr=+neon -show-encoding < %s | FileCheck %s // Check that the assembler can handle the documented syntax for AArch64 diff --git a/llvm/test/MC/AArch64/neon-3vdiff.s b/llvm/test/MC/AArch64/neon-3vdiff.s index 476f7c6abe6..3ffc38fc69c 100644 --- a/llvm/test/MC/AArch64/neon-3vdiff.s +++ b/llvm/test/MC/AArch64/neon-3vdiff.s @@ -1,4 +1,3 @@ -// RUN: llvm-mc -triple=aarch64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s // RUN: llvm-mc -triple=arm64-none-linux-gnu -mattr=+crypto -mattr=+neon -show-encoding < %s | FileCheck %s // Check that the assembler can handle the documented syntax for AArch64 diff --git a/llvm/test/MC/AArch64/neon-aba-abd.s b/llvm/test/MC/AArch64/neon-aba-abd.s index 8833b3bbe95..e7964834146 100644 --- a/llvm/test/MC/AArch64/neon-aba-abd.s +++ b/llvm/test/MC/AArch64/neon-aba-abd.s @@ -1,4 +1,3 @@ -// RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s // RUN: llvm-mc -triple arm64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s // Check that the assembler can handle the documented syntax for AArch64 diff --git a/llvm/test/MC/AArch64/neon-across.s b/llvm/test/MC/AArch64/neon-across.s index 1a5446b3a4f..60b766d8c88 100644 --- a/llvm/test/MC/AArch64/neon-across.s +++ b/llvm/test/MC/AArch64/neon-across.s @@ -1,4 +1,3 @@ -// RUN: llvm-mc -triple=aarch64 -mattr=+neon -show-encoding < %s | FileCheck %s // RUN: llvm-mc -triple=arm64 -mattr=+neon -show-encoding < %s | FileCheck %s // Check that the assembler can handle the documented syntax for AArch64 diff --git a/llvm/test/MC/AArch64/neon-add-pairwise.s b/llvm/test/MC/AArch64/neon-add-pairwise.s index 83d443edb77..0b9e4d3146b 100644 --- a/llvm/test/MC/AArch64/neon-add-pairwise.s +++ b/llvm/test/MC/AArch64/neon-add-pairwise.s @@ -1,4 +1,3 @@ -// RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s // RUN: llvm-mc -triple arm64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s // Check that the assembler can handle the documented syntax for AArch64 diff --git a/llvm/test/MC/AArch64/neon-add-sub-instructions.s b/llvm/test/MC/AArch64/neon-add-sub-instructions.s index ad169a8ff24..7d11d70bb90 100644 --- a/llvm/test/MC/AArch64/neon-add-sub-instructions.s +++ b/llvm/test/MC/AArch64/neon-add-sub-instructions.s @@ -1,4 +1,3 @@ -// RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s // RUN: llvm-mc -triple arm64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s // Check that the assembler can handle the documented syntax for AArch64 diff --git a/llvm/test/MC/AArch64/neon-bitwise-instructions.s b/llvm/test/MC/AArch64/neon-bitwise-instructions.s index 949d1b14ffc..ec192aa2d8a 100644 --- a/llvm/test/MC/AArch64/neon-bitwise-instructions.s +++ b/llvm/test/MC/AArch64/neon-bitwise-instructions.s @@ -1,4 +1,3 @@ -// RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s // RUN: llvm-mc -triple arm64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s // Check that the assembler can handle the documented syntax for AArch64 diff --git a/llvm/test/MC/AArch64/neon-compare-instructions.s b/llvm/test/MC/AArch64/neon-compare-instructions.s index dfc3ae71515..4d3daf066ed 100644 --- a/llvm/test/MC/AArch64/neon-compare-instructions.s +++ b/llvm/test/MC/AArch64/neon-compare-instructions.s @@ -1,4 +1,3 @@ -// RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s // RUN: llvm-mc -triple arm64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s // Check that the assembler can handle the documented syntax for AArch64 diff --git a/llvm/test/MC/AArch64/neon-crypto.s b/llvm/test/MC/AArch64/neon-crypto.s index 3f36ba9e2a1..ed1bf888264 100644 --- a/llvm/test/MC/AArch64/neon-crypto.s +++ b/llvm/test/MC/AArch64/neon-crypto.s @@ -1,5 +1,3 @@ -// RUN: llvm-mc -triple=aarch64 -mattr=+neon -mattr=+crypto -show-encoding < %s | FileCheck %s -// RUN: not llvm-mc -triple=aarch64 -mattr=+neon -show-encoding < %s 2>&1 | FileCheck -check-prefix=CHECK-NO-CRYPTO %s // RUN: llvm-mc -triple=arm64 -mattr=+neon -mattr=+crypto -show-encoding < %s | FileCheck %s // RUN: not llvm-mc -triple=arm64 -mattr=+neon -show-encoding < %s 2>&1 | FileCheck -check-prefix=CHECK-NO-CRYPTO-ARM64 %s diff --git a/llvm/test/MC/AArch64/neon-diagnostics.s b/llvm/test/MC/AArch64/neon-diagnostics.s index 10fdde46028..46ae311f5f8 100644 --- a/llvm/test/MC/AArch64/neon-diagnostics.s +++ b/llvm/test/MC/AArch64/neon-diagnostics.s @@ -1,5 +1,3 @@ -// RUN: not llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon < %s 2> %t -// RUN: FileCheck --check-prefix=CHECK-ERROR --check-prefix=CHECK-AARCH64-ERROR < %t %s // RUN: not llvm-mc -triple arm64-none-linux-gnu -mattr=+neon < %s 2> %t // RUN: FileCheck --check-prefix=CHECK-ERROR --check-prefix=CHECK-ARM64-ERROR < %t %s @@ -590,12 +588,6 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: fcmgt v0.2d, v31.2s, v16.2s // CHECK-ERROR: ^ -// CHECK-AARCH64-ERROR: error: expected floating-point constant #0.0 or invalid register type -// CHECK-AARCH64-ERROR: fcmgt v4.4s, v7.4s, v15.4h -// CHECK-AARCH64-ERROR: ^ -// CHECK-AARCH64-ERROR: error: expected floating-point constant #0.0 or invalid register type -// CHECK-AARCH64-ERROR: fcmlt v29.2d, v5.2d, v2.16b -// CHECK-AARCH64-ERROR: ^ // CHECK-ARM64-ERROR: error: invalid operand for instruction // CHECK-ARM64-ERROR: fcmgt v4.4s, v7.4s, v15.4h @@ -691,12 +683,6 @@ // CHECK-ERROR: fcmeq v0.16b, v1.16b, #0.0 // CHECK-ERROR: ^ -// CHECK-AARCH64-ERROR: error: only #0.0 is acceptable as immediate -// CHECK-AARCH64-ERROR: fcmeq v0.8b, v1.4h, #1.0 -// CHECK-AARCH64-ERROR: ^ -// CHECK-AARCH64-ERROR: error: only #0.0 is acceptable as immediate -// CHECK-AARCH64-ERROR: fcmeq v0.8b, v1.4h, #1 -// CHECK-AARCH64-ERROR: ^ // CHECK-ARM64-ERROR: error: expected floating-point constant #0.0 // CHECK-ARM64-ERROR: fcmeq v0.8b, v1.4h, #1.0 @@ -722,12 +708,6 @@ // CHECK-ERROR: fcmge v3.8b, v8.2s, #0.0 // CHECK-ERROR: ^ -// CHECK-AARCH64-ERROR: error: only #0.0 is acceptable as immediate -// CHECK-AARCH64-ERROR: fcmle v17.8h, v15.2d, #-1.0 -// CHECK-AARCH64-ERROR: ^ -// CHECK-AARCH64-ERROR: error: only #0.0 is acceptable as immediate -// CHECK-AARCH64-ERROR: fcmle v17.8h, v15.2d, #2 -// CHECK-AARCH64-ERROR: ^ // CHECK-ARM64-ERROR: error: expected floating-point constant #0.0 // CHECK-ARM64-ERROR: fcmle v17.8h, v15.2d, #-1.0 @@ -752,12 +732,6 @@ // CHECK-ERROR: fcmgt v4.4s, v7.4h, #0.0 // CHECK-ERROR: ^ -// CHECK-AARCH64-ERROR: error: only #0.0 is acceptable as immediate -// CHECK-AARCH64-ERROR: fcmlt v29.2d, v5.2d, #255.0 -// CHECK-AARCH64-ERROR: ^ -// CHECK-AARCH64-ERROR: error: only #0.0 is acceptable as immediate -// CHECK-AARCH64-ERROR: fcmlt v29.2d, v5.2d, #255 -// CHECK-AARCH64-ERROR: ^ // CHECK-ARM64-ERROR: error: expected floating-point constant #0.0 // CHECK-ARM64-ERROR: fcmlt v29.2d, v5.2d, #255.0 @@ -782,12 +756,6 @@ // CHECK-ERROR: fcmge v3.8b, v8.2s, #0.0 // CHECK-ERROR: ^ -// CHECK-AARCH64-ERROR: error: only #0.0 is acceptable as immediate -// CHECK-AARCH64-ERROR: fcmle v17.2d, v15.2d, #15.0 -// CHECK-AARCH64-ERROR: ^ -// CHECK-AARCH64-ERROR: error: only #0.0 is acceptable as immediate -// CHECK-AARCH64-ERROR: fcmle v17.2d, v15.2d, #15 -// CHECK-AARCH64-ERROR: ^ // CHECK-ARM64-ERROR: error: expected floating-point constant #0.0 // CHECK-ARM64-ERROR: fcmle v17.2d, v15.2d, #15.0 @@ -812,12 +780,6 @@ // CHECK-ERROR: fcmgt v4.4s, v7.4h, #0.0 // CHECK-ERROR: ^ -// CHECK-AARCH64-ERROR: error: only #0.0 is acceptable as immediate -// CHECK-AARCH64-ERROR: fcmlt v29.2d, v5.2d, #16.0 -// CHECK-AARCH64-ERROR: ^ -// CHECK-AARCH64-ERROR: error: only #0.0 is acceptable as immediate -// CHECK-AARCH64-ERROR: fcmlt v29.2d, v5.2d, #2 -// CHECK-AARCH64-ERROR: ^ // CHECK-ARM64-ERROR: error: expected floating-point constant #0.0 // CHECK-ARM64-ERROR: fcmlt v29.2d, v5.2d, #16.0 @@ -1337,9 +1299,6 @@ shl v0.4s, v21.4s, #32 shl v0.2d, v1.2d, #64 -// CHECK-AARCH64-ERROR: error: expected comma before next operand -// CHECK-AARCH64-ERROR: shl v0.4s, v15,2s, #3 -// CHECK-AARCH64-ERROR: ^ // CHECK-ARM64-ERROR: error: unexpected token in argument list // CHECK-ARM64-ERROR: shl v0.4s, v15,2s, #3 @@ -2673,9 +2632,6 @@ pmull2 v0.4s, v1.8h v2.8h pmull2 v0.2d, v1.4s, v2.4s -// CHECK-AARCH64-ERROR: error: expected comma before next operand -// CHECK-AARCH64-ERROR: pmull2 v0.4s, v1.8h v2.8h -// CHECK-AARCH64-ERROR: ^ // CHECK-ARM64-ERROR: error: unexpected token in argument list // CHECK-ARM64-ERROR: pmull2 v0.4s, v1.8h v2.8h @@ -3003,22 +2959,18 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: mla v0.2d, v1.2d, v16.d[1] // CHECK-ERROR: ^ -// CHECK-AARCH64-ERROR: error: lane number incompatible with layout // CHECK-ARM64-ERROR: vector lane must be an integer in range // CHECK-ERROR: mla v0.2s, v1.2s, v2.s[4] // CHECK-ERROR: ^ -// CHECK-AARCH64-ERROR: error: lane number incompatible with layout // CHECK-ARM64-ERROR: vector lane must be an integer in range // CHECK-ERROR: mla v0.4s, v1.4s, v2.s[4] // CHECK-ERROR: ^ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: mla v0.2h, v1.2h, v2.h[1] // CHECK-ERROR: ^ -// CHECK-AARCH64-ERROR: error: lane number incompatible with layout // CHECK-ARM64-ERROR: vector lane must be an integer in range // CHECK-ERROR: mla v0.4h, v1.4h, v2.h[8] // CHECK-ERROR: ^ -// CHECK-AARCH64-ERROR: error: lane number incompatible with layout // CHECK-ARM64-ERROR: vector lane must be an integer in range // CHECK-ERROR: mla v0.8h, v1.8h, v2.h[8] // CHECK-ERROR: ^ @@ -3041,22 +2993,18 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: mls v0.2d, v1.2d, v16.d[1] // CHECK-ERROR: ^ -// CHECK-AARCH64-ERROR: error: lane number incompatible with layout // CHECK-ARM64-ERROR: vector lane must be an integer in range // CHECK-ERROR: mls v0.2s, v1.2s, v2.s[4] // CHECK-ERROR: ^ -// CHECK-AARCH64-ERROR: error: lane number incompatible with layout // CHECK-ARM64-ERROR: vector lane must be an integer in range // CHECK-ERROR: mls v0.4s, v1.4s, v2.s[4] // CHECK-ERROR: ^ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: mls v0.2h, v1.2h, v2.h[1] // CHECK-ERROR: ^ -// CHECK-AARCH64-ERROR: error: lane number incompatible with layout // CHECK-ARM64-ERROR: vector lane must be an integer in range // CHECK-ERROR: mls v0.4h, v1.4h, v2.h[8] // CHECK-ERROR: ^ -// CHECK-AARCH64-ERROR: error: lane number incompatible with layout // CHECK-ARM64-ERROR: vector lane must be an integer in range // CHECK-ERROR: mls v0.8h, v1.8h, v2.h[8] // CHECK-ERROR: ^ @@ -3082,27 +3030,21 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: fmla v0.8h, v1.8h, v2.h[2] // CHECK-ERROR: ^ -// CHECK-AARCH64-ERROR: error: lane number incompatible with layout // CHECK-ARM64-ERROR: vector lane must be an integer in range // CHECK-ERROR: fmla v0.2s, v1.2s, v2.s[4] // CHECK-ERROR: ^ -// CHECK-AARCH64-ERROR: error: lane number incompatible with layout // CHECK-ARM64-ERROR: vector lane must be an integer in range // CHECK-ERROR: fmla v0.2s, v1.2s, v22.s[4] // CHECK-ERROR: ^ -// CHECK-AARCH64-ERROR: error: lane number incompatible with layout // CHECK-ARM64-ERROR: vector lane must be an integer in range // CHECK-ERROR: fmla v3.4s, v8.4s, v2.s[4] // CHECK-ERROR: ^ -// CHECK-AARCH64-ERROR: error: lane number incompatible with layout // CHECK-ARM64-ERROR: vector lane must be an integer in range // CHECK-ERROR: fmla v3.4s, v8.4s, v22.s[4] // CHECK-ERROR: ^ -// CHECK-AARCH64-ERROR: error: lane number incompatible with layout // CHECK-ARM64-ERROR: vector lane must be an integer in range // CHECK-ERROR: fmla v0.2d, v1.2d, v2.d[2] // CHECK-ERROR: ^ -// CHECK-AARCH64-ERROR: error: lane number incompatible with layout // CHECK-ARM64-ERROR: vector lane must be an integer in range // CHECK-ERROR: fmla v0.2d, v1.2d, v22.d[2] // CHECK-ERROR: ^ @@ -3122,27 +3064,21 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: fmls v0.8h, v1.8h, v2.h[2] // CHECK-ERROR: ^ -// CHECK-AARCH64-ERROR: error: lane number incompatible with layout // CHECK-ARM64-ERROR: vector lane must be an integer in range // CHECK-ERROR: fmls v0.2s, v1.2s, v2.s[4] // CHECK-ERROR: ^ -// CHECK-AARCH64-ERROR: error: lane number incompatible with layout // CHECK-ARM64-ERROR: vector lane must be an integer in range // CHECK-ERROR: fmls v0.2s, v1.2s, v22.s[4] // CHECK-ERROR: ^ -// CHECK-AARCH64-ERROR: error: lane number incompatible with layout // CHECK-ARM64-ERROR: vector lane must be an integer in range // CHECK-ERROR: fmls v3.4s, v8.4s, v2.s[4] // CHECK-ERROR: ^ -// CHECK-AARCH64-ERROR: error: lane number incompatible with layout // CHECK-ARM64-ERROR: vector lane must be an integer in range // CHECK-ERROR: fmls v3.4s, v8.4s, v22.s[4] // CHECK-ERROR: ^ -// CHECK-AARCH64-ERROR: error: lane number incompatible with layout // CHECK-ARM64-ERROR: vector lane must be an integer in range // CHECK-ERROR: fmls v0.2d, v1.2d, v2.d[2] // CHECK-ERROR: ^ -// CHECK-AARCH64-ERROR: error: lane number incompatible with layout // CHECK-ARM64-ERROR: vector lane must be an integer in range // CHECK-ERROR: fmls v0.2d, v1.2d, v22.d[2] // CHECK-ERROR: ^ @@ -3163,7 +3099,6 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: smlal v0.4h, v1.4h, v2.h[2] // CHECK-ERROR: ^ -// CHECK-AARCH64-ERROR: error: lane number incompatible with layout // CHECK-ARM64-ERROR: vector lane must be an integer in range // CHECK-ERROR: smlal v0.4s, v1.4h, v2.h[8] // CHECK-ERROR: ^ @@ -3173,18 +3108,15 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: smlal v0.2s, v1.2s, v2.s[1] // CHECK-ERROR: ^ -// CHECK-AARCH64-ERROR: error: lane number incompatible with layout // CHECK-ARM64-ERROR: vector lane must be an integer in range // CHECK-ERROR: smlal v0.2d, v1.2s, v2.s[4] // CHECK-ERROR: ^ -// CHECK-AARCH64-ERROR: error: lane number incompatible with layout // CHECK-ARM64-ERROR: vector lane must be an integer in range // CHECK-ERROR: smlal v0.2d, v1.2s, v22.s[4] // CHECK-ERROR: ^ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: smlal2 v0.4h, v1.8h, v1.h[2] // CHECK-ERROR: ^ -// CHECK-AARCH64-ERROR: error: lane number incompatible with layout // CHECK-ARM64-ERROR: vector lane must be an integer in range // CHECK-ERROR: smlal2 v0.4s, v1.8h, v1.h[8] // CHECK-ERROR: ^ @@ -3194,11 +3126,9 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: smlal2 v0.2s, v1.4s, v1.s[2] // CHECK-ERROR: ^ -// CHECK-AARCH64-ERROR: error: lane number incompatible with layout // CHECK-ARM64-ERROR: vector lane must be an integer in range // CHECK-ERROR: smlal2 v0.2d, v1.4s, v1.s[4] // CHECK-ERROR: ^ -// CHECK-AARCH64-ERROR: error: lane number incompatible with layout // CHECK-ARM64-ERROR: vector lane must be an integer in range // CHECK-ERROR: smlal2 v0.2d, v1.4s, v22.s[4] // CHECK-ERROR: ^ @@ -3219,7 +3149,6 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: smlsl v0.4h, v1.4h, v2.h[2] // CHECK-ERROR: ^ -// CHECK-AARCH64-ERROR: error: lane number incompatible with layout // CHECK-ARM64-ERROR: vector lane must be an integer in range // CHECK-ERROR: smlsl v0.4s, v1.4h, v2.h[8] // CHECK-ERROR: ^ @@ -3229,18 +3158,15 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: smlsl v0.2s, v1.2s, v2.s[1] // CHECK-ERROR: ^ -// CHECK-AARCH64-ERROR: error: lane number incompatible with layout // CHECK-ARM64-ERROR: vector lane must be an integer in range // CHECK-ERROR: smlsl v0.2d, v1.2s, v2.s[4] // CHECK-ERROR: ^ -// CHECK-AARCH64-ERROR: error: lane number incompatible with layout // CHECK-ARM64-ERROR: vector lane must be an integer in range // CHECK-ERROR: smlsl v0.2d, v1.2s, v22.s[4] // CHECK-ERROR: ^ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: smlsl2 v0.4h, v1.8h, v1.h[2] // CHECK-ERROR: ^ -// CHECK-AARCH64-ERROR: error: lane number incompatible with layout // CHECK-ARM64-ERROR: vector lane must be an integer in range // CHECK-ERROR: smlsl2 v0.4s, v1.8h, v1.h[8] // CHECK-ERROR: ^ @@ -3250,11 +3176,9 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: smlsl2 v0.2s, v1.4s, v1.s[2] // CHECK-ERROR: ^ -// CHECK-AARCH64-ERROR: error: lane number incompatible with layout // CHECK-ARM64-ERROR: vector lane must be an integer in range // CHECK-ERROR: smlsl2 v0.2d, v1.4s, v1.s[4] // CHECK-ERROR: ^ -// CHECK-AARCH64-ERROR: error: lane number incompatible with layout // CHECK-ARM64-ERROR: vector lane must be an integer in range // CHECK-ERROR: smlsl2 v0.2d, v1.4s, v22.s[4] // CHECK-ERROR: ^ @@ -3275,7 +3199,6 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: umlal v0.4h, v1.4h, v2.h[2] // CHECK-ERROR: ^ -// CHECK-AARCH64-ERROR: error: lane number incompatible with layout // CHECK-ARM64-ERROR: vector lane must be an integer in range // CHECK-ERROR: umlal v0.4s, v1.4h, v2.h[8] // CHECK-ERROR: ^ @@ -3285,18 +3208,15 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: umlal v0.2s, v1.2s, v2.s[1] // CHECK-ERROR: ^ -// CHECK-AARCH64-ERROR: error: lane number incompatible with layout // CHECK-ARM64-ERROR: vector lane must be an integer in range // CHECK-ERROR: umlal v0.2d, v1.2s, v2.s[4] // CHECK-ERROR: ^ -// CHECK-AARCH64-ERROR: error: lane number incompatible with layout // CHECK-ARM64-ERROR: vector lane must be an integer in range // CHECK-ERROR: umlal v0.2d, v1.2s, v22.s[4] // CHECK-ERROR: ^ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: umlal2 v0.4h, v1.8h, v1.h[2] // CHECK-ERROR: ^ -// CHECK-AARCH64-ERROR: error: lane number incompatible with layout // CHECK-ARM64-ERROR: vector lane must be an integer in range // CHECK-ERROR: umlal2 v0.4s, v1.8h, v1.h[8] // CHECK-ERROR: ^ @@ -3306,11 +3226,9 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: umlal2 v0.2s, v1.4s, v1.s[2] // CHECK-ERROR: ^ -// CHECK-AARCH64-ERROR: error: lane number incompatible with layout // CHECK-ARM64-ERROR: vector lane must be an integer in range // CHECK-ERROR: umlal2 v0.2d, v1.4s, v1.s[4] // CHECK-ERROR: ^ -// CHECK-AARCH64-ERROR: error: lane number incompatible with layout // CHECK-ARM64-ERROR: vector lane must be an integer in range // CHECK-ERROR: umlal2 v0.2d, v1.4s, v22.s[4] // CHECK-ERROR: ^ @@ -3331,7 +3249,6 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: umlsl v0.4h, v1.4h, v2.h[2] // CHECK-ERROR: ^ -// CHECK-AARCH64-ERROR: error: lane number incompatible with layout // CHECK-ARM64-ERROR: vector lane must be an integer in range // CHECK-ERROR: umlsl v0.4s, v1.4h, v2.h[8] // CHECK-ERROR: ^ @@ -3341,18 +3258,15 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: umlsl v0.2s, v1.2s, v2.s[3] // CHECK-ERROR: ^ -// CHECK-AARCH64-ERROR: error: lane number incompatible with layout // CHECK-ARM64-ERROR: vector lane must be an integer in range // CHECK-ERROR: umlsl v0.2d, v1.2s, v2.s[4] // CHECK-ERROR: ^ -// CHECK-AARCH64-ERROR: error: lane number incompatible with layout // CHECK-ARM64-ERROR: vector lane must be an integer in range // CHECK-ERROR: umlsl v0.2d, v1.2s, v22.s[4] // CHECK-ERROR: ^ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: umlsl2 v0.4h, v1.8h, v1.h[2] // CHECK-ERROR: ^ -// CHECK-AARCH64-ERROR: error: lane number incompatible with layout // CHECK-ARM64-ERROR: vector lane must be an integer in range // CHECK-ERROR: umlsl2 v0.4s, v1.8h, v1.h[8] // CHECK-ERROR: ^ @@ -3362,11 +3276,9 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: umlsl2 v0.2s, v1.4s, v1.s[2] // CHECK-ERROR: ^ -// CHECK-AARCH64-ERROR: error: lane number incompatible with layout // CHECK-ARM64-ERROR: vector lane must be an integer in range // CHECK-ERROR: umlsl2 v0.2d, v1.4s, v1.s[4] // CHECK-ERROR: ^ -// CHECK-AARCH64-ERROR: error: lane number incompatible with layout // CHECK-ARM64-ERROR: vector lane must be an integer in range // CHECK-ERROR: umlsl2 v0.2d, v1.4s, v22.s[4] // CHECK-ERROR: ^ @@ -3387,7 +3299,6 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: sqdmlal v0.4h, v1.4h, v2.h[2] // CHECK-ERROR: ^ -// CHECK-AARCH64-ERROR: error: lane number incompatible with layout // CHECK-ARM64-ERROR: vector lane must be an integer in range // CHECK-ERROR: sqdmlal v0.4s, v1.4h, v2.h[8] // CHECK-ERROR: ^ @@ -3397,18 +3308,15 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: sqdmlal v0.2s, v1.2s, v2.s[3] // CHECK-ERROR: ^ -// CHECK-AARCH64-ERROR: error: lane number incompatible with layout // CHECK-ARM64-ERROR: vector lane must be an integer in range // CHECK-ERROR: sqdmlal v0.2d, v1.2s, v2.s[4] // CHECK-ERROR: ^ -// CHECK-AARCH64-ERROR: error: lane number incompatible with layout // CHECK-ARM64-ERROR: vector lane must be an integer in range // CHECK-ERROR: sqdmlal v0.2d, v1.2s, v22.s[4] // CHECK-ERROR: ^ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: sqdmlal2 v0.4h, v1.8h, v1.h[2] // CHECK-ERROR: ^ -// CHECK-AARCH64-ERROR: error: lane number incompatible with layout // CHECK-ARM64-ERROR: vector lane must be an integer in range // CHECK-ERROR: sqdmlal2 v0.4s, v1.8h, v1.h[8] // CHECK-ERROR: ^ @@ -3418,11 +3326,9 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: sqdmlal2 v0.2s, v1.4s, v1.s[2] // CHECK-ERROR: ^ -// CHECK-AARCH64-ERROR: error: lane number incompatible with layout // CHECK-ARM64-ERROR: vector lane must be an integer in range // CHECK-ERROR: sqdmlal2 v0.2d, v1.4s, v1.s[4] // CHECK-ERROR: ^ -// CHECK-AARCH64-ERROR: error: lane number incompatible with layout // CHECK-ARM64-ERROR: vector lane must be an integer in range // CHECK-ERROR: sqdmlal2 v0.2d, v1.4s, v22.s[4] // CHECK-ERROR: ^ @@ -3443,7 +3349,6 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: sqdmlsl v0.4h, v1.4h, v2.h[2] // CHECK-ERROR: ^ -// CHECK-AARCH64-ERROR: error: lane number incompatible with layout // CHECK-ARM64-ERROR: vector lane must be an integer in range // CHECK-ERROR: sqdmlsl v0.4s, v1.4h, v2.h[8] // CHECK-ERROR: ^ @@ -3453,18 +3358,15 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: sqdmlsl v0.2s, v1.2s, v2.s[3] // CHECK-ERROR: ^ -// CHECK-AARCH64-ERROR: error: lane number incompatible with layout // CHECK-ARM64-ERROR: vector lane must be an integer in range // CHECK-ERROR: sqdmlsl v0.2d, v1.2s, v2.s[4] // CHECK-ERROR: ^ -// CHECK-AARCH64-ERROR: error: lane number incompatible with layout // CHECK-ARM64-ERROR: vector lane must be an integer in range // CHECK-ERROR: sqdmlsl v0.2d, v1.2s, v22.s[4] // CHECK-ERROR: ^ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: sqdmlsl2 v0.4h, v1.8h, v1.h[2] // CHECK-ERROR: ^ -// CHECK-AARCH64-ERROR: error: lane number incompatible with layout // CHECK-ARM64-ERROR: vector lane must be an integer in range // CHECK-ERROR: sqdmlsl2 v0.4s, v1.8h, v1.h[8] // CHECK-ERROR: ^ @@ -3474,11 +3376,9 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: sqdmlsl2 v0.2s, v1.4s, v1.s[2] // CHECK-ERROR: ^ -// CHECK-AARCH64-ERROR: error: lane number incompatible with layout // CHECK-ARM64-ERROR: vector lane must be an integer in range // CHECK-ERROR: sqdmlsl2 v0.2d, v1.4s, v1.s[4] // CHECK-ERROR: ^ -// CHECK-AARCH64-ERROR: error: lane number incompatible with layout // CHECK-ARM64-ERROR: vector lane must be an integer in range // CHECK-ERROR: sqdmlsl2 v0.2d, v1.4s, v22.s[4] // CHECK-ERROR: ^ @@ -3493,35 +3393,27 @@ mul v0.4s, v1.4s, v22.s[4] mul v0.2d, v1.2d, v2.d[1] -// CHECK-AARCH64-ERROR: error: lane number incompatible with layout // CHECK-ARM64-ERROR: vector lane must be an integer in range // CHECK-ERROR: mul v0.4h, v1.4h, v2.h[8] // CHECK-ERROR: ^ -// CHECK-AARCH64-ERROR: error: lane number incompatible with layout // CHECK-ARM64-ERROR: error: invalid operand for instruction // CHECK-ERROR: mul v0.4h, v1.4h, v16.h[8] // CHECK-ERROR: ^ -// CHECK-AARCH64-ERROR: error: lane number incompatible with layout // CHECK-ARM64-ERROR: vector lane must be an integer in range // CHECK-ERROR: mul v0.8h, v1.8h, v2.h[8] // CHECK-ERROR: ^ -// CHECK-AARCH64-ERROR: error: lane number incompatible with layout // CHECK-ARM64-ERROR: invalid operand for instruction // CHECK-ERROR: mul v0.8h, v1.8h, v16.h[8] // CHECK-ERROR: ^ -// CHECK-AARCH64-ERROR: error: lane number incompatible with layout // CHECK-ARM64-ERROR: vector lane must be an integer in range // CHECK-ERROR: mul v0.2s, v1.2s, v2.s[4] // CHECK-ERROR: ^ -// CHECK-AARCH64-ERROR: error: lane number incompatible with layout // CHECK-ARM64-ERROR: vector lane must be an integer in range // CHECK-ERROR: mul v0.2s, v1.2s, v22.s[4] // CHECK-ERROR: ^ -// CHECK-AARCH64-ERROR: error: lane number incompatible with layout // CHECK-ARM64-ERROR: vector lane must be an integer in range // CHECK-ERROR: mul v0.4s, v1.4s, v2.s[4] // CHECK-ERROR: ^ -// CHECK-AARCH64-ERROR: error: lane number incompatible with layout // CHECK-ARM64-ERROR: vector lane must be an integer in range // CHECK-ERROR: mul v0.4s, v1.4s, v22.s[4] // CHECK-ERROR: ^ @@ -3540,27 +3432,21 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: fmul v0.4h, v1.4h, v2.h[4] // CHECK-ERROR: ^ -// CHECK-AARCH64-ERROR: error: lane number incompatible with layout // CHECK-ARM64-ERROR: vector lane must be an integer in range // CHECK-ERROR: fmul v0.2s, v1.2s, v2.s[4] // CHECK-ERROR: ^ -// CHECK-AARCH64-ERROR: error: lane number incompatible with layout // CHECK-ARM64-ERROR: vector lane must be an integer in range // CHECK-ERROR: fmul v0.2s, v1.2s, v22.s[4] // CHECK-ERROR: ^ -// CHECK-AARCH64-ERROR: error: lane number incompatible with layout // CHECK-ARM64-ERROR: vector lane must be an integer in range // CHECK-ERROR: fmul v0.4s, v1.4s, v2.s[4] // CHECK-ERROR: ^ -// CHECK-AARCH64-ERROR: error: lane number incompatible with layout // CHECK-ARM64-ERROR: vector lane must be an integer in range // CHECK-ERROR: fmul v0.4s, v1.4s, v22.s[4] // CHECK-ERROR: ^ -// CHECK-AARCH64-ERROR: error: lane number incompatible with layout // CHECK-ARM64-ERROR: vector lane must be an integer in range // CHECK-ERROR: fmul v0.2d, v1.2d, v2.d[2] // CHECK-ERROR: ^ -// CHECK-AARCH64-ERROR: error: lane number incompatible with layout // CHECK-ARM64-ERROR: vector lane must be an integer in range // CHECK-ERROR: fmul v0.2d, v1.2d, v22.d[2] // CHECK-ERROR: ^ @@ -3576,27 +3462,21 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: fmulx v0.4h, v1.4h, v2.h[4] // CHECK-ERROR: ^ -// CHECK-AARCH64-ERROR: error: lane number incompatible with layout // CHECK-ARM64-ERROR: vector lane must be an integer in range // CHECK-ERROR: fmulx v0.2s, v1.2s, v2.s[4] // CHECK-ERROR: ^ -// CHECK-AARCH64-ERROR: error: lane number incompatible with layout // CHECK-ARM64-ERROR: vector lane must be an integer in range // CHECK-ERROR: fmulx v0.2s, v1.2s, v22.s[4] // CHECK-ERROR: ^ -// CHECK-AARCH64-ERROR: error: lane number incompatible with layout // CHECK-ARM64-ERROR: vector lane must be an integer in range // CHECK-ERROR: fmulx v0.4s, v1.4s, v2.s[4] // CHECK-ERROR: ^ -// CHECK-AARCH64-ERROR: error: lane number incompatible with layout // CHECK-ARM64-ERROR: vector lane must be an integer in range // CHECK-ERROR: fmulx v0.4s, v1.4s, v22.s[4] // CHECK-ERROR: ^ -// CHECK-AARCH64-ERROR: error: lane number incompatible with layout // CHECK-ARM64-ERROR: vector lane must be an integer in range // CHECK-ERROR: fmulx v0.2d, v1.2d, v2.d[2] // CHECK-ERROR: ^ -// CHECK-AARCH64-ERROR: error: lane number incompatible with layout // CHECK-ARM64-ERROR: vector lane must be an integer in range // CHECK-ERROR: fmulx v0.2d, v1.2d, v22.d[2] // CHECK-ERROR: ^ @@ -3617,7 +3497,6 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: smull v0.4h, v1.4h, v2.h[2] // CHECK-ERROR: ^ -// CHECK-AARCH64-ERROR: error: lane number incompatible with layout // CHECK-ARM64-ERROR: vector lane must be an integer in range // CHECK-ERROR: smull v0.4s, v1.4h, v2.h[8] // CHECK-ERROR: ^ @@ -3627,18 +3506,15 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: smull v0.2s, v1.2s, v2.s[2] // CHECK-ERROR: ^ -// CHECK-AARCH64-ERROR: error: lane number incompatible with layout // CHECK-ARM64-ERROR: vector lane must be an integer in range // CHECK-ERROR: smull v0.2d, v1.2s, v2.s[4] // CHECK-ERROR: ^ -// CHECK-AARCH64-ERROR: error: lane number incompatible with layout // CHECK-ARM64-ERROR: vector lane must be an integer in range // CHECK-ERROR: smull v0.2d, v1.2s, v22.s[4] // CHECK-ERROR: ^ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: smull2 v0.4h, v1.8h, v2.h[2] // CHECK-ERROR: ^ -// CHECK-AARCH64-ERROR: error: lane number incompatible with layout // CHECK-ARM64-ERROR: vector lane must be an integer in range // CHECK-ERROR: smull2 v0.4s, v1.8h, v2.h[8] // CHECK-ERROR: ^ @@ -3648,11 +3524,9 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: smull2 v0.2s, v1.4s, v2.s[2] // CHECK-ERROR: ^ -// CHECK-AARCH64-ERROR: error: lane number incompatible with layout // CHECK-ARM64-ERROR: vector lane must be an integer in range // CHECK-ERROR: smull2 v0.2d, v1.4s, v2.s[4] // CHECK-ERROR: ^ -// CHECK-AARCH64-ERROR: error: lane number incompatible with layout // CHECK-ARM64-ERROR: vector lane must be an integer in range // CHECK-ERROR: smull2 v0.2d, v1.4s, v22.s[4] // CHECK-ERROR: ^ @@ -3673,7 +3547,6 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: umull v0.4h, v1.4h, v2.h[2] // CHECK-ERROR: ^ -// CHECK-AARCH64-ERROR: error: lane number incompatible with layout // CHECK-ARM64-ERROR: vector lane must be an integer in range // CHECK-ERROR: umull v0.4s, v1.4h, v2.h[8] // CHECK-ERROR: ^ @@ -3683,18 +3556,15 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: umull v0.2s, v1.2s, v2.s[2] // CHECK-ERROR: ^ -// CHECK-AARCH64-ERROR: error: lane number incompatible with layout // CHECK-ARM64-ERROR: vector lane must be an integer in range // CHECK-ERROR: umull v0.2d, v1.2s, v2.s[4] // CHECK-ERROR: ^ -// CHECK-AARCH64-ERROR: error: lane number incompatible with layout // CHECK-ARM64-ERROR: vector lane must be an integer in range // CHECK-ERROR: umull v0.2d, v1.2s, v22.s[4] // CHECK-ERROR: ^ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: umull2 v0.4h, v1.8h, v2.h[2] // CHECK-ERROR: ^ -// CHECK-AARCH64-ERROR: error: lane number incompatible with layout // CHECK-ARM64-ERROR: vector lane must be an integer in range // CHECK-ERROR: umull2 v0.4s, v1.8h, v2.h[8] // CHECK-ERROR: ^ @@ -3704,11 +3574,9 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: umull2 v0.2s, v1.4s, v2.s[2] // CHECK-ERROR: ^ -// CHECK-AARCH64-ERROR: error: lane number incompatible with layout // CHECK-ARM64-ERROR: vector lane must be an integer in range // CHECK-ERROR: umull2 v0.2d, v1.4s, v2.s[4] // CHECK-ERROR: ^ -// CHECK-AARCH64-ERROR: error: lane number incompatible with layout // CHECK-ARM64-ERROR: vector lane must be an integer in range // CHECK-ERROR: umull2 v0.2d, v1.4s, v22.s[4] // CHECK-ERROR: ^ @@ -3729,7 +3597,6 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: sqdmull v0.4h, v1.4h, v2.h[2] // CHECK-ERROR: ^ -// CHECK-AARCH64-ERROR: error: lane number incompatible with layout // CHECK-ARM64-ERROR: vector lane must be an integer in range // CHECK-ERROR: sqdmull v0.4s, v1.4h, v2.h[8] // CHECK-ERROR: ^ @@ -3739,18 +3606,15 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: sqdmull v0.2s, v1.2s, v2.s[2] // CHECK-ERROR: ^ -// CHECK-AARCH64-ERROR: error: lane number incompatible with layout // CHECK-ARM64-ERROR: vector lane must be an integer in range // CHECK-ERROR: sqdmull v0.2d, v1.2s, v2.s[4] // CHECK-ERROR: ^ -// CHECK-AARCH64-ERROR: error: lane number incompatible with layout // CHECK-ARM64-ERROR: vector lane must be an integer in range // CHECK-ERROR: sqdmull v0.2d, v1.2s, v22.s[4] // CHECK-ERROR: ^ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: sqdmull2 v0.4h, v1.8h, v2.h[2] // CHECK-ERROR: ^ -// CHECK-AARCH64-ERROR: error: lane number incompatible with layout // CHECK-ARM64-ERROR: vector lane must be an integer in range // CHECK-ERROR: sqdmull2 v0.4s, v1.8h, v2.h[8] // CHECK-ERROR: ^ @@ -3760,11 +3624,9 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: sqdmull2 v0.2s, v1.4s, v2.s[2] // CHECK-ERROR: ^ -// CHECK-AARCH64-ERROR: error: lane number incompatible with layout // CHECK-ARM64-ERROR: vector lane must be an integer in range // CHECK-ERROR: sqdmull2 v0.2d, v1.4s, v2.s[4] // CHECK-ERROR: ^ -// CHECK-AARCH64-ERROR: error: lane number incompatible with layout // CHECK-ARM64-ERROR: vector lane must be an integer in range // CHECK-ERROR: sqdmull2 v0.2d, v1.4s, v22.s[4] // CHECK-ERROR: ^ @@ -3779,33 +3641,27 @@ sqdmulh v0.4s, v1.4s, v22.s[4] sqdmulh v0.2d, v1.2d, v22.d[1] -// CHECK-AARCH64-ERROR: error: lane number incompatible with layout // CHECK-ARM64-ERROR: vector lane must be an integer in range // CHECK-ERROR: sqdmulh v0.4h, v1.4h, v2.h[8] // CHECK-ERROR: ^ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: sqdmulh v0.4h, v1.4h, v16.h[2] // CHECK-ERROR: ^ -// CHECK-AARCH64-ERROR: error: lane number incompatible with layout // CHECK-ARM64-ERROR: vector lane must be an integer in range // CHECK-ERROR: sqdmulh v0.8h, v1.8h, v2.h[8] // CHECK-ERROR: ^ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: sqdmulh v0.8h, v1.8h, v16.h[2] // CHECK-ERROR: ^ -// CHECK-AARCH64-ERROR: error: lane number incompatible with layout // CHECK-ARM64-ERROR: vector lane must be an integer in range // CHECK-ERROR: sqdmulh v0.2s, v1.2s, v2.s[4] // CHECK-ERROR: ^ -// CHECK-AARCH64-ERROR: error: lane number incompatible with layout // CHECK-ARM64-ERROR: vector lane must be an integer in range // CHECK-ERROR: sqdmulh v0.2s, v1.2s, v22.s[4] // CHECK-ERROR: ^ -// CHECK-AARCH64-ERROR: error: lane number incompatible with layout // CHECK-ARM64-ERROR: vector lane must be an integer in range // CHECK-ERROR: sqdmulh v0.4s, v1.4s, v2.s[4] // CHECK-ERROR: ^ -// CHECK-AARCH64-ERROR: error: lane number incompatible with layout // CHECK-ARM64-ERROR: vector lane must be an integer in range // CHECK-ERROR: sqdmulh v0.4s, v1.4s, v22.s[4] // CHECK-ERROR: ^ @@ -3823,33 +3679,27 @@ sqrdmulh v0.4s, v1.4s, v22.s[4] sqrdmulh v0.2d, v1.2d, v22.d[1] -// CHECK-AARCH64-ERROR: error: lane number incompatible with layout // CHECK-ARM64-ERROR: vector lane must be an integer in range // CHECK-ERROR: sqrdmulh v0.4h, v1.4h, v2.h[8] // CHECK-ERROR: ^ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: sqrdmulh v0.4h, v1.4h, v16.h[2] // CHECK-ERROR: ^ -// CHECK-AARCH64-ERROR: error: lane number incompatible with layout // CHECK-ARM64-ERROR: vector lane must be an integer in range // CHECK-ERROR: sqrdmulh v0.8h, v1.8h, v2.h[8] // CHECK-ERROR: ^ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: sqrdmulh v0.8h, v1.8h, v16.h[2] // CHECK-ERROR: ^ -// CHECK-AARCH64-ERROR: error: lane number incompatible with layout // CHECK-ARM64-ERROR: vector lane must be an integer in range // CHECK-ERROR: sqrdmulh v0.2s, v1.2s, v2.s[4] // CHECK-ERROR: ^ -// CHECK-AARCH64-ERROR: error: lane number incompatible with layout // CHECK-ARM64-ERROR: vector lane must be an integer in range // CHECK-ERROR: sqrdmulh v0.2s, v1.2s, v22.s[4] // CHECK-ERROR: ^ -// CHECK-AARCH64-ERROR: error: lane number incompatible with layout // CHECK-ARM64-ERROR: vector lane must be an integer in range // CHECK-ERROR: sqrdmulh v0.4s, v1.4s, v2.s[4] // CHECK-ERROR: ^ -// CHECK-AARCH64-ERROR: error: lane number incompatible with layout // CHECK-ARM64-ERROR: vector lane must be an integer in range // CHECK-ERROR: sqrdmulh v0.4s, v1.4s, v22.s[4] // CHECK-ERROR: ^ @@ -4068,15 +3918,12 @@ ld1 {v4}, [x0] ld1 {v32.16b}, [x0] ld1 {v15.8h}, [x32] -// CHECK-AARCH64-ERROR: error: expected vector type register // CHECK-ARM64-ERROR: error: vector register expected // CHECK-ERROR: ld1 {x3}, [x2] // CHECK-ERROR: ^ -// CHECK-AARCH64-ERROR: error: expected vector type register // CHECK-ARM64-ERROR: error: invalid operand for instruction // CHECK-ERROR: ld1 {v4}, [x0] // CHECK-ERROR: ^ -// CHECK-AARCH64-ERROR: error: expected vector type register // CHECK-ARM64-ERROR: error: vector register expected // CHECK-ERROR: ld1 {v32.16b}, [x0] // CHECK-ERROR: ^ @@ -4091,14 +3938,12 @@ ld1 {v1.8h-v1.8h}, [x0] ld1 {v15.8h-v17.4h}, [x15] ld1 {v0.8b-v2.8b, [x0] -// CHECK-AARCH64-ERROR: error: invalid space between two vectors // CHECK-ARM64-ERROR: error: registers must be sequential // CHECK-ERROR: ld1 {v0.16b, v2.16b}, [x0] // CHECK-ERROR: ^ // CHECK-ERROR: error: invalid number of vectors // CHECK-ERROR: ld1 {v0.8h, v1.8h, v2.8h, v3.8h, v4.8h}, [x0] // CHECK-ERROR: ^ -// CHECK-AARCH64-ERROR: error: '{' expected // CHECK-ARM64-ERROR: error: unexpected token in argument list // CHECK-ERROR: ld1 v0.8b, v1.8b}, [x0] // CHECK-ERROR: ^ @@ -4108,7 +3953,6 @@ // CHECK-ERROR: error: invalid number of vectors // CHECK-ERROR: ld1 {v1.8h-v1.8h}, [x0] // CHECK-ERROR: ^ -// CHECK-AARCH64-ERROR: error: expected the same vector layout // CHECK-ARM64-ERROR: error: mismatched register size suffix // CHECK-ERROR: ld1 {v15.8h-v17.4h}, [x15] // CHECK-ERROR: ^ @@ -4121,18 +3965,14 @@ ld2 {v15.4h, v16.4h, v17.4h}, [x32] ld2 {v15.8h-v16.4h}, [x15] ld2 {v0.2d-v2.2d}, [x0] -// CHECK-AARCH64-ERROR: error: invalid space between two vectors // CHECK-ARM64-ERROR: error: mismatched register size suffix // CHECK-ERROR: ld2 {v15.8h, v16.4h}, [x15] // CHECK-ERROR: ^ -// CHECK-AARCH64-ERROR: error: invalid space between two vectors // CHECK-ARM64-ERROR: error: registers must be sequential // CHECK-ERROR: ld2 {v0.8b, v2.8b}, [x0] // CHECK-ERROR: ^ -// CHECK-AARCH64: error: invalid operand for instruction // CHECK-ERROR: ld2 {v15.4h, v16.4h, v17.4h}, [x32] // CHECK-ERROR: ^ -// CHECK-AARCH64-ERROR: error: expected the same vector layout // CHECK-ARM64-ERROR: error: mismatched register size suffix // CHECK-ERROR: ld2 {v15.8h-v16.4h}, [x15] // CHECK-ERROR: ^ @@ -4145,19 +3985,15 @@ ld3 {v0.8b, v2.8b, v3.8b}, [x0] ld3 {v15.8h-v17.4h}, [x15] ld3 {v31.4s-v2.4s}, [sp] -// CHECK-AARCH64-ERROR: error: invalid space between two vectors // CHECK-ARM64-ERROR: error: mismatched register size suffix // CHECK-ERROR: ld3 {v15.8h, v16.8h, v17.4h}, [x15] // CHECK-ERROR: ^ -// CHECK-AARCH64-ERROR: error: expected vector type register // CHECK-ARM64-ERROR: error: mismatched register size suffix // CHECK-ERROR: ld3 {v0.8b, v1,8b, v2.8b, v3.8b}, [x0] // CHECK-ERROR: ^ -// CHECK-AARCH64-ERROR: error: invalid space between two vectors // CHECK-ARM64-ERROR: error: registers must be sequential // CHECK-ERROR: ld3 {v0.8b, v2.8b, v3.8b}, [x0] // CHECK-ERROR: ^ -// CHECK-AARCH64-ERROR: error: expected the same vector layout // CHECK-ARM64-ERROR: error: mismatched register size suffix // CHECK-ERROR: ld3 {v15.8h-v17.4h}, [x15] // CHECK-ERROR: ^ @@ -4170,18 +4006,15 @@ ld4 {v15.4h, v16.4h, v17.4h, v18.4h, v19.4h}, [x31] ld4 {v15.8h-v18.4h}, [x15] ld4 {v31.2s-v1.2s}, [x31] -// CHECK-AARCH64-ERROR: error: invalid space between two vectors // CHECK-ARM64-ERROR: error: mismatched register size suffix // CHECK-ERROR: ld4 {v15.8h, v16.8h, v17.4h, v18.8h}, [x15] // CHECK-ERROR: ^ -// CHECK-AARCH64-ERROR: error: invalid space between two vectors // CHECK-ARM64-ERROR: error: registers must be sequential // CHECK-ERROR: ld4 {v0.8b, v2.8b, v3.8b, v4.8b}, [x0] // CHECK-ERROR: ^ // CHECK-ERROR: error: invalid number of vectors // CHECK-ERROR: ld4 {v15.4h, v16.4h, v17.4h, v18.4h, v19.4h}, [x31] // CHECK-ERROR: ^ -// CHECK-AARCH64-ERROR: error: expected the same vector layout // CHECK-ARM64-ERROR: error: mismatched register size suffix // CHECK-ERROR: ld4 {v15.8h-v18.4h}, [x15] // CHECK-ERROR: ^ @@ -4193,15 +4026,12 @@ st1 {v4}, [x0] st1 {v32.16b}, [x0] st1 {v15.8h}, [x32] -// CHECK-AARCH64-ERROR: error: expected vector type register // CHECK-ARM64-ERROR: error: vector register expected // CHECK-ERROR: st1 {x3}, [x2] // CHECK-ERROR: ^ -// CHECK-AARCH64-ERROR: error: expected vector type register // CHECK-ARM64-ERROR: error: invalid operand for instruction // CHECK-ERROR: st1 {v4}, [x0] // CHECK-ERROR: ^ -// CHECK-AARCH64-ERROR: error: expected vector type register // CHECK-ARM64-ERROR: error: vector register expected // CHECK-ERROR: st1 {v32.16b}, [x0] // CHECK-ERROR: ^ @@ -4216,14 +4046,12 @@ st1 {v1.8h-v1.8h}, [x0] st1 {v15.8h-v17.4h}, [x15] st1 {v0.8b-v2.8b, [x0] -// CHECK-AARCH64-ERROR: error: invalid space between two vectors // CHECK-ARM64-ERROR: error: registers must be sequential // CHECK-ERROR: st1 {v0.16b, v2.16b}, [x0] // CHECK-ERROR: ^ // CHECK-ERROR: error: invalid number of vectors // CHECK-ERROR: st1 {v0.8h, v1.8h, v2.8h, v3.8h, v4.8h}, [x0] // CHECK-ERROR: ^ -// CHECK-AARCH64-ERROR: error: '{' expected // CHECK-ARM64-ERROR: error: unexpected token in argument list // CHECK-ERROR: st1 v0.8b, v1.8b}, [x0] // CHECK-ERROR: ^ @@ -4233,7 +4061,6 @@ // CHECK-ERROR: error: invalid number of vectors // CHECK-ERROR: st1 {v1.8h-v1.8h}, [x0] // CHECK-ERROR: ^ -// CHECK-AARCH64-ERROR: error: expected the same vector layout // CHECK-ARM64-ERROR: error: mismatched register size suffix // CHECK-ERROR: st1 {v15.8h-v17.4h}, [x15] // CHECK-ERROR: ^ @@ -4246,18 +4073,15 @@ st2 {v15.4h, v16.4h, v17.4h}, [x30] st2 {v15.8h-v16.4h}, [x15] st2 {v0.2d-v2.2d}, [x0] -// CHECK-AARCH64-ERROR: error: invalid space between two vectors // CHECK-ARM64-ERROR: error: mismatched register size suffix // CHECK-ERROR: st2 {v15.8h, v16.4h}, [x15] // CHECK-ERROR: ^ -// CHECK-AARCH64-ERROR: error: invalid space between two vectors // CHECK-ARM64-ERROR: error: registers must be sequential // CHECK-ERROR: st2 {v0.8b, v2.8b}, [x0] // CHECK-ERROR: ^ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: st2 {v15.4h, v16.4h, v17.4h}, [x30] // CHECK-ERROR: ^ -// CHECK-AARCH64-ERROR: error: expected the same vector layout // CHECK-ARM64-ERROR: error: mismatched register size suffix // CHECK-ERROR: st2 {v15.8h-v16.4h}, [x15] // CHECK-ERROR: ^ @@ -4270,19 +4094,15 @@ st3 {v0.8b, v2.8b, v3.8b}, [x0] st3 {v15.8h-v17.4h}, [x15] st3 {v31.4s-v2.4s}, [sp] -// CHECK-AARCH64-ERROR: error: invalid space between two vectors // CHECK-ARM64-ERROR: error: mismatched register size suffix // CHECK-ERROR: st3 {v15.8h, v16.8h, v17.4h}, [x15] // CHECK-ERROR: ^ -// CHECK-AARCH64-ERROR: error: expected vector type register // CHECK-ARM64-ERROR: error: mismatched register size suffix // CHECK-ERROR: st3 {v0.8b, v1,8b, v2.8b, v3.8b}, [x0] // CHECK-ERROR: ^ -// CHECK-AARCH64-ERROR: error: invalid space between two vectors // CHECK-ARM64-ERROR: error: registers must be sequential // CHECK-ERROR: st3 {v0.8b, v2.8b, v3.8b}, [x0] // CHECK-ERROR: ^ -// CHECK-AARCH64-ERROR: error: expected the same vector layout // CHECK-ARM64-ERROR: error: mismatched register size suffix // CHECK-ERROR: st3 {v15.8h-v17.4h}, [x15] // CHECK-ERROR: ^ @@ -4295,18 +4115,15 @@ st4 {v15.4h, v16.4h, v17.4h, v18.4h, v19.4h}, [x31] st4 {v15.8h-v18.4h}, [x15] st4 {v31.2s-v1.2s}, [x31] -// CHECK-AARCH64-ERROR: error: invalid space between two vectors // CHECK-ARM64-ERROR: error: mismatched register size suffix // CHECK-ERROR: st4 {v15.8h, v16.8h, v17.4h, v18.8h}, [x15] // CHECK-ERROR: ^ -// CHECK-AARCH64-ERROR: error: invalid space between two vectors // CHECK-ARM64-ERROR: error: registers must be sequential // CHECK-ERROR: st4 {v0.8b, v2.8b, v3.8b, v4.8b}, [x0] // CHECK-ERROR: ^ // CHECK-ERROR: error: invalid number of vectors // CHECK-ERROR: st4 {v15.4h, v16.4h, v17.4h, v18.4h, v19.4h}, [x31] // CHECK-ERROR: ^ -// CHECK-AARCH64-ERROR: error: expected the same vector layout // CHECK-ARM64-ERROR: error: mismatched register size suffix // CHECK-ERROR: st4 {v15.8h-v18.4h}, [x15] // CHECK-ERROR: ^ @@ -4324,7 +4141,6 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: ld1 {v0.16b}, [x0], #8 // CHECK-ERROR: ^ -// CHECK-AARCH64-ERROR: error: expected vector type register // CHECK-ARM64-ERROR: error: invalid vector kind qualifier // CHECK-ERROR: ld1 {v0.8h, v1.16h}, [x0], x1 // CHECK-ERROR: ^ @@ -4341,7 +4157,6 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: ld3 {v5.2s, v6.2s, v7.2s}, [x1], #48 // CHECK-ERROR: ^ -// CHECK-AARCH64-ERROR: error: invalid space between two vectors // CHECK-ARM64-ERROR: error: mismatched register size suffix // CHECK-ERROR: ld4 {v31.2d, v0.2d, v1.2d, v2.1d}, [x3], x1 // CHECK-ERROR: ^ @@ -4352,7 +4167,6 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: st1 {v0.16b}, [x0], #8 // CHECK-ERROR: ^ -// CHECK-AARCH64-ERROR: error: expected vector type register // CHECK-ARM64-ERROR: error: invalid vector kind qualifier // CHECK-ERROR: st1 {v0.8h, v1.16h}, [x0], x1 // CHECK-ERROR: ^ @@ -4369,7 +4183,6 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: st3 {v5.2s, v6.2s, v7.2s}, [x1], #48 // CHECK-ERROR: ^ -// CHECK-AARCH64-ERROR: error: invalid space between two vectors // CHECK-ARM64-ERROR: error: mismatched register size suffix // CHECK-ERROR: st4 {v31.2d, v0.2d, v1.2d, v2.1d}, [x3], x1 // CHECK-ERROR: ^ @@ -4382,18 +4195,15 @@ ld2r {v31.4s, v0.2s}, [sp] ld3r {v0.8b, v1.8b, v2.8b, v3.8b}, [x0] ld4r {v31.2s, v0.2s, v1.2d, v2.2s}, [sp] -// CHECK-AARCH64-ERROR: error: expected vector type register // CHECK-ARM64-ERROR: error: vector register expected // CHECK-ERROR: ld1r {x1}, [x0] // CHECK-ERROR: ^ -// CHECK-AARCH64-ERROR: error: invalid space between two vectors // CHECK-ARM64-ERROR: error: mismatched register size suffix // CHECK-ERROR: ld2r {v31.4s, v0.2s}, [sp] // CHECK-ERROR: ^ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: ld3r {v0.8b, v1.8b, v2.8b, v3.8b}, [x0] // CHECK-ERROR: ^ -// CHECK-AARCH64-ERROR: error: invalid space between two vectors // CHECK-ARM64-ERROR: error: mismatched register size suffix // CHECK-ERROR: ld4r {v31.2s, v0.2s, v1.2d, v2.2s}, [sp] // CHECK-ERROR: ^ @@ -4406,19 +4216,15 @@ ld2 {v15.h, v16.h}[8], [x15] ld3 {v31.s, v0.s, v1.s}[-1], [sp] ld4 {v0.d, v1.d, v2.d, v3.d}[2], [x0] -// CHECK-AARCH64-ERROR:: error: lane number incompatible with layout // CHECK-ARM64-ERROR: vector lane must be an integer in range // CHECK-ERROR: ld1 {v0.b}[16], [x0] // CHECK-ERROR: ^ -// CHECK-AARCH64-ERROR: error: lane number incompatible with layout // CHECK-ARM64-ERROR: vector lane must be an integer in range // CHECK-ERROR: ld2 {v15.h, v16.h}[8], [x15] // CHECK-ERROR: ^ -// CHECK-AARCH64-ERROR: error: expected lane number // CHECK-ARM64-ERROR: error: vector lane must be an integer in range // CHECK-ERROR: ld3 {v31.s, v0.s, v1.s}[-1], [sp] // CHECK-ERROR: ^ -// CHECK-AARCH64-ERROR: error: lane number incompatible with layout // CHECK-ARM64-ERROR: vector lane must be an integer in range // CHECK-ERROR: ld4 {v0.d, v1.d, v2.d, v3.d}[2], [x0] // CHECK-ERROR: ^ @@ -4427,18 +4233,15 @@ st2 {v31.s, v0.s}[3], [8] st3 {v15.h, v16.h, v17.h}[-1], [x15] st4 {v0.d, v1.d, v2.d, v3.d}[2], [x0] -// CHECK-AARCH64-ERROR:: error: lane number incompatible with layout // CHECK-ARM64-ERROR: vector lane must be an integer in range // CHECK-ERROR: st1 {v0.d}[16], [x0] // CHECK-ERROR: ^ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: st2 {v31.s, v0.s}[3], [8] // CHECK-ERROR: ^ -// CHECK-AARCH64-ERROR: error: expected lane number // CHECK-ARM64-ERROR: error: vector lane must be an integer in range // CHECK-ERROR: st3 {v15.h, v16.h, v17.h}[-1], [x15] // CHECK-ERROR: ^ -// CHECK-AARCH64-ERROR: lane number incompatible with layout // CHECK-ARM64-ERROR: vector lane must be an integer in range // CHECK-ERROR: st4 {v0.d, v1.d, v2.d, v3.d}[2], [x0] // CHECK-ERROR: ^ @@ -4478,7 +4281,6 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: ld2 {v15.h, v16.h}[0], [x15], #3 // CHECK-ERROR: ^ -// CHECK-AARCH64-ERROR: error: expected the same vector layout // CHECK-ARM64-ERROR: error: mismatched register size suffix // CHECK-ERROR: ld3 {v31.s, v0.s, v1.d}[0], [sp], x9 // CHECK-ERROR: ^ @@ -4513,19 +4315,15 @@ ins v20.s[1], s30 ins v1.d[0], d7 -// CHECK-AARCH64-ERROR: error: lane number incompatible with layout // CHECK-ARM64-ERROR: vector lane must be an integer in range // CHECK-ERROR: ins v2.b[16], w1 // CHECK-ERROR: ^ -// CHECK-AARCH64-ERROR: error: lane number incompatible with layout // CHECK-ARM64-ERROR: vector lane must be an integer in range // CHECK-ERROR: ins v7.h[8], w14 // CHECK-ERROR: ^ -// CHECK-AARCH64-ERROR: error: lane number incompatible with layout // CHECK-ARM64-ERROR: vector lane must be an integer in range // CHECK-ERROR: ins v20.s[5], w30 // CHECK-ERROR: ^ -// CHECK-AARCH64-ERROR: error: lane number incompatible with layout // CHECK-ARM64-ERROR: vector lane must be an integer in range // CHECK-ERROR: ins v1.d[2], x7 // CHECK-ERROR: ^ @@ -4553,23 +4351,18 @@ smov x14, v6.d[1] smov x20, v9.d[0] -// CHECK-AARCH64-ERROR error: lane number incompatible with layout // CHECK-ARM64-ERROR: vector lane must be an integer in range // CHECK-ERROR smov w1, v0.b[16] // CHECK-ERROR ^ -// CHECK-AARCH64-ERROR error: lane number incompatible with layout // CHECK-ARM64-ERROR: vector lane must be an integer in range // CHECK-ERROR smov w14, v6.h[8] // CHECK-ERROR ^ -// CHECK-AARCH64-ERROR error: lane number incompatible with layout // CHECK-ARM64-ERROR: vector lane must be an integer in range // CHECK-ERROR smov x1, v0.b[16] // CHECK-ERROR ^ -// CHECK-AARCH64-ERROR error: lane number incompatible with layout // CHECK-ARM64-ERROR: vector lane must be an integer in range // CHECK-ERROR smov x14, v6.h[8] // CHECK-ERROR ^ -// CHECK-AARCH64-ERROR error: lane number incompatible with layout // CHECK-ARM64-ERROR: vector lane must be an integer in range // CHECK-ERROR smov x20, v9.s[5] // CHECK-ERROR ^ @@ -4597,19 +4390,15 @@ umov s20, v9.s[2] umov d7, v18.d[1] -// CHECK-AARCH64-ERROR error: lane number incompatible with layout // CHECK-ARM64-ERROR: vector lane must be an integer in range // CHECK-ERROR umov w1, v0.b[16] // CHECK-ERROR ^ -// CHECK-AARCH64-ERROR error: lane number incompatible with layout // CHECK-ARM64-ERROR: vector lane must be an integer in range // CHECK-ERROR umov w14, v6.h[8] // CHECK-ERROR ^ -// CHECK-AARCH64-ERROR error: lane number incompatible with layout // CHECK-ARM64-ERROR: vector lane must be an integer in range // CHECK-ERROR umov w20, v9.s[5] // CHECK-ERROR ^ -// CHECK-AARCH64-ERROR error: lane number incompatible with layout // CHECK-ARM64-ERROR: vector lane must be an integer in range // CHECK-ERROR umov x7, v18.d[3] // CHECK-ERROR ^ @@ -5026,7 +4815,6 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: sqdmlal s17, h27, s12 // CHECK-ERROR: ^ -// CHECK-AARCH64-ERROR: error: too few operands for instruction // CHECK-ARM64-ERROR: error: invalid operand for instruction // CHECK-ERROR: sqdmlal d19, s24, d12 // CHECK-ERROR: ^ @@ -5041,7 +4829,6 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: sqdmlsl s14, h12, s25 // CHECK-ERROR: ^ -// CHECK-AARCH64-ERROR: error: too few operands for instruction // CHECK-ARM64-ERROR: error: invalid operand for instruction // CHECK-ERROR: sqdmlsl d12, s23, d13 // CHECK-ERROR: ^ @@ -5056,7 +4843,6 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: sqdmull s12, h22, s12 // CHECK-ERROR: ^ -// CHECK-AARCH64-ERROR: error: too few operands for instruction // CHECK-ARM64-ERROR: error: invalid operand for instruction // CHECK-ERROR: sqdmull d15, s22, d12 // CHECK-ERROR: ^ @@ -7099,7 +6885,6 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: fmul h0, h1, v1.s[0] // CHECK-ERROR: ^ -// CHECK-AARCH64-ERROR: error: lane number incompatible with layout // CHECK-ARM64-ERROR: vector lane must be an integer in range // CHECK-ERROR: fmul s2, s29, v10.s[4] // CHECK-ERROR: ^ @@ -7119,7 +6904,6 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: fmulx h0, h1, v1.d[0] // CHECK-ERROR: ^ -// CHECK-AARCH64-ERROR: error: lane number incompatible with layout // CHECK-ARM64-ERROR: vector lane must be an integer in range // CHECK-ERROR: fmulx d2, d29, v10.d[3] // CHECK-ERROR: ^ @@ -7139,7 +6923,6 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: fmla d30, s11, v1.d[1] // CHECK-ERROR: ^ -// CHECK-AARCH64-ERROR: error: lane number incompatible with layout // CHECK-ARM64-ERROR: vector lane must be an integer in range // CHECK-ERROR: fmla s16, s22, v16.s[5] // CHECK-ERROR: ^ @@ -7159,7 +6942,6 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: fmls h7, h17, v26.s[2] // CHECK-ERROR: ^ -// CHECK-AARCH64-ERROR: error: expected lane number // CHECK-ARM64-ERROR: error: vector lane must be an integer in range [0, 1] // CHECK-ERROR: fmls d16, d22, v16.d[-1] // CHECK-ERROR: ^ @@ -7182,7 +6964,6 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: sqdmlal s8, s9, v14.s[1] // CHECK-ERROR: ^ -// CHECK-AARCH64-ERROR: error: lane number incompatible with layout // CHECK-ARM64-ERROR: vector lane must be an integer in range // CHECK-ERROR: sqdmlal d4, s5, v1.s[5] // CHECK-ERROR: ^ @@ -7208,7 +6989,6 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: sqdmlsl d1, h1, v13.s[0] // CHECK-ERROR: ^ -// CHECK-AARCH64-ERROR: error: lane number incompatible with layout // CHECK-ARM64-ERROR: vector lane must be an integer in range // CHECK-ERROR: sqdmlsl d1, s1, v13.s[4] // CHECK-ERROR: ^ @@ -7236,7 +7016,6 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: sqdmull s1, s1, v4.s[0] // CHECK-ERROR: ^ -// CHECK-AARCH64-ERROR: error: lane number incompatible with layout // CHECK-ARM64-ERROR: vector lane must be an integer in range // CHECK-ERROR: sqdmull s12, h17, v9.h[9] // CHECK-ERROR: ^ @@ -7262,7 +7041,6 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: sqdmulh s25, s26, v27.h[3] // CHECK-ERROR: ^ -// CHECK-AARCH64-ERROR: error: lane number incompatible with layout // CHECK-ARM64-ERROR: vector lane must be an integer in range // CHECK-ERROR: sqdmulh s25, s26, v27.s[4] // CHECK-ERROR: ^ @@ -7288,7 +7066,6 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: sqrdmulh s5, h6, v7.s[2] // CHECK-ERROR: ^ -// CHECK-AARCH64-ERROR: error: lane number incompatible with layout // CHECK-ARM64-ERROR: vector lane must be an integer in range // CHECK-ERROR: sqrdmulh h31, h30, v14.h[9] // CHECK-ERROR: ^ @@ -7321,19 +7098,15 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: dup d0, v17.s[3] // CHECK-ERROR: ^ -// CHECK-AARCH64-ERROR: error: lane number incompatible with layout // CHECK-ARM64-ERROR: vector lane must be an integer in range // CHECK-ERROR: dup d0, v17.d[4] // CHECK-ERROR: ^ -// CHECK-AARCH64-ERROR: error: lane number incompatible with layout // CHECK-ARM64-ERROR: vector lane must be an integer in range // CHECK-ERROR: dup s0, v1.s[7] // CHECK-ERROR: ^ -// CHECK-AARCH64-ERROR: error: lane number incompatible with layout // CHECK-ARM64-ERROR: vector lane must be an integer in range // CHECK-ERROR: dup h0, v31.h[16] // CHECK-ERROR: ^ -// CHECK-AARCH64-ERROR: error: lane number incompatible with layout // CHECK-ARM64-ERROR: vector lane must be an integer in range // CHECK-ERROR: dup b1, v3.b[16] // CHECK-ERROR: ^ diff --git a/llvm/test/MC/AArch64/neon-extract.s b/llvm/test/MC/AArch64/neon-extract.s index fbfc048de96..1daa46d096e 100644 --- a/llvm/test/MC/AArch64/neon-extract.s +++ b/llvm/test/MC/AArch64/neon-extract.s @@ -1,4 +1,3 @@ -// RUN: llvm-mc -triple=aarch64 -mattr=+neon -show-encoding < %s | FileCheck %s // RUN: llvm-mc -triple=arm64 -mattr=+neon -show-encoding < %s | FileCheck %s // Check that the assembler can handle the documented syntax for AArch64 diff --git a/llvm/test/MC/AArch64/neon-facge-facgt.s b/llvm/test/MC/AArch64/neon-facge-facgt.s index bb739fa1859..799b85ff42f 100644 --- a/llvm/test/MC/AArch64/neon-facge-facgt.s +++ b/llvm/test/MC/AArch64/neon-facge-facgt.s @@ -1,4 +1,3 @@ -// RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s // RUN: llvm-mc -triple arm64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s // Check that the assembler can handle the documented syntax for AArch64 diff --git a/llvm/test/MC/AArch64/neon-frsqrt-frecp.s b/llvm/test/MC/AArch64/neon-frsqrt-frecp.s index ec3b64bfa59..56bc47154a0 100644 --- a/llvm/test/MC/AArch64/neon-frsqrt-frecp.s +++ b/llvm/test/MC/AArch64/neon-frsqrt-frecp.s @@ -1,4 +1,3 @@ -// RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s // RUN: llvm-mc -triple arm64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s // Check that the assembler can handle the documented syntax for AArch64 diff --git a/llvm/test/MC/AArch64/neon-halving-add-sub.s b/llvm/test/MC/AArch64/neon-halving-add-sub.s index 8e36b20386e..19b56ced3e6 100644 --- a/llvm/test/MC/AArch64/neon-halving-add-sub.s +++ b/llvm/test/MC/AArch64/neon-halving-add-sub.s @@ -1,4 +1,3 @@ -// RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s // RUN: llvm-mc -triple arm64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s // Check that the assembler can handle the documented syntax for AArch64 diff --git a/llvm/test/MC/AArch64/neon-max-min-pairwise.s b/llvm/test/MC/AArch64/neon-max-min-pairwise.s index 4421be4ed0a..e48f9753586 100644 --- a/llvm/test/MC/AArch64/neon-max-min-pairwise.s +++ b/llvm/test/MC/AArch64/neon-max-min-pairwise.s @@ -1,4 +1,3 @@ -// RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s // RUN: llvm-mc -triple arm64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s // Check that the assembler can handle the documented syntax for AArch64 diff --git a/llvm/test/MC/AArch64/neon-max-min.s b/llvm/test/MC/AArch64/neon-max-min.s index 3700f755394..8cc4ac86e65 100644 --- a/llvm/test/MC/AArch64/neon-max-min.s +++ b/llvm/test/MC/AArch64/neon-max-min.s @@ -1,4 +1,3 @@ -// RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s // RUN: llvm-mc -triple arm64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s // Check that the assembler can handle the documented syntax for AArch64 diff --git a/llvm/test/MC/AArch64/neon-mla-mls-instructions.s b/llvm/test/MC/AArch64/neon-mla-mls-instructions.s index b82706862ec..5c8b7d8788a 100644 --- a/llvm/test/MC/AArch64/neon-mla-mls-instructions.s +++ b/llvm/test/MC/AArch64/neon-mla-mls-instructions.s @@ -1,4 +1,3 @@ -// RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s // RUN: llvm-mc -triple arm64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s // Check that the assembler can handle the documented syntax for AArch64 diff --git a/llvm/test/MC/AArch64/neon-mov.s b/llvm/test/MC/AArch64/neon-mov.s index 8c420f1c013..6231ffe49c5 100644 --- a/llvm/test/MC/AArch64/neon-mov.s +++ b/llvm/test/MC/AArch64/neon-mov.s @@ -1,4 +1,3 @@ -// RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s // RUN: llvm-mc -triple arm64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s // Check that the assembler can handle the documented syntax for AArch64 diff --git a/llvm/test/MC/AArch64/neon-mul-div-instructions.s b/llvm/test/MC/AArch64/neon-mul-div-instructions.s index 6a39ad8e2e0..2601d50f131 100644 --- a/llvm/test/MC/AArch64/neon-mul-div-instructions.s +++ b/llvm/test/MC/AArch64/neon-mul-div-instructions.s @@ -1,4 +1,3 @@ -// RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s // RUN: llvm-mc -triple arm64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s // Check that the assembler can handle the documented syntax for AArch64 diff --git a/llvm/test/MC/AArch64/neon-perm.s b/llvm/test/MC/AArch64/neon-perm.s index 641415ee1ee..4b28dd01db3 100644 --- a/llvm/test/MC/AArch64/neon-perm.s +++ b/llvm/test/MC/AArch64/neon-perm.s @@ -1,4 +1,3 @@ -// RUN: llvm-mc -triple=aarch64 -mattr=+neon -show-encoding < %s | FileCheck %s // RUN: llvm-mc -triple=arm64 -mattr=+neon -show-encoding < %s | FileCheck %s // Check that the assembler can handle the documented syntax for AArch64 diff --git a/llvm/test/MC/AArch64/neon-rounding-halving-add.s b/llvm/test/MC/AArch64/neon-rounding-halving-add.s index 7e81b1a65ca..55c9f921da7 100644 --- a/llvm/test/MC/AArch64/neon-rounding-halving-add.s +++ b/llvm/test/MC/AArch64/neon-rounding-halving-add.s @@ -1,4 +1,3 @@ -// RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s // RUN: llvm-mc -triple arm64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s // Check that the assembler can handle the documented syntax for AArch64 diff --git a/llvm/test/MC/AArch64/neon-rounding-shift.s b/llvm/test/MC/AArch64/neon-rounding-shift.s index 5f72bafea48..38924e7c4bd 100644 --- a/llvm/test/MC/AArch64/neon-rounding-shift.s +++ b/llvm/test/MC/AArch64/neon-rounding-shift.s @@ -1,4 +1,3 @@ -// RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s // RUN: llvm-mc -triple arm64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s // Check that the assembler can handle the documented syntax for AArch64 diff --git a/llvm/test/MC/AArch64/neon-saturating-add-sub.s b/llvm/test/MC/AArch64/neon-saturating-add-sub.s index 1d2916a48d1..d39997901f7 100644 --- a/llvm/test/MC/AArch64/neon-saturating-add-sub.s +++ b/llvm/test/MC/AArch64/neon-saturating-add-sub.s @@ -1,4 +1,3 @@ -// RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s // RUN: llvm-mc -triple arm64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s // Check that the assembler can handle the documented syntax for AArch64 diff --git a/llvm/test/MC/AArch64/neon-saturating-rounding-shift.s b/llvm/test/MC/AArch64/neon-saturating-rounding-shift.s index bc5c1c0a213..702b9d2c60e 100644 --- a/llvm/test/MC/AArch64/neon-saturating-rounding-shift.s +++ b/llvm/test/MC/AArch64/neon-saturating-rounding-shift.s @@ -1,4 +1,3 @@ -// RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s // RUN: llvm-mc -triple arm64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s // Check that the assembler can handle the documented syntax for AArch64 diff --git a/llvm/test/MC/AArch64/neon-saturating-shift.s b/llvm/test/MC/AArch64/neon-saturating-shift.s index d35e1f3d0f0..d03172b1788 100644 --- a/llvm/test/MC/AArch64/neon-saturating-shift.s +++ b/llvm/test/MC/AArch64/neon-saturating-shift.s @@ -1,4 +1,3 @@ -// RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s // RUN: llvm-mc -triple arm64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s // Check that the assembler can handle the documented syntax for AArch64 diff --git a/llvm/test/MC/AArch64/neon-scalar-abs.s b/llvm/test/MC/AArch64/neon-scalar-abs.s index c529cfc7522..897c93506e1 100644 --- a/llvm/test/MC/AArch64/neon-scalar-abs.s +++ b/llvm/test/MC/AArch64/neon-scalar-abs.s @@ -1,4 +1,3 @@ -// RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s // RUN: llvm-mc -triple arm64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s // Check that the assembler can handle the documented syntax for AArch64 diff --git a/llvm/test/MC/AArch64/neon-scalar-add-sub.s b/llvm/test/MC/AArch64/neon-scalar-add-sub.s index fea1fc8ee8a..955c30716b4 100644 --- a/llvm/test/MC/AArch64/neon-scalar-add-sub.s +++ b/llvm/test/MC/AArch64/neon-scalar-add-sub.s @@ -1,4 +1,3 @@ -// RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s // RUN: llvm-mc -triple arm64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s //------------------------------------------------------------------------------ diff --git a/llvm/test/MC/AArch64/neon-scalar-by-elem-mla.s b/llvm/test/MC/AArch64/neon-scalar-by-elem-mla.s index 7d5c6d04fd4..d4f3682dc2b 100644 --- a/llvm/test/MC/AArch64/neon-scalar-by-elem-mla.s +++ b/llvm/test/MC/AArch64/neon-scalar-by-elem-mla.s @@ -1,4 +1,3 @@ -// RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s // RUN: llvm-mc -triple arm64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s //------------------------------------------------------------------------------ diff --git a/llvm/test/MC/AArch64/neon-scalar-by-elem-mul.s b/llvm/test/MC/AArch64/neon-scalar-by-elem-mul.s index 78c51594d17..d22aa9b15b2 100644 --- a/llvm/test/MC/AArch64/neon-scalar-by-elem-mul.s +++ b/llvm/test/MC/AArch64/neon-scalar-by-elem-mul.s @@ -1,4 +1,3 @@ -// RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s // RUN: llvm-mc -triple arm64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s //------------------------------------------------------------------------------ diff --git a/llvm/test/MC/AArch64/neon-scalar-by-elem-saturating-mla.s b/llvm/test/MC/AArch64/neon-scalar-by-elem-saturating-mla.s index 007568cceb4..dadb8db9936 100644 --- a/llvm/test/MC/AArch64/neon-scalar-by-elem-saturating-mla.s +++ b/llvm/test/MC/AArch64/neon-scalar-by-elem-saturating-mla.s @@ -1,4 +1,3 @@ -// RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s // RUN: llvm-mc -triple arm64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s //----------------------------------------------------------------------------- diff --git a/llvm/test/MC/AArch64/neon-scalar-by-elem-saturating-mul.s b/llvm/test/MC/AArch64/neon-scalar-by-elem-saturating-mul.s index 727bc670e1f..90eeb5e64c0 100644 --- a/llvm/test/MC/AArch64/neon-scalar-by-elem-saturating-mul.s +++ b/llvm/test/MC/AArch64/neon-scalar-by-elem-saturating-mul.s @@ -1,4 +1,3 @@ -// RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s // RUN: llvm-mc -triple arm64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s //----------------------------------------------------------------------------- diff --git a/llvm/test/MC/AArch64/neon-scalar-compare.s b/llvm/test/MC/AArch64/neon-scalar-compare.s index 1cd04fd111f..16ba92e0797 100644 --- a/llvm/test/MC/AArch64/neon-scalar-compare.s +++ b/llvm/test/MC/AArch64/neon-scalar-compare.s @@ -1,4 +1,3 @@ -// RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s // RUN: llvm-mc -triple arm64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s // Check that the assembler can handle the documented syntax for AArch64 diff --git a/llvm/test/MC/AArch64/neon-scalar-cvt.s b/llvm/test/MC/AArch64/neon-scalar-cvt.s index dc8e3165b6d..047495276fb 100644 --- a/llvm/test/MC/AArch64/neon-scalar-cvt.s +++ b/llvm/test/MC/AArch64/neon-scalar-cvt.s @@ -1,4 +1,3 @@ -// RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s // RUN: llvm-mc -triple arm64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s // Check that the assembler can handle the documented syntax for AArch64 diff --git a/llvm/test/MC/AArch64/neon-scalar-dup.s b/llvm/test/MC/AArch64/neon-scalar-dup.s index 81bdb7c4f85..ba4f3c2ad79 100644 --- a/llvm/test/MC/AArch64/neon-scalar-dup.s +++ b/llvm/test/MC/AArch64/neon-scalar-dup.s @@ -1,4 +1,3 @@ -// RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s // RUN: llvm-mc -triple arm64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s //------------------------------------------------------------------------------ diff --git a/llvm/test/MC/AArch64/neon-scalar-extract-narrow.s b/llvm/test/MC/AArch64/neon-scalar-extract-narrow.s index 7e4ff85de7d..e6167930d1c 100644 --- a/llvm/test/MC/AArch64/neon-scalar-extract-narrow.s +++ b/llvm/test/MC/AArch64/neon-scalar-extract-narrow.s @@ -1,4 +1,3 @@ -// RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s // RUN: llvm-mc -triple arm64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s // Check that the assembler can handle the documented syntax for AArch64 diff --git a/llvm/test/MC/AArch64/neon-scalar-fp-compare.s b/llvm/test/MC/AArch64/neon-scalar-fp-compare.s index 054f923322e..cb9e7a7a66e 100644 --- a/llvm/test/MC/AArch64/neon-scalar-fp-compare.s +++ b/llvm/test/MC/AArch64/neon-scalar-fp-compare.s @@ -1,4 +1,3 @@ -// RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s // RUN: llvm-mc -triple arm64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s // Check that the assembler can handle the documented syntax for AArch64 diff --git a/llvm/test/MC/AArch64/neon-scalar-mul.s b/llvm/test/MC/AArch64/neon-scalar-mul.s index 968793fea88..21be537cbb7 100644 --- a/llvm/test/MC/AArch64/neon-scalar-mul.s +++ b/llvm/test/MC/AArch64/neon-scalar-mul.s @@ -1,4 +1,3 @@ -// RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s // RUN: llvm-mc -triple arm64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s // Check that the assembler can handle the documented syntax for AArch64 diff --git a/llvm/test/MC/AArch64/neon-scalar-neg.s b/llvm/test/MC/AArch64/neon-scalar-neg.s index ac61f9b78aa..e902c2307a1 100644 --- a/llvm/test/MC/AArch64/neon-scalar-neg.s +++ b/llvm/test/MC/AArch64/neon-scalar-neg.s @@ -1,4 +1,3 @@ -// RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s // RUN: llvm-mc -triple arm64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s // Check that the assembler can handle the documented syntax for AArch64 diff --git a/llvm/test/MC/AArch64/neon-scalar-recip.s b/llvm/test/MC/AArch64/neon-scalar-recip.s index 9dc6d069cd0..dde26b557be 100644 --- a/llvm/test/MC/AArch64/neon-scalar-recip.s +++ b/llvm/test/MC/AArch64/neon-scalar-recip.s @@ -1,4 +1,3 @@ -// RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s // RUN: llvm-mc -triple arm64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s // Check that the assembler can handle the documented syntax for AArch64 diff --git a/llvm/test/MC/AArch64/neon-scalar-reduce-pairwise.s b/llvm/test/MC/AArch64/neon-scalar-reduce-pairwise.s index bf5eb5304b8..cb7564ac68d 100644 --- a/llvm/test/MC/AArch64/neon-scalar-reduce-pairwise.s +++ b/llvm/test/MC/AArch64/neon-scalar-reduce-pairwise.s @@ -1,4 +1,3 @@ -// RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s // RUN: llvm-mc -triple arm64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s //---------------------------------------------------------------------- diff --git a/llvm/test/MC/AArch64/neon-scalar-rounding-shift.s b/llvm/test/MC/AArch64/neon-scalar-rounding-shift.s index 2d654958917..2594c2f2ac5 100644 --- a/llvm/test/MC/AArch64/neon-scalar-rounding-shift.s +++ b/llvm/test/MC/AArch64/neon-scalar-rounding-shift.s @@ -1,4 +1,3 @@ -// RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s // RUN: llvm-mc -triple arm64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s diff --git a/llvm/test/MC/AArch64/neon-scalar-saturating-add-sub.s b/llvm/test/MC/AArch64/neon-scalar-saturating-add-sub.s index 3cdfd6204df..d5cd838a92b 100644 --- a/llvm/test/MC/AArch64/neon-scalar-saturating-add-sub.s +++ b/llvm/test/MC/AArch64/neon-scalar-saturating-add-sub.s @@ -1,4 +1,3 @@ -// RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s // RUN: llvm-mc -triple arm64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s //------------------------------------------------------------------------------ diff --git a/llvm/test/MC/AArch64/neon-scalar-saturating-rounding-shift.s b/llvm/test/MC/AArch64/neon-scalar-saturating-rounding-shift.s index 17bf222661c..83bd59f50c8 100644 --- a/llvm/test/MC/AArch64/neon-scalar-saturating-rounding-shift.s +++ b/llvm/test/MC/AArch64/neon-scalar-saturating-rounding-shift.s @@ -1,4 +1,3 @@ -// RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s // RUN: llvm-mc -triple arm64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s //------------------------------------------------------------------------------ diff --git a/llvm/test/MC/AArch64/neon-scalar-saturating-shift.s b/llvm/test/MC/AArch64/neon-scalar-saturating-shift.s index 3eddabd616f..679f1f4052c 100644 --- a/llvm/test/MC/AArch64/neon-scalar-saturating-shift.s +++ b/llvm/test/MC/AArch64/neon-scalar-saturating-shift.s @@ -1,4 +1,3 @@ -// RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s // RUN: llvm-mc -triple arm64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s //------------------------------------------------------------------------------ diff --git a/llvm/test/MC/AArch64/neon-scalar-shift-imm.s b/llvm/test/MC/AArch64/neon-scalar-shift-imm.s index a0847d207a3..47a8dec212b 100644 --- a/llvm/test/MC/AArch64/neon-scalar-shift-imm.s +++ b/llvm/test/MC/AArch64/neon-scalar-shift-imm.s @@ -1,4 +1,3 @@ -// RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s // RUN: llvm-mc -triple arm64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s // Check that the assembler can handle the documented syntax for AArch64 diff --git a/llvm/test/MC/AArch64/neon-scalar-shift.s b/llvm/test/MC/AArch64/neon-scalar-shift.s index 54b42f5eab2..98aa51a63da 100644 --- a/llvm/test/MC/AArch64/neon-scalar-shift.s +++ b/llvm/test/MC/AArch64/neon-scalar-shift.s @@ -1,4 +1,3 @@ -// RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s // RUN: llvm-mc -triple arm64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s //------------------------------------------------------------------------------ diff --git a/llvm/test/MC/AArch64/neon-shift-left-long.s b/llvm/test/MC/AArch64/neon-shift-left-long.s index 679af09ea4a..87204683104 100644 --- a/llvm/test/MC/AArch64/neon-shift-left-long.s +++ b/llvm/test/MC/AArch64/neon-shift-left-long.s @@ -1,4 +1,3 @@ -// RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s // RUN: llvm-mc -triple arm64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s // Check that the assembler can handle the documented syntax for AArch64 diff --git a/llvm/test/MC/AArch64/neon-shift.s b/llvm/test/MC/AArch64/neon-shift.s index d5b730c0702..dcff992a782 100644 --- a/llvm/test/MC/AArch64/neon-shift.s +++ b/llvm/test/MC/AArch64/neon-shift.s @@ -1,4 +1,3 @@ -// RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s // RUN: llvm-mc -triple arm64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s // Check that the assembler can handle the documented syntax for AArch64 diff --git a/llvm/test/MC/AArch64/neon-simd-copy.s b/llvm/test/MC/AArch64/neon-simd-copy.s index dc8b060b357..917f7cb524e 100644 --- a/llvm/test/MC/AArch64/neon-simd-copy.s +++ b/llvm/test/MC/AArch64/neon-simd-copy.s @@ -1,4 +1,3 @@ -// RUN: llvm-mc -triple=aarch64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s // RUN: llvm-mc -triple=arm64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s // Check that the assembler can handle the documented syntax for AArch64 diff --git a/llvm/test/MC/AArch64/neon-simd-ldst-multi-elem.s b/llvm/test/MC/AArch64/neon-simd-ldst-multi-elem.s index 85e7c28e396..b8b3e72ff77 100644 --- a/llvm/test/MC/AArch64/neon-simd-ldst-multi-elem.s +++ b/llvm/test/MC/AArch64/neon-simd-ldst-multi-elem.s @@ -1,4 +1,3 @@ -// RUN: llvm-mc -triple=aarch64 -mattr=+neon -show-encoding < %s | FileCheck %s // RUN: llvm-mc -triple=arm64 -mattr=+neon -show-encoding < %s | FileCheck %s // Check that the assembler can handle the documented syntax for AArch64 diff --git a/llvm/test/MC/AArch64/neon-simd-ldst-one-elem.s b/llvm/test/MC/AArch64/neon-simd-ldst-one-elem.s index 63b7bca3985..4febf6d8fe0 100644 --- a/llvm/test/MC/AArch64/neon-simd-ldst-one-elem.s +++ b/llvm/test/MC/AArch64/neon-simd-ldst-one-elem.s @@ -1,4 +1,3 @@ -// RUN: llvm-mc -triple=aarch64 -mattr=+neon -show-encoding < %s | FileCheck %s // RUN: llvm-mc -triple=arm64 -mattr=+neon -show-encoding < %s | FileCheck %s // Check that the assembler can handle the documented syntax for AArch64 diff --git a/llvm/test/MC/AArch64/neon-simd-misc.s b/llvm/test/MC/AArch64/neon-simd-misc.s index 4486dddce40..6d1aafdd772 100644 --- a/llvm/test/MC/AArch64/neon-simd-misc.s +++ b/llvm/test/MC/AArch64/neon-simd-misc.s @@ -1,4 +1,3 @@ -// RUN: llvm-mc -triple=aarch64 -mattr=+neon -show-encoding < %s | FileCheck %s // RUN: llvm-mc -triple=arm64 -mattr=+neon -show-encoding < %s | FileCheck %s // Check that the assembler can handle the documented syntax for AArch64 diff --git a/llvm/test/MC/AArch64/neon-simd-post-ldst-multi-elem.s b/llvm/test/MC/AArch64/neon-simd-post-ldst-multi-elem.s index b8cc266cfca..c57a122f35c 100644 --- a/llvm/test/MC/AArch64/neon-simd-post-ldst-multi-elem.s +++ b/llvm/test/MC/AArch64/neon-simd-post-ldst-multi-elem.s @@ -1,4 +1,3 @@ -// RUN: llvm-mc -triple=aarch64 -mattr=+neon -show-encoding < %s | FileCheck %s // RUN: llvm-mc -triple=arm64 -mattr=+neon -show-encoding < %s | FileCheck %s // Check that the assembler can handle the documented syntax for AArch64 diff --git a/llvm/test/MC/AArch64/neon-simd-shift.s b/llvm/test/MC/AArch64/neon-simd-shift.s index 46a75009dc4..1c1ad7489d5 100644 --- a/llvm/test/MC/AArch64/neon-simd-shift.s +++ b/llvm/test/MC/AArch64/neon-simd-shift.s @@ -1,4 +1,3 @@ -// RUN: llvm-mc -triple=aarch64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s // RUN: llvm-mc -triple=arm64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s // Check that the assembler can handle the documented syntax for AArch64 diff --git a/llvm/test/MC/AArch64/neon-sxtl.s b/llvm/test/MC/AArch64/neon-sxtl.s index 2efdb4dcbbd..363796ee334 100644 --- a/llvm/test/MC/AArch64/neon-sxtl.s +++ b/llvm/test/MC/AArch64/neon-sxtl.s @@ -1,4 +1,3 @@ -// RUN: llvm-mc -triple=aarch64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s // RUN: llvm-mc -triple=arm64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s // Check that the assembler can handle the documented syntax for AArch64 diff --git a/llvm/test/MC/AArch64/neon-tbl.s b/llvm/test/MC/AArch64/neon-tbl.s index e8d77c75c37..bb39fa9f22a 100644 --- a/llvm/test/MC/AArch64/neon-tbl.s +++ b/llvm/test/MC/AArch64/neon-tbl.s @@ -1,4 +1,3 @@ -// RUN: llvm-mc -triple=aarch64 -mattr=+neon -show-encoding < %s | FileCheck %s // RUN: llvm-mc -triple=arm64 -mattr=+neon -show-encoding < %s | FileCheck %s // Check that the assembler can handle the documented syntax for AArch64 diff --git a/llvm/test/MC/AArch64/neon-uxtl.s b/llvm/test/MC/AArch64/neon-uxtl.s index 502166b2818..46c56625c0f 100644 --- a/llvm/test/MC/AArch64/neon-uxtl.s +++ b/llvm/test/MC/AArch64/neon-uxtl.s @@ -1,4 +1,3 @@ -// RUN: llvm-mc -triple=aarch64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s // RUN: llvm-mc -triple=arm64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s // Check that the assembler can handle the documented syntax for AArch64 diff --git a/llvm/test/MC/AArch64/noneon-diagnostics.s b/llvm/test/MC/AArch64/noneon-diagnostics.s index 3c953e3764d..470a74d5b31 100644 --- a/llvm/test/MC/AArch64/noneon-diagnostics.s +++ b/llvm/test/MC/AArch64/noneon-diagnostics.s @@ -1,6 +1,3 @@ -// RUN: not llvm-mc -triple aarch64-none-linux-gnu -mattr=-neon < %s 2> %t -// RUN: FileCheck --check-prefix=CHECK-ERROR < %t %s - // RUN: not llvm-mc -triple arm64-none-linux-gnu -mattr=-neon < %s 2> %t // RUN: FileCheck --check-prefix=CHECK-ARM64-ERROR < %t %s diff --git a/llvm/test/MC/AArch64/optional-hash.s b/llvm/test/MC/AArch64/optional-hash.s index a332cb09124..7ae1aa49047 100644 --- a/llvm/test/MC/AArch64/optional-hash.s +++ b/llvm/test/MC/AArch64/optional-hash.s @@ -1,7 +1,4 @@ // PR18929 -// RUN: llvm-mc < %s -triple=aarch64-linux-gnueabi -mattr=+fp-armv8,+neon -filetype=obj -o - \ -// RUN: | llvm-objdump --disassemble -arch=aarch64 -mattr=+fp-armv8,+neon - | FileCheck %s - // RUN: llvm-mc < %s -triple=arm64-linux-gnueabi -mattr=+fp-armv8,+neon -filetype=obj -o - \ // RUN: | llvm-objdump --disassemble -arch=arm64 -mattr=+fp-armv8,+neon - | FileCheck %s diff --git a/llvm/test/MC/AArch64/tls-relocs.s b/llvm/test/MC/AArch64/tls-relocs.s index 5b2e9887599..ae7b20cefd5 100644 --- a/llvm/test/MC/AArch64/tls-relocs.s +++ b/llvm/test/MC/AArch64/tls-relocs.s @@ -1,7 +1,3 @@ -// RUN: llvm-mc -triple=aarch64-none-linux-gnu -show-encoding < %s | FileCheck %s --check-prefix=CHECK-AARCH64 -// RUN: llvm-mc -triple=aarch64-none-linux-gnu -filetype=obj < %s -o - | \ -// RUN: llvm-readobj -r -t | FileCheck --check-prefix=CHECK-ELF %s - // RUN: llvm-mc -triple=arm64-none-linux-gnu -show-encoding < %s | FileCheck %s --check-prefix=CHECK-ARM64 // RUN: llvm-mc -triple=arm64-none-linux-gnu -filetype=obj < %s -o - | \ // RUN: llvm-readobj -r -t | FileCheck --check-prefix=CHECK-ELF %s @@ -11,14 +7,6 @@ movn x2, #:dtprel_g2:var movz x3, #:dtprel_g2:var movn x4, #:dtprel_g2:var -// CHECK-AARCH64: movz x1, #:dtprel_g2:var // encoding: [0x01'A',A,0xc0'A',0x92'A'] -// CHECK-AARCH64-NEXT: // fixup A - offset: 0, value: :dtprel_g2:var, kind: fixup_a64_movw_dtprel_g2 -// CHECK-AARCH64: movn x2, #:dtprel_g2:var // encoding: [0x02'A',A,0xc0'A',0x92'A'] -// CHECK-AARCH64-NEXT: // fixup A - offset: 0, value: :dtprel_g2:var, kind: fixup_a64_movw_dtprel_g2 -// CHECK-AARCH64: movz x3, #:dtprel_g2:var // encoding: [0x03'A',A,0xc0'A',0x92'A'] -// CHECK-AARCH64-NEXT: // fixup A - offset: 0, value: :dtprel_g2:var, kind: fixup_a64_movw_dtprel_g2 -// CHECK-AARCH64: movn x4, #:dtprel_g2:var // encoding: [0x04'A',A,0xc0'A',0x92'A'] -// CHECK-AARCH64-NEXT: // fixup A - offset: 0, value: :dtprel_g2:var, kind: fixup_a64_movw_dtprel_g2 // CHECK-ARM64: movz x1, #:dtprel_g2:var // encoding: [0bAAA00001,A,0b110AAAAA,0x92] // CHECK-ARM64: // fixup A - offset: 0, value: :dtprel_g2:var, kind: fixup_arm64_movw @@ -41,14 +29,6 @@ movn x6, #:dtprel_g1:var movz w7, #:dtprel_g1:var movn w8, #:dtprel_g1:var -// CHECK-AARCH64: movz x5, #:dtprel_g1:var // encoding: [0x05'A',A,0xa0'A',0x92'A'] -// CHECK-AARCH64-NEXT: // fixup A - offset: 0, value: :dtprel_g1:var, kind: fixup_a64_movw_dtprel_g1 -// CHECK-AARCH64: movn x6, #:dtprel_g1:var // encoding: [0x06'A',A,0xa0'A',0x92'A'] -// CHECK-AARCH64-NEXT: // fixup A - offset: 0, value: :dtprel_g1:var, kind: fixup_a64_movw_dtprel_g1 -// CHECK-AARCH64: movz w7, #:dtprel_g1:var // encoding: [0x07'A',A,0xa0'A',0x12'A'] -// CHECK-AARCH64-NEXT: // fixup A - offset: 0, value: :dtprel_g1:var, kind: fixup_a64_movw_dtprel_g1 -// CHECK-AARCH64: movn w8, #:dtprel_g1:var // encoding: [0x08'A',A,0xa0'A',0x12'A'] -// CHECK-AARCH64-NEXT: // fixup A - offset: 0, value: :dtprel_g1:var, kind: fixup_a64_movw_dtprel_g1 // CHECK-ARM64: movz x5, #:dtprel_g1:var // encoding: [0bAAA00101,A,0b101AAAAA,0x92] // CHECK-ARM64: // fixup A - offset: 0, value: :dtprel_g1:var, kind: fixup_arm64_movw @@ -67,10 +47,6 @@ movk x9, #:dtprel_g1_nc:var movk w10, #:dtprel_g1_nc:var -// CHECK-AARCH64: movk x9, #:dtprel_g1_nc:var // encoding: [0x09'A',A,0xa0'A',0xf2'A'] -// CHECK-AARCH64-NEXT: // fixup A - offset: 0, value: :dtprel_g1_nc:var, kind: fixup_a64_movw_dtprel_g1_nc -// CHECK-AARCH64: movk w10, #:dtprel_g1_nc:var // encoding: [0x0a'A',A,0xa0'A',0x72'A'] -// CHECK-AARCH64-NEXT: // fixup A - offset: 0, value: :dtprel_g1_nc:var, kind: fixup_a64_movw_dtprel_g1_nc // CHECK-ARM64: movk x9, #:dtprel_g1_nc:var // encoding: [0bAAA01001,A,0b101AAAAA,0xf2] // CHECK-ARM64: // fixup A - offset: 0, value: :dtprel_g1_nc:var, kind: fixup_arm64_movw @@ -85,13 +61,6 @@ movn x12, #:dtprel_g0:var movz w13, #:dtprel_g0:var movn w14, #:dtprel_g0:var -// CHECK-AARCH64: movz x11, #:dtprel_g0:var // encoding: [0x0b'A',A,0x80'A',0x92'A'] -// CHECK-AARCH64-NEXT: // fixup A - offset: 0, value: :dtprel_g0:var, kind: fixup_a64_movw_dtprel_g0 -// CHECK-AARCH64: movn x12, #:dtprel_g0:var // encoding: [0x0c'A',A,0x80'A',0x92'A'] -// CHECK-AARCH64-NEXT: // fixup A - offset: 0, value: :dtprel_g0:var, kind: fixup_a64_movw_dtprel_g0 -// CHECK-AARCH64: movz w13, #:dtprel_g0:var // encoding: [0x0d'A',A,0x80'A',0x12'A'] -// CHECK-AARCH64-NEXT: // fixup A - offset: 0, value: :dtprel_g0:var, kind: fixup_a64_movw_dtprel_g0 -// CHECK-AARCH64: movn w14, #:dtprel_g0:var // encoding: [0x0e'A',A,0x80'A',0x12'A'] // CHECK-ARM64: movz x11, #:dtprel_g0:var // encoding: [0bAAA01011,A,0b100AAAAA,0x92] // CHECK-ARM64: // fixup A - offset: 0, value: :dtprel_g0:var, kind: fixup_arm64_movw @@ -110,10 +79,6 @@ movk x15, #:dtprel_g0_nc:var movk w16, #:dtprel_g0_nc:var -// CHECK-AARCH64: movk x15, #:dtprel_g0_nc:var // encoding: [0x0f'A',A,0x80'A',0xf2'A'] -// CHECK-AARCH64-NEXT: // fixup A - offset: 0, value: :dtprel_g0_nc:var, kind: fixup_a64_movw_dtprel_g0_nc -// CHECK-AARCH64: movk w16, #:dtprel_g0_nc:var // encoding: [0x10'A',A,0x80'A',0x72'A'] -// CHECK-AARCH64-NEXT: // fixup A - offset: 0, value: :dtprel_g0_nc:var, kind: fixup_a64_movw_dtprel_g0_nc // CHECK-ARM64: movk x15, #:dtprel_g0_nc:var // encoding: [0bAAA01111,A,0b100AAAAA,0xf2] // CHECK-ARM64: // fixup A - offset: 0, value: :dtprel_g0_nc:var, kind: fixup_arm64_movw @@ -126,10 +91,6 @@ add x17, x18, #:dtprel_hi12:var, lsl #12 add w19, w20, #:dtprel_hi12:var, lsl #12 -// CHECK-AARCH64: add x17, x18, #:dtprel_hi12:var, lsl #12 // encoding: [0x51'A',0x02'A',0x40'A',0x91'A'] -// CHECK-AARCH64-NEXT: // fixup A - offset: 0, value: :dtprel_hi12:var, kind: fixup_a64_add_dtprel_hi12 -// CHECK-AARCH64: add w19, w20, #:dtprel_hi12:var, lsl #12 // encoding: [0x93'A',0x02'A',0x40'A',0x11'A'] -// CHECK-AARCH64-NEXT: // fixup A - offset: 0, value: :dtprel_hi12:var, kind: fixup_a64_add_dtprel_hi12 // CHECK-ARM64: add x17, x18, :dtprel_hi12:var, lsl #12 // encoding: [0x51,0bAAAAAA10,0b00AAAAAA,0x91] // CHECK-ARM64: // fixup A - offset: 0, value: :dtprel_hi12:var, kind: fixup_arm64_add_imm12 @@ -142,10 +103,6 @@ add x21, x22, #:dtprel_lo12:var add w23, w24, #:dtprel_lo12:var -// CHECK-AARCH64: add x21, x22, #:dtprel_lo12:var // encoding: [0xd5'A',0x02'A',A,0x91'A'] -// CHECK-AARCH64-NEXT: // fixup A - offset: 0, value: :dtprel_lo12:var, kind: fixup_a64_add_dtprel_lo12 -// CHECK-AARCH64: add w23, w24, #:dtprel_lo12:var // encoding: [0x17'A',0x03'A',A,0x11'A'] -// CHECK-AARCH64-NEXT: // fixup A - offset: 0, value: :dtprel_lo12:var, kind: fixup_a64_add_dtprel_lo12 // CHECK-ARM64: add x21, x22, :dtprel_lo12:var // encoding: [0xd5,0bAAAAAA10,0b00AAAAAA,0x91] // CHECK-ARM64: // fixup A - offset: 0, value: :dtprel_lo12:var, kind: fixup_arm64_add_imm12 @@ -158,10 +115,6 @@ add x25, x26, #:dtprel_lo12_nc:var add w27, w28, #:dtprel_lo12_nc:var -// CHECK-AARCH64: add x25, x26, #:dtprel_lo12_nc:var // encoding: [0x59'A',0x03'A',A,0x91'A'] -// CHECK-AARCH64-NEXT: // fixup A - offset: 0, value: :dtprel_lo12_nc:var, kind: fixup_a64_add_dtprel_lo12_nc -// CHECK-AARCH64: add w27, w28, #:dtprel_lo12_nc:var // encoding: [0x9b'A',0x03'A',A,0x11'A'] -// CHECK-AARCH64-NEXT: // fixup A - offset: 0, value: :dtprel_lo12_nc:var, kind: fixup_a64_add_dtprel_lo12_nc // CHECK-ARM64: add x25, x26, :dtprel_lo12_nc:var // encoding: [0x59,0bAAAAAA11,0b00AAAAAA,0x91] // CHECK-ARM64: // fixup A - offset: 0, value: :dtprel_lo12_nc:var, kind: fixup_arm64_add_imm12 @@ -174,10 +127,6 @@ ldrb w29, [x30, #:dtprel_lo12:var] ldrsb x29, [x28, #:dtprel_lo12_nc:var] -// CHECK-AARCH64: ldrb w29, [x30, #:dtprel_lo12:var] // encoding: [0xdd'A',0x03'A',0x40'A',0x39'A'] -// CHECK-AARCH64-NEXT: // fixup A - offset: 0, value: :dtprel_lo12:var, kind: fixup_a64_ldst8_dtprel_lo12 -// CHECK-AARCH64: ldrsb x29, [x28, #:dtprel_lo12_nc:var] // encoding: [0x9d'A',0x03'A',0x80'A',0x39'A'] -// CHECK-AARCH64-NEXT: // fixup A - offset: 0, value: :dtprel_lo12_nc:var, kind: fixup_a64_ldst8_dtprel_lo12_nc // CHECK-ARM64: ldrb w29, [x30, :dtprel_lo12:var] // encoding: [0xdd,0bAAAAAA11,0b01AAAAAA,0x39] // CHECK-ARM64: // fixup A - offset: 0, value: :dtprel_lo12:var, kind: fixup_arm64_ldst_imm12_scale1 @@ -190,10 +139,6 @@ strh w27, [x26, #:dtprel_lo12:var] ldrsh x25, [x24, #:dtprel_lo12_nc:var] -// CHECK-AARCH64: strh w27, [x26, #:dtprel_lo12:var] // encoding: [0x5b'A',0x03'A',A,0x79'A'] -// CHECK-AARCH64-NEXT: // fixup A - offset: 0, value: :dtprel_lo12:var, kind: fixup_a64_ldst16_dtprel_lo12 -// CHECK-AARCH64: ldrsh x25, [x24, #:dtprel_lo12_nc:var] // encoding: [0x19'A',0x03'A',0x80'A',0x79'A'] -// CHECK-AARCH64-NEXT: // fixup A - offset: 0, value: :dtprel_lo12_nc:var, kind: fixup_a64_ldst16_dtprel_lo12_n // CHECK-ARM64: strh w27, [x26, :dtprel_lo12:var] // encoding: [0x5b,0bAAAAAA11,0b00AAAAAA,0x79] // CHECK-ARM64: // fixup A - offset: 0, value: :dtprel_lo12:var, kind: fixup_arm64_ldst_imm12_scale2 @@ -206,10 +151,6 @@ ldr w23, [x22, #:dtprel_lo12:var] ldrsw x21, [x20, #:dtprel_lo12_nc:var] -// CHECK-AARCH64: ldr w23, [x22, #:dtprel_lo12:var] // encoding: [0xd7'A',0x02'A',0x40'A',0xb9'A'] -// CHECK-AARCH64-NEXT: // fixup A - offset: 0, value: :dtprel_lo12:var, kind: fixup_a64_ldst32_dtprel_lo12 -// CHECK-AARCH64: ldrsw x21, [x20, #:dtprel_lo12_nc:var] // encoding: [0x95'A',0x02'A',0x80'A',0xb9'A'] -// CHECK-AARCH64-NEXT: // fixup A - offset: 0, value: :dtprel_lo12_nc:var, kind: fixup_a64_ldst32_dtprel_lo12_n // CHECK-ARM64: ldr w23, [x22, :dtprel_lo12:var] // encoding: [0xd7,0bAAAAAA10,0b01AAAAAA,0xb9] // CHECK-ARM64: // fixup A - offset: 0, value: :dtprel_lo12:var, kind: fixup_arm64_ldst_imm12_scale4 @@ -222,10 +163,6 @@ ldr x19, [x18, #:dtprel_lo12:var] str x17, [x16, #:dtprel_lo12_nc:var] -// CHECK-AARCH64: ldr x19, [x18, #:dtprel_lo12:var] // encoding: [0x53'A',0x02'A',0x40'A',0xf9'A'] -// CHECK-AARCH64-NEXT: // fixup A - offset: 0, value: :dtprel_lo12:var, kind: fixup_a64_ldst64_dtprel_lo12 -// CHECK-AARCH64: str x17, [x16, #:dtprel_lo12_nc:var] // encoding: [0x11'A',0x02'A',A,0xf9'A'] -// CHECK-AARCH64-NEXT: // fixup A - offset: 0, value: :dtprel_lo12_nc:var, kind: fixup_a64_ldst64_dtprel_lo12_nc // CHECK-ARM64: ldr x19, [x18, :dtprel_lo12:var] // encoding: [0x53,0bAAAAAA10,0b01AAAAAA,0xf9] // CHECK-ARM64: // fixup A - offset: 0, value: :dtprel_lo12:var, kind: fixup_arm64_ldst_imm12_scale8 @@ -239,10 +176,6 @@ // TLS initial-exec forms movz x15, #:gottprel_g1:var movz w14, #:gottprel_g1:var -// CHECK-AARCH64: movz x15, #:gottprel_g1:var // encoding: [0x0f'A',A,0xa0'A',0x92'A'] -// CHECK-AARCH64-NEXT: // fixup A - offset: 0, value: :gottprel_g1:var, kind: fixup_a64_movw_gottprel_g1 -// CHECK-AARCH64: movz w14, #:gottprel_g1:var // encoding: [0x0e'A',A,0xa0'A',0x12'A'] -// CHECK-AARCH64-NEXT: // fixup A - offset: 0, value: :gottprel_g1:var, kind: fixup_a64_movw_gottprel_g1 // CHECK-ARM64: movz x15, #:gottprel_g1:var // encoding: [0bAAA01111,A,0b101AAAAA,0x92] // CHECK-ARM64: // fixup A - offset: 0, value: :gottprel_g1:var, kind: fixup_arm64_movw @@ -255,10 +188,6 @@ movk x13, #:gottprel_g0_nc:var movk w12, #:gottprel_g0_nc:var -// CHECK-AARCH64: movk x13, #:gottprel_g0_nc:var // encoding: [0x0d'A',A,0x80'A',0xf2'A'] -// CHECK-AARCH64-NEXT: // fixup A - offset: 0, value: :gottprel_g0_nc:var, kind: fixup_a64_movw_gottprel_g0_nc -// CHECK-AARCH64: movk w12, #:gottprel_g0_nc:var // encoding: [0x0c'A',A,0x80'A',0x72'A'] -// CHECK-AARCH64-NEXT: // fixup A - offset: 0, value: :gottprel_g0_nc:var, kind: fixup_a64_movw_gottprel_g0_nc // CHECK-ARM64: movk x13, #:gottprel_g0_nc:var // encoding: [0bAAA01101,A,0b100AAAAA,0xf2] // CHECK-ARM64: // fixup A - offset: 0, value: :gottprel_g0_nc:var, kind: fixup_arm64_movw @@ -272,12 +201,6 @@ adrp x11, :gottprel:var ldr x10, [x0, #:gottprel_lo12:var] ldr x9, :gottprel:var -// CHECK-AARCH64: adrp x11, :gottprel:var // encoding: [0x0b'A',A,A,0x90'A'] -// CHECK-AARCH64-NEXT: // fixup A - offset: 0, value: :gottprel:var, kind: fixup_a64_adr_gottprel_page -// CHECK-AARCH64: ldr x10, [x0, #:gottprel_lo12:var] // encoding: [0x0a'A',A,0x40'A',0xf9'A'] -// CHECK-AARCH64-NEXT: // fixup A - offset: 0, value: :gottprel_lo12:var, kind: fixup_a64_ld64_gottprel_lo12_nc -// CHECK-AARCH64: ldr x9, :gottprel:var // encoding: [0x09'A',A,A,0x58'A'] -// CHECK-AARCH64-NEXT: // fixup A - offset: 0, value: :gottprel:var, kind: fixup_a64_ld_gottprel_prel19 // CHECK-ARM64: adrp x11, :gottprel:var // encoding: [0x0b'A',A,A,0x90'A'] // CHECK-ARM64: // fixup A - offset: 0, value: :gottprel:var, kind: fixup_arm64_pcrel_adrp_imm21 @@ -294,10 +217,6 @@ // TLS local-exec forms movz x3, #:tprel_g2:var movn x4, #:tprel_g2:var -// CHECK-AARCH64: movz x3, #:tprel_g2:var // encoding: [0x03'A',A,0xc0'A',0x92'A'] -// CHECK-AARCH64-NEXT: // fixup A - offset: 0, value: :tprel_g2:var, kind: fixup_a64_movw_tprel_g2 -// CHECK-AARCH64: movn x4, #:tprel_g2:var // encoding: [0x04'A',A,0xc0'A',0x92'A'] -// CHECK-AARCH64-NEXT: // fixup A - offset: 0, value: :tprel_g2:var, kind: fixup_a64_movw_tprel_g2 // CHECK-ARM64: movz x3, #:tprel_g2:var // encoding: [0bAAA00011,A,0b110AAAAA,0x92] // CHECK-ARM64: // fixup A - offset: 0, value: :tprel_g2:var, kind: fixup_arm64_movw @@ -312,14 +231,6 @@ movn x6, #:tprel_g1:var movz w7, #:tprel_g1:var movn w8, #:tprel_g1:var -// CHECK-AARCH64: movz x5, #:tprel_g1:var // encoding: [0x05'A',A,0xa0'A',0x92'A'] -// CHECK-AARCH64-NEXT: // fixup A - offset: 0, value: :tprel_g1:var, kind: fixup_a64_movw_tprel_g1 -// CHECK-AARCH64: movn x6, #:tprel_g1:var // encoding: [0x06'A',A,0xa0'A',0x92'A'] -// CHECK-AARCH64-NEXT: // fixup A - offset: 0, value: :tprel_g1:var, kind: fixup_a64_movw_tprel_g1 -// CHECK-AARCH64: movz w7, #:tprel_g1:var // encoding: [0x07'A',A,0xa0'A',0x12'A'] -// CHECK-AARCH64-NEXT: // fixup A - offset: 0, value: :tprel_g1:var, kind: fixup_a64_movw_tprel_g1 -// CHECK-AARCH64: movn w8, #:tprel_g1:var // encoding: [0x08'A',A,0xa0'A',0x12'A'] -// CHECK-AARCH64-NEXT: // fixup A - offset: 0, value: :tprel_g1:var, kind: fixup_a64_movw_tprel_g1 // CHECK-ARM64: movz x5, #:tprel_g1:var // encoding: [0bAAA00101,A,0b101AAAAA,0x92] // CHECK-ARM64: // fixup A - offset: 0, value: :tprel_g1:var, kind: fixup_arm64_movw @@ -338,10 +249,6 @@ movk x9, #:tprel_g1_nc:var movk w10, #:tprel_g1_nc:var -// CHECK-AARCH64: movk x9, #:tprel_g1_nc:var // encoding: [0x09'A',A,0xa0'A',0xf2'A'] -// CHECK-AARCH64-NEXT: // fixup A - offset: 0, value: :tprel_g1_nc:var, kind: fixup_a64_movw_tprel_g1_nc -// CHECK-AARCH64: movk w10, #:tprel_g1_nc:var // encoding: [0x0a'A',A,0xa0'A',0x72'A'] -// CHECK-AARCH64-NEXT: // fixup A - offset: 0, value: :tprel_g1_nc:var, kind: fixup_a64_movw_tprel_g1_nc // CHECK-ARM64: movk x9, #:tprel_g1_nc:var // encoding: [0bAAA01001,A,0b101AAAAA,0xf2] // CHECK-ARM64: // fixup A - offset: 0, value: :tprel_g1_nc:var, kind: fixup_arm64_movw @@ -356,14 +263,6 @@ movn x12, #:tprel_g0:var movz w13, #:tprel_g0:var movn w14, #:tprel_g0:var -// CHECK-AARCH64: movz x11, #:tprel_g0:var // encoding: [0x0b'A',A,0x80'A',0x92'A'] -// CHECK-AARCH64-NEXT: // fixup A - offset: 0, value: :tprel_g0:var, kind: fixup_a64_movw_tprel_g0 -// CHECK-AARCH64: movn x12, #:tprel_g0:var // encoding: [0x0c'A',A,0x80'A',0x92'A'] -// CHECK-AARCH64-NEXT: // fixup A - offset: 0, value: :tprel_g0:var, kind: fixup_a64_movw_tprel_g0 -// CHECK-AARCH64: movz w13, #:tprel_g0:var // encoding: [0x0d'A',A,0x80'A',0x12'A'] -// CHECK-AARCH64-NEXT: // fixup A - offset: 0, value: :tprel_g0:var, kind: fixup_a64_movw_tprel_g0 -// CHECK-AARCH64: movn w14, #:tprel_g0:var // encoding: [0x0e'A',A,0x80'A',0x12'A'] -// CHECK-AARCH64-NEXT: // fixup A - offset: 0, value: :tprel_g0:var, kind: fixup_a64_movw_tprel_g0 // CHECK-ARM64: movz x11, #:tprel_g0:var // encoding: [0bAAA01011,A,0b100AAAAA,0x92] // CHECK-ARM64: // fixup A - offset: 0, value: :tprel_g0:var, kind: fixup_arm64_movw @@ -382,10 +281,6 @@ movk x15, #:tprel_g0_nc:var movk w16, #:tprel_g0_nc:var -// CHECK-AARCH64: movk x15, #:tprel_g0_nc:var // encoding: [0x0f'A',A,0x80'A',0xf2'A'] -// CHECK-AARCH64-NEXT: // fixup A - offset: 0, value: :tprel_g0_nc:var, kind: fixup_a64_movw_tprel_g0_nc -// CHECK-AARCH64: movk w16, #:tprel_g0_nc:var // encoding: [0x10'A',A,0x80'A',0x72'A'] -// CHECK-AARCH64-NEXT: // fixup A - offset: 0, value: :tprel_g0_nc:var, kind: fixup_a64_movw_tprel_g0_nc // CHECK-ARM64: movk x15, #:tprel_g0_nc:var // encoding: [0bAAA01111,A,0b100AAAAA,0xf2] // CHECK-ARM64: // fixup A - offset: 0, value: :tprel_g0_nc:var, kind: fixup_arm64_movw @@ -398,10 +293,6 @@ add x17, x18, #:tprel_hi12:var, lsl #12 add w19, w20, #:tprel_hi12:var, lsl #12 -// CHECK-AARCH64: add x17, x18, #:tprel_hi12:var, lsl #12 // encoding: [0x51'A',0x02'A',0x40'A',0x91'A'] -// CHECK-AARCH64-NEXT: // fixup A - offset: 0, value: :tprel_hi12:var, kind: fixup_a64_add_tprel_hi12 -// CHECK-AARCH64: add w19, w20, #:tprel_hi12:var, lsl #12 // encoding: [0x93'A',0x02'A',0x40'A',0x11'A'] -// CHECK-AARCH64-NEXT: // fixup A - offset: 0, value: :tprel_hi12:var, kind: fixup_a64_add_tprel_hi12 // CHECK-ARM64: add x17, x18, :tprel_hi12:var, lsl #12 // encoding: [0x51,0bAAAAAA10,0b00AAAAAA,0x91] // CHECK-ARM64: // fixup A - offset: 0, value: :tprel_hi12:var, kind: fixup_arm64_add_imm12 @@ -414,10 +305,6 @@ add x21, x22, #:tprel_lo12:var add w23, w24, #:tprel_lo12:var -// CHECK-AARCH64: add x21, x22, #:tprel_lo12:var // encoding: [0xd5'A',0x02'A',A,0x91'A'] -// CHECK-AARCH64-NEXT: // fixup A - offset: 0, value: :tprel_lo12:var, kind: fixup_a64_add_tprel_lo12 -// CHECK-AARCH64: add w23, w24, #:tprel_lo12:var // encoding: [0x17'A',0x03'A',A,0x11'A'] -// CHECK-AARCH64-NEXT: // fixup A - offset: 0, value: :tprel_lo12:var, kind: fixup_a64_add_tprel_lo12 // CHECK-ARM64: add x21, x22, :tprel_lo12:var // encoding: [0xd5,0bAAAAAA10,0b00AAAAAA,0x91] // CHECK-ARM64: // fixup A - offset: 0, value: :tprel_lo12:var, kind: fixup_arm64_add_imm12 @@ -430,10 +317,6 @@ add x25, x26, #:tprel_lo12_nc:var add w27, w28, #:tprel_lo12_nc:var -// CHECK-AARCH64: add x25, x26, #:tprel_lo12_nc:var // encoding: [0x59'A',0x03'A',A,0x91'A'] -// CHECK-AARCH64-NEXT: // fixup A - offset: 0, value: :tprel_lo12_nc:var, kind: fixup_a64_add_tprel_lo12_nc -// CHECK-AARCH64: add w27, w28, #:tprel_lo12_nc:var // encoding: [0x9b'A',0x03'A',A,0x11'A'] -// CHECK-AARCH64-NEXT: // fixup A - offset: 0, value: :tprel_lo12_nc:var, kind: fixup_a64_add_tprel_lo12_nc // CHECK-ARM64: add x25, x26, :tprel_lo12_nc:var // encoding: [0x59,0bAAAAAA11,0b00AAAAAA,0x91] // CHECK-ARM64: // fixup A - offset: 0, value: :tprel_lo12_nc:var, kind: fixup_arm64_add_imm12 @@ -446,10 +329,6 @@ ldrb w29, [x30, #:tprel_lo12:var] ldrsb x29, [x28, #:tprel_lo12_nc:var] -// CHECK-AARCH64: ldrb w29, [x30, #:tprel_lo12:var] // encoding: [0xdd'A',0x03'A',0x40'A',0x39'A'] -// CHECK-AARCH64-NEXT: // fixup A - offset: 0, value: :tprel_lo12:var, kind: fixup_a64_ldst8_tprel_lo12 -// CHECK-AARCH64: ldrsb x29, [x28, #:tprel_lo12_nc:var] // encoding: [0x9d'A',0x03'A',0x80'A',0x39'A'] -// CHECK-AARCH64-NEXT: // fixup A - offset: 0, value: :tprel_lo12_nc:var, kind: fixup_a64_ldst8_tprel_lo12_nc // CHECK-ARM64: ldrb w29, [x30, :tprel_lo12:var] // encoding: [0xdd,0bAAAAAA11,0b01AAAAAA,0x39] // CHECK-ARM64: // fixup A - offset: 0, value: :tprel_lo12:var, kind: fixup_arm64_ldst_imm12_scale1 @@ -462,10 +341,6 @@ strh w27, [x26, #:tprel_lo12:var] ldrsh x25, [x24, #:tprel_lo12_nc:var] -// CHECK-AARCH64: strh w27, [x26, #:tprel_lo12:var] // encoding: [0x5b'A',0x03'A',A,0x79'A'] -// CHECK-AARCH64-NEXT: // fixup A - offset: 0, value: :tprel_lo12:var, kind: fixup_a64_ldst16_tprel_lo12 -// CHECK-AARCH64: ldrsh x25, [x24, #:tprel_lo12_nc:var] // encoding: [0x19'A',0x03'A',0x80'A',0x79'A'] -// CHECK-AARCH64-NEXT: // fixup A - offset: 0, value: :tprel_lo12_nc:var, kind: fixup_a64_ldst16_tprel_lo12_n // CHECK-ARM64: strh w27, [x26, :tprel_lo12:var] // encoding: [0x5b,0bAAAAAA11,0b00AAAAAA,0x79] // CHECK-ARM64: // fixup A - offset: 0, value: :tprel_lo12:var, kind: fixup_arm64_ldst_imm12_scale2 @@ -478,10 +353,6 @@ ldr w23, [x22, #:tprel_lo12:var] ldrsw x21, [x20, #:tprel_lo12_nc:var] -// CHECK-AARCH64: ldr w23, [x22, #:tprel_lo12:var] // encoding: [0xd7'A',0x02'A',0x40'A',0xb9'A'] -// CHECK-AARCH64-NEXT: // fixup A - offset: 0, value: :tprel_lo12:var, kind: fixup_a64_ldst32_tprel_lo12 -// CHECK-AARCH64: ldrsw x21, [x20, #:tprel_lo12_nc:var] // encoding: [0x95'A',0x02'A',0x80'A',0xb9'A'] -// CHECK-AARCH64-NEXT: // fixup A - offset: 0, value: :tprel_lo12_nc:var, kind: fixup_a64_ldst32_tprel_lo12_n // CHECK-ARM64: ldr w23, [x22, :tprel_lo12:var] // encoding: [0xd7,0bAAAAAA10,0b01AAAAAA,0xb9] // CHECK-ARM64: // fixup A - offset: 0, value: :tprel_lo12:var, kind: fixup_arm64_ldst_imm12_scale4 @@ -493,10 +364,6 @@ ldr x19, [x18, #:tprel_lo12:var] str x17, [x16, #:tprel_lo12_nc:var] -// CHECK-AARCH64: ldr x19, [x18, #:tprel_lo12:var] // encoding: [0x53'A',0x02'A',0x40'A',0xf9'A'] -// CHECK-AARCH64-NEXT: // fixup A - offset: 0, value: :tprel_lo12:var, kind: fixup_a64_ldst64_tprel_lo12 -// CHECK-AARCH64: str x17, [x16, #:tprel_lo12_nc:var] // encoding: [0x11'A',0x02'A',A,0xf9'A'] -// CHECK-AARCH64-NEXT: // fixup A - offset: 0, value: :tprel_lo12_nc:var, kind: fixup_a64_ldst64_tprel_lo12_nc // CHECK-ARM64: ldr x19, [x18, :tprel_lo12:var] // encoding: [0x53,0bAAAAAA10,0b01AAAAAA,0xf9] // CHECK-ARM64: // fixup A - offset: 0, value: :tprel_lo12:var, kind: fixup_arm64_ldst_imm12_scale8 @@ -513,15 +380,6 @@ .tlsdesccall var blr x3 -// CHECK-AARCH64: adrp x8, :tlsdesc:var // encoding: [0x08'A',A,A,0x90'A'] -// CHECK-AARCH64-NEXT: // fixup A - offset: 0, value: :tlsdesc:var, kind: fixup_a64_tlsdesc_adr_page -// CHECK-AARCH64: ldr x7, [x6, #:tlsdesc_lo12:var] // encoding: [0xc7'A',A,0x40'A',0xf9'A'] -// CHECK-AARCH64-NEXT: // fixup A - offset: 0, value: :tlsdesc_lo12:var, kind: fixup_a64_tlsdesc_ld64_lo12_nc -// CHECK-AARCH64: add x5, x4, #:tlsdesc_lo12:var // encoding: [0x85'A',A,A,0x91'A'] -// CHECK-AARCH64-NEXT: // fixup A - offset: 0, value: :tlsdesc_lo12:var, kind: fixup_a64_tlsdesc_add_lo12_nc -// CHECK-AARCH64: .tlsdesccall var // encoding: [] -// CHECK-AARCH64-NEXT: // fixup A - offset: 0, value: :tlsdesc:var, kind: fixup_a64_tlsdesc_call -// CHECK-AARCH64: blr x3 // encoding: [0x60,0x00,0x3f,0xd6] // CHECK-ARM64: adrp x8, :tlsdesc:var // encoding: [0x08'A',A,A,0x90'A'] // CHECK-ARM64: // fixup A - offset: 0, value: :tlsdesc:var, kind: fixup_arm64_pcrel_adrp_imm21 diff --git a/llvm/test/MC/AArch64/trace-regs-diagnostics.s b/llvm/test/MC/AArch64/trace-regs-diagnostics.s index 04f9d277355..fa57817dd38 100644 --- a/llvm/test/MC/AArch64/trace-regs-diagnostics.s +++ b/llvm/test/MC/AArch64/trace-regs-diagnostics.s @@ -1,4 +1,3 @@ -// RUN: not llvm-mc -triple aarch64-none-linux-gnu < %s 2>&1 | FileCheck %s // RUN: not llvm-mc -triple arm64-none-linux-gnu < %s 2>&1 | FileCheck %s // Write-only mrs x12, trcoslar diff --git a/llvm/test/MC/AArch64/trace-regs.s b/llvm/test/MC/AArch64/trace-regs.s index b763e67c91c..be25f08947b 100644 --- a/llvm/test/MC/AArch64/trace-regs.s +++ b/llvm/test/MC/AArch64/trace-regs.s @@ -1,4 +1,3 @@ -// RUN: llvm-mc -triple=aarch64-none-linux-gnu -show-encoding < %s | FileCheck %s // RUN: llvm-mc -triple=arm64-none-linux-gnu -show-encoding < %s | FileCheck %s mrs x8, trcstatr diff --git a/llvm/test/MC/Disassembler/AArch64/lit.local.cfg b/llvm/test/MC/Disassembler/AArch64/lit.local.cfg index c6f83453ac2..65369741489 100644 --- a/llvm/test/MC/Disassembler/AArch64/lit.local.cfg +++ b/llvm/test/MC/Disassembler/AArch64/lit.local.cfg @@ -1,4 +1,4 @@ targets = set(config.root.targets_to_build.split()) -if 'AArch64' not in targets or 'ARM64' not in targets: +if 'ARM64' not in targets: config.unsupported = True |
