diff options
| author | Simon Dardis <simon.dardis@imgtec.com> | 2016-10-05 15:28:33 +0000 |
|---|---|---|
| committer | Simon Dardis <simon.dardis@imgtec.com> | 2016-10-05 15:28:33 +0000 |
| commit | bbfd5287489fe2a55d71097c6e4914ace20d7d7f (patch) | |
| tree | 02a009dc939f55be1b9640ab4834e191b0b70970 /llvm/test/MC | |
| parent | 0411e8669b82233a645fd6dcdc813e989eef25c6 (diff) | |
| download | bcm5719-llvm-bbfd5287489fe2a55d71097c6e4914ace20d7d7f.tar.gz bcm5719-llvm-bbfd5287489fe2a55d71097c6e4914ace20d7d7f.zip | |
Revert "[mips] Add rsqrt, recip for MIPS"
This reverts commit r282485 which contain two patches instead of
one.
llvm-svn: 283327
Diffstat (limited to 'llvm/test/MC')
53 files changed, 73 insertions, 149 deletions
diff --git a/llvm/test/MC/Disassembler/Mips/micromips32r3/valid-el.txt b/llvm/test/MC/Disassembler/Mips/micromips32r3/valid-el.txt index 84f498754cd..cc391934c5a 100644 --- a/llvm/test/MC/Disassembler/Mips/micromips32r3/valid-el.txt +++ b/llvm/test/MC/Disassembler/Mips/micromips32r3/valid-el.txt @@ -195,7 +195,3 @@ 0xea 0xb8 0x40 0x00 # CHECK: sdc1 $f7, 64($10) 0x46 0xb8 0x04 0x00 # CHECK: sdc1 $f2, 4($6) 0x46 0x98 0x04 0x00 # CHECK: swc1 $f2, 4($6) -0x46,0x56,0x3b,0x52 # CHECK: recip.d $f18, $f6 -0x7e,0x54,0x3b,0x12 # CHECK: recip.s $f3, $f30 -0x5c,0x54,0x3b,0x42 # CHECK: rsqrt.d $f2, $f28 -0x88,0x54,0x3b,0x02 # CHECK: rsqrt.s $f4, $f8 diff --git a/llvm/test/MC/Disassembler/Mips/micromips32r3/valid.txt b/llvm/test/MC/Disassembler/Mips/micromips32r3/valid.txt index 3be26bb5b66..894ac6e048f 100644 --- a/llvm/test/MC/Disassembler/Mips/micromips32r3/valid.txt +++ b/llvm/test/MC/Disassembler/Mips/micromips32r3/valid.txt @@ -199,7 +199,3 @@ 0x00 0x64 0xcd 0x3c # CHECK: cfc2 $3, $4 0x54 0xa6 0x18 0x3b # CHECK: ctc1 $5, $6 0x00 0xe8 0xdd 0x3c # CHECK: ctc2 $7, $8 -0x56 0x46 0x52 0x3b # CHECK: recip.d $f18, $f6 -0x54 0x7e 0x12 0x3b # CHECK: recip.s $f3, $f30 -0x54 0x5c 0x42 0x3b # CHECK: rsqrt.d $f2, $f28 -0x54 0x88 0x02 0x3b # CHECK: rsqrt.s $f4, $f8 diff --git a/llvm/test/MC/Disassembler/Mips/mips32r2/valid-mips32r2-el.txt b/llvm/test/MC/Disassembler/Mips/mips32r2/valid-mips32r2-el.txt index 5a374ac43cb..82a883557e8 100644 --- a/llvm/test/MC/Disassembler/Mips/mips32r2/valid-mips32r2-el.txt +++ b/llvm/test/MC/Disassembler/Mips/mips32r2/valid-mips32r2-el.txt @@ -135,12 +135,8 @@ 0x67 0x45 0xc9 0x34 # CHECK: ori $9, $6, 17767 0xc2 0x49 0x26 0x00 # CHECK: rotr $9, $6, 7 0x46 0x48 0xe6 0x00 # CHECK: rotrv $9, $6, $7 -0x95 0x34 0x20 0x46 # CHECK: recip.d $f18, $f6 -0xd5 0xf0 0x00 0x46 # CHECK: recip.s $f3, $f30 0x0c 0x73 0x20 0x46 # CHECK: round.w.d $f12, $f14 0x8c 0x39 0x00 0x46 # CHECK: round.w.s $f6, $f7 -0x96 0xe0 0x20 0x46 # CHECK: rsqrt.d $f2, $f28 -0x16 0x41 0x00 0x46 # CHECK: rsqrt.s $f4, $f8 0xc6 0x23 0xa4 0xa0 # CHECK: sb $4, 9158($5) 0x06 0x00 0xa4 0xa0 # CHECK: sb $4, 6($5) 0xc6 0x23 0xe9 0xe0 # CHECK: sc $9, 9158($7) diff --git a/llvm/test/MC/Disassembler/Mips/mips32r2/valid-mips32r2.txt b/llvm/test/MC/Disassembler/Mips/mips32r2/valid-mips32r2.txt index 9935929a1cc..7ee4f4bf7fa 100644 --- a/llvm/test/MC/Disassembler/Mips/mips32r2/valid-mips32r2.txt +++ b/llvm/test/MC/Disassembler/Mips/mips32r2/valid-mips32r2.txt @@ -286,10 +286,6 @@ 0x46 0x80 0x5e 0xa1 # CHECK: cvt.d.w $f26, $f11 0x46 0x80 0x73 0x21 # CHECK: cvt.d.w $f12, $f14 0x46 0x80 0x7d 0xa0 # CHECK: cvt.s.w $f22, $f15 -0x46 0x20 0x34 0x95 # CHECK: recip.d $f18, $f6 -0x46 0x00 0xf0 0xd5 # CHECK: recip.s $f3, $f30 -0x46 0x20 0xe0 0x96 # CHECK: rsqrt.d $f2, $f28 -0x46 0x00 0x41 0x16 # CHECK: rsqrt.s $f4, $f8 0x4c 0x52 0xf2 0xa9 # CHECK: msub.d $f10, $f2, $f30, $f18 0x4c 0xa6 0x00 0x05 # CHECK: luxc1 $f0, $6($5) 0x4c 0xac 0xc8 0x30 # CHECK: nmadd.s $f0, $f5, $f25, $f12 diff --git a/llvm/test/MC/Disassembler/Mips/mips32r2/valid-xfail-mips32r2.txt b/llvm/test/MC/Disassembler/Mips/mips32r2/valid-xfail-mips32r2.txt index bc7ae8dd839..da8130c9f4c 100644 --- a/llvm/test/MC/Disassembler/Mips/mips32r2/valid-xfail-mips32r2.txt +++ b/llvm/test/MC/Disassembler/Mips/mips32r2/valid-xfail-mips32r2.txt @@ -70,9 +70,13 @@ 0x46 0xda 0xf2 0x2e # CHECK: pul.ps $f8, $f30, $f26 0x46 0xc2 0x46 0x2f # CHECK: puu.ps $f24, $f8, $f2 0x41 0x49 0x98 0x00 # CHECK: rdpgpr s3, t1 +0x46 0x20 0x34 0x95 # CHECK: recip.d $f18, $f6 +0x46 0x00 0xf0 0xd5 # CHECK: recip.s $f3, $f30 0x02 0xa7 0x68 0x46 # CHECK: rorv t5, a3, s5 0x46 0x20 0x03 0x08 # CHECK: round.l.d $f12, $f0 0x46 0x00 0x2e 0x08 # CHECK: round.l.s $f24, $f5 +0x46 0x20 0xe0 0x96 # CHECK: rsqrt.d $f2, $f28 +0x46 0x00 0x41 0x16 # CHECK: rsqrt.s $f4, $f8 0x46 0xda 0x71 0x01 # CHECK: sub.ps $f4, $f14, $f26 0x46 0x20 0xb5 0x89 # CHECK: trunc.l.d $f22, $f22 0x46 0x00 0xff 0x09 # CHECK: trunc.l.s $f28, $f31 diff --git a/llvm/test/MC/Disassembler/Mips/mips32r3/valid-mips32r3-el.txt b/llvm/test/MC/Disassembler/Mips/mips32r3/valid-mips32r3-el.txt index 96c7805e216..37c14de4cb6 100644 --- a/llvm/test/MC/Disassembler/Mips/mips32r3/valid-mips32r3-el.txt +++ b/llvm/test/MC/Disassembler/Mips/mips32r3/valid-mips32r3-el.txt @@ -129,14 +129,10 @@ 0x78 0x98 0x04 0x4f # CHECK: nmsub.s $f1, $f24, $f19, $f4 0x25 0x18 0x65 0x00 # CHECK: or $3, $3, $5 0x67 0x45 0xc9 0x34 # CHECK: ori $9, $6, 17767 -0x95 0x34 0x20 0x46 # CHECK: recip.d $f18, $f6 -0xd5 0xf0 0x00 0x46 # CHECK: recip.s $f3, $f30 0xc2 0x49 0x26 0x00 # CHECK: rotr $9, $6, 7 0x46 0x48 0xe6 0x00 # CHECK: rotrv $9, $6, $7 0x0c 0x73 0x20 0x46 # CHECK: round.w.d $f12, $f14 0x8c 0x39 0x00 0x46 # CHECK: round.w.s $f6, $f7 -0x96 0xe0 0x20 0x46 # CHECK: rsqrt.d $f2, $f28 -0x16 0x41 0x00 0x46 # CHECK: rsqrt.s $f4, $f8 0xc6 0x23 0xa4 0xa0 # CHECK: sb $4, 9158($5) 0x06 0x00 0xa4 0xa0 # CHECK: sb $4, 6($5) 0xc6 0x23 0xe9 0xe0 # CHECK: sc $9, 9158($7) diff --git a/llvm/test/MC/Disassembler/Mips/mips32r3/valid-mips32r3.txt b/llvm/test/MC/Disassembler/Mips/mips32r3/valid-mips32r3.txt index 9be0189e6bf..8e5c16b4a33 100644 --- a/llvm/test/MC/Disassembler/Mips/mips32r3/valid-mips32r3.txt +++ b/llvm/test/MC/Disassembler/Mips/mips32r3/valid-mips32r3.txt @@ -283,10 +283,6 @@ 0x46 0x80 0x5e 0xa1 # CHECK: cvt.d.w $f26, $f11 0x46 0x80 0x73 0x21 # CHECK: cvt.d.w $f12, $f14 0x46 0x80 0x7d 0xa0 # CHECK: cvt.s.w $f22, $f15 -0x46 0x20 0x34 0x95 # CHECK: recip.d $f18, $f6 -0x46 0x00 0xf0 0xd5 # CHECK: recip.s $f3, $f30 -0x46 0x20 0xe0 0x96 # CHECK: rsqrt.d $f2, $f28 -0x46 0x00 0x41 0x16 # CHECK: rsqrt.s $f4, $f8 0x4c 0x52 0xf2 0xa9 # CHECK: msub.d $f10, $f2, $f30, $f18 0x4c 0xa6 0x00 0x05 # CHECK: luxc1 $f0, $6($5) 0x4c 0xac 0xc8 0x30 # CHECK: nmadd.s $f0, $f5, $f25, $f12 diff --git a/llvm/test/MC/Disassembler/Mips/mips32r3/valid-xfail-mips32r3.txt b/llvm/test/MC/Disassembler/Mips/mips32r3/valid-xfail-mips32r3.txt index 5d317edd465..7623bba364f 100644 --- a/llvm/test/MC/Disassembler/Mips/mips32r3/valid-xfail-mips32r3.txt +++ b/llvm/test/MC/Disassembler/Mips/mips32r3/valid-xfail-mips32r3.txt @@ -70,9 +70,13 @@ 0x46 0xda 0xf2 0x2e # CHECK: pul.ps $f8, $f30, $f26 0x46 0xc2 0x46 0x2f # CHECK: puu.ps $f24, $f8, $f2 0x41 0x49 0x98 0x00 # CHECK: rdpgpr s3, t1 +0x46 0x20 0x34 0x95 # CHECK: recip.d $f18, $f6 +0x46 0x00 0xf0 0xd5 # CHECK: recip.s $f3, $f30 0x02 0xa7 0x68 0x46 # CHECK: rorv t5, a3, s5 0x46 0x20 0x03 0x08 # CHECK: round.l.d $f12, $f0 0x46 0x00 0x2e 0x08 # CHECK: round.l.s $f24, $f5 +0x46 0x20 0xe0 0x96 # CHECK: rsqrt.d $f2, $f28 +0x46 0x00 0x41 0x16 # CHECK: rsqrt.s $f4, $f8 0x46 0xda 0x71 0x01 # CHECK: sub.ps $f4, $f14, $f26 0x46 0x20 0xb5 0x89 # CHECK: trunc.l.d $f22, $f22 0x46 0x00 0xff 0x09 # CHECK: trunc.l.s $f28, $f31 diff --git a/llvm/test/MC/Disassembler/Mips/mips32r5/valid-mips32r5-el.txt b/llvm/test/MC/Disassembler/Mips/mips32r5/valid-mips32r5-el.txt index 072e17b6151..b68089b0a07 100644 --- a/llvm/test/MC/Disassembler/Mips/mips32r5/valid-mips32r5-el.txt +++ b/llvm/test/MC/Disassembler/Mips/mips32r5/valid-mips32r5-el.txt @@ -131,12 +131,8 @@ 0x67 0x45 0xc9 0x34 # CHECK: ori $9, $6, 17767 0xc2 0x49 0x26 0x00 # CHECK: rotr $9, $6, 7 0x46 0x48 0xe6 0x00 # CHECK: rotrv $9, $6, $7 -0x95 0x34 0x20 0x46 # CHECK: recip.d $f18, $f6 -0xd5 0xf0 0x00 0x46 # CHECK: recip.s $f3, $f30 0x0c 0x73 0x20 0x46 # CHECK: round.w.d $f12, $f14 0x8c 0x39 0x00 0x46 # CHECK: round.w.s $f6, $f7 -0x96 0xe0 0x20 0x46 # CHECK: rsqrt.d $f2, $f28 -0x16 0x41 0x00 0x46 # CHECK: rsqrt.s $f4, $f8 0xc6 0x23 0xa4 0xa0 # CHECK: sb $4, 9158($5) 0x06 0x00 0xa4 0xa0 # CHECK: sb $4, 6($5) 0xc6 0x23 0xe9 0xe0 # CHECK: sc $9, 9158($7) diff --git a/llvm/test/MC/Disassembler/Mips/mips32r5/valid-mips32r5.txt b/llvm/test/MC/Disassembler/Mips/mips32r5/valid-mips32r5.txt index ecb64ccdea2..afe1b695dea 100644 --- a/llvm/test/MC/Disassembler/Mips/mips32r5/valid-mips32r5.txt +++ b/llvm/test/MC/Disassembler/Mips/mips32r5/valid-mips32r5.txt @@ -284,10 +284,6 @@ 0x46 0x80 0x5e 0xa1 # CHECK: cvt.d.w $f26, $f11 0x46 0x80 0x73 0x21 # CHECK: cvt.d.w $f12, $f14 0x46 0x80 0x7d 0xa0 # CHECK: cvt.s.w $f22, $f15 -0x46 0x20 0x34 0x95 # CHECK: recip.d $f18, $f6 -0x46 0x00 0xf0 0xd5 # CHECK: recip.s $f3, $f30 -0x46 0x20 0xe0 0x96 # CHECK: rsqrt.d $f2, $f28 -0x46 0x00 0x41 0x16 # CHECK: rsqrt.s $f4, $f8 0x4c 0x52 0xf2 0xa9 # CHECK: msub.d $f10, $f2, $f30, $f18 0x4c 0xa6 0x00 0x05 # CHECK: luxc1 $f0, $6($5) 0x4c 0xac 0xc8 0x30 # CHECK: nmadd.s $f0, $f5, $f25, $f12 diff --git a/llvm/test/MC/Disassembler/Mips/mips32r5/valid-xfail-mips32r5.txt b/llvm/test/MC/Disassembler/Mips/mips32r5/valid-xfail-mips32r5.txt index ed9bc08d72d..27f5498ea66 100644 --- a/llvm/test/MC/Disassembler/Mips/mips32r5/valid-xfail-mips32r5.txt +++ b/llvm/test/MC/Disassembler/Mips/mips32r5/valid-xfail-mips32r5.txt @@ -70,9 +70,13 @@ 0x46 0xda 0xf2 0x2e # CHECK: pul.ps $f8, $f30, $f26 0x46 0xc2 0x46 0x2f # CHECK: puu.ps $f24, $f8, $f2 0x41 0x49 0x98 0x00 # CHECK: rdpgpr s3, t1 +0x46 0x20 0x34 0x95 # CHECK: recip.d $f18, $f6 +0x46 0x00 0xf0 0xd5 # CHECK: recip.s $f3, $f30 0x02 0xa7 0x68 0x46 # CHECK: rorv t5, a3, s5 0x46 0x20 0x03 0x08 # CHECK: round.l.d $f12, $f0 0x46 0x00 0x2e 0x08 # CHECK: round.l.s $f24, $f5 +0x46 0x20 0xe0 0x96 # CHECK: rsqrt.d $f2, $f28 +0x46 0x00 0x41 0x16 # CHECK: rsqrt.s $f4, $f8 0x46 0xda 0x71 0x01 # CHECK: sub.ps $f4, $f14, $f26 0x46 0x20 0xb5 0x89 # CHECK: trunc.l.d $f22, $f22 0x46 0x00 0xff 0x09 # CHECK: trunc.l.s $f28, $f31 diff --git a/llvm/test/MC/Disassembler/Mips/mips32r6/valid-mips32r6-el.txt b/llvm/test/MC/Disassembler/Mips/mips32r6/valid-mips32r6-el.txt index 271ff904f17..34bfd769f2d 100644 --- a/llvm/test/MC/Disassembler/Mips/mips32r6/valid-mips32r6-el.txt +++ b/llvm/test/MC/Disassembler/Mips/mips32r6/valid-mips32r6-el.txt @@ -125,12 +125,8 @@ 0x14 0x10 0x24 0x46 # CHECK: seleqz.d $f0, $f2, $f4 0x17 0x10 0x04 0x46 # CHECK: selnez.s $f0, $f2, $f4 0x17 0x10 0x24 0x46 # CHECK: selnez.d $f0, $f2, $f4 -0x95 0x34 0x20 0x46 # CHECK: recip.d $f18, $f6 -0xd5 0xf0 0x00 0x46 # CHECK: recip.s $f3, $f30 0x9a 0x20 0x00 0x46 # CHECK: rint.s $f2, $f4 0x9a 0x20 0x20 0x46 # CHECK: rint.d $f2, $f4 -0x96 0xe0 0x20 0x46 # CHECK: rsqrt.d $f2, $f28 -0x16 0x41 0x00 0x46 # CHECK: rsqrt.s $f4, $f8 0x9b 0x20 0x00 0x46 # CHECK: class.s $f2, $f4 0x9b 0x20 0x20 0x46 # CHECK: class.d $f2, $f4 0x09 0x04 0x80 0x00 # CHECK: jr.hb $4 diff --git a/llvm/test/MC/Disassembler/Mips/mips32r6/valid-mips32r6.txt b/llvm/test/MC/Disassembler/Mips/mips32r6/valid-mips32r6.txt index b796f48d566..7266848706d 100644 --- a/llvm/test/MC/Disassembler/Mips/mips32r6/valid-mips32r6.txt +++ b/llvm/test/MC/Disassembler/Mips/mips32r6/valid-mips32r6.txt @@ -134,10 +134,6 @@ 0x46 0xa4 0x18 0x8d # CHECK: cmp.sult.d $f2, $f3, $f4 0x46 0xa4 0x18 0x8e # CHECK: cmp.sle.d $f2, $f3, $f4 0x46 0xa4 0x18 0x8f # CHECK: cmp.sule.d $f2, $f3, $f4 -0x46 0x20 0x34 0x95 # CHECK: recip.d $f18, $f6 -0x46 0x00 0xf0 0xd5 # CHECK: recip.s $f3, $f30 -0x46 0x20 0xe0 0x96 # CHECK: rsqrt.d $f2, $f28 -0x46 0x00 0x41 0x16 # CHECK: rsqrt.s $f4, $f8 0x42 0x00 0x00 0x58 # CHECK: eretnc # FIXME: The encode/decode functions are not inverses of each other. # The immediate should be 8 but the disassembler currently emits 12 diff --git a/llvm/test/MC/Disassembler/Mips/mips4/valid-mips4-el.txt b/llvm/test/MC/Disassembler/Mips/mips4/valid-mips4-el.txt index 64c350e45a8..4a3d78cde55 100644 --- a/llvm/test/MC/Disassembler/Mips/mips4/valid-mips4-el.txt +++ b/llvm/test/MC/Disassembler/Mips/mips4/valid-mips4-el.txt @@ -155,15 +155,11 @@ 0x27 0x38 0x07 0x00 # CHECK: nor $7, $zero, $7 0x25 0x60 0x1d 0x02 # CHECK: or $12, $16, $sp 0x04 0x00 0x42 0x34 # CHECK: ori $2, $2, 4 -0x08 0x00 0xa1 0xcc # CHECK: pref 1, 8($5) -0x95 0x34 0x20 0x46 # CHECK: recip.d $f18, $f6 -0xd5 0xf0 0x00 0x46 # CHECK: recip.s $f3, $f30 +0x08 0x00 0xa1 0xcc # CHECK: pref 1, 8($5) 0x08 0x0b 0x20 0x46 # CHECK: round.l.d $f12, $f1 0x48 0x2e 0x00 0x46 # CHECK: round.l.s $f25, $f5 0x8c 0x21 0x20 0x46 # CHECK: round.w.d $f6, $f4 0xcc 0xe6 0x00 0x46 # CHECK: round.w.s $f27, $f28 -0x96 0xe0 0x20 0x46 # CHECK: rsqrt.d $f2, $f28 -0x16 0x41 0x00 0x46 # CHECK: rsqrt.s $f4, $f8 0x6f 0xb2 0xd6 0xa1 # CHECK: sb $22, -19857($14) 0xd8 0x49 0x6f 0xe2 # CHECK: sc $15, 18904($19) 0xcd 0xdf 0xaf 0xf3 # CHECK: scd $15, -8243($sp) diff --git a/llvm/test/MC/Disassembler/Mips/mips4/valid-mips4.txt b/llvm/test/MC/Disassembler/Mips/mips4/valid-mips4.txt index 2635b6bca7d..f225d2cc220 100644 --- a/llvm/test/MC/Disassembler/Mips/mips4/valid-mips4.txt +++ b/llvm/test/MC/Disassembler/Mips/mips4/valid-mips4.txt @@ -257,7 +257,3 @@ 0xf5 0xbe 0x77 0x6e # CHECK: sdc1 $f30, 30574($13) 0xfa 0x54 0x5a 0x75 # CHECK: sdc2 $20, 23157($18) 0xfd 0x4c 0x16 0xcb # CHECK: sd $12, 5835($10) -0x46 0x20 0x34 0xd5 # CHECK: recip.d $f19, $f6 -0x46 0x00 0xf0 0xd5 # CHECK: recip.s $f3, $f30 -0x46 0x20 0xe0 0xd6 # CHECK: rsqrt.d $f3, $f28 -0x46 0x00 0x41 0x16 # CHECK: rsqrt.s $f4, $f8 diff --git a/llvm/test/MC/Disassembler/Mips/mips4/valid-xfail-mips4.txt b/llvm/test/MC/Disassembler/Mips/mips4/valid-xfail-mips4.txt index 1b669389e7b..3375bcf3140 100644 --- a/llvm/test/MC/Disassembler/Mips/mips4/valid-xfail-mips4.txt +++ b/llvm/test/MC/Disassembler/Mips/mips4/valid-xfail-mips4.txt @@ -36,3 +36,7 @@ 0x4c 0xac 0xc8 0x30 # CHECK: nmadd.s $f0, $f5, $f25, $f12 0x4d 0x1e 0x87 0xb9 # CHECK: nmsub.d $f30, $f8, $f16, $f30 0x4f 0x04 0x98 0x78 # CHECK: nmsub.s $f1, $f24, $f19, $f4 +0x46 0x20 0x34 0xd5 # CHECK: recip.d $f19, $f6 +0x46 0x00 0xf0 0xd5 # CHECK: recip.s $f3, $f30 +0x46 0x20 0xe0 0xd6 # CHECK: rsqrt.d $f3, $f28 +0x46 0x00 0x41 0x16 # CHECK: rsqrt.s $f4, $f8 diff --git a/llvm/test/MC/Disassembler/Mips/mips64/valid-mips64-el.txt b/llvm/test/MC/Disassembler/Mips/mips64/valid-mips64-el.txt index eb531aad882..1cd7b0bceba 100644 --- a/llvm/test/MC/Disassembler/Mips/mips64/valid-mips64-el.txt +++ b/llvm/test/MC/Disassembler/Mips/mips64/valid-mips64-el.txt @@ -206,10 +206,6 @@ 0x10 0x00 0xa4 0xa8 # CHECK: swl $4, 16($5) 0x10 0x00 0xe6 0xb8 # CHECK: swr $6, 16($7) 0xcf 0x01 0x00 0x00 # CHECK: sync 7 -0x95 0x34 0x20 0x46 # CHECK: recip.d $f18, $f6 -0xd5 0xf0 0x00 0x46 # CHECK: recip.s $f3, $f30 -0x96 0xe0 0x20 0x46 # CHECK: rsqrt.d $f2, $f28 -0x16 0x41 0x00 0x46 # CHECK: rsqrt.s $f4, $f8 0xc9 0xbd 0x20 0x46 # CHECK: trunc.l.d $f23, $f23 0x09 0xff 0x00 0x46 # CHECK: trunc.l.s $f28, $f31 0x0d 0x73 0x20 0x46 # CHECK: trunc.w.d $f12, $f14 diff --git a/llvm/test/MC/Disassembler/Mips/mips64/valid-mips64-xfail.txt b/llvm/test/MC/Disassembler/Mips/mips64/valid-mips64-xfail.txt index bb6807a25da..dd97bcd5a1f 100644 --- a/llvm/test/MC/Disassembler/Mips/mips64/valid-mips64-xfail.txt +++ b/llvm/test/MC/Disassembler/Mips/mips64/valid-mips64-xfail.txt @@ -73,4 +73,8 @@ 0x46 0xdd 0xd0 0x6d # CHECK: plu.ps $f1, $f26, $f29 0x46 0xda 0xf2 0x6e # CHECK: pul.ps $f9, $f30, $f26 0x46 0xc2 0x4e 0x2f # CHECK: puu.ps $f24, $f9, $f2 +0x46 0x20 0x34 0xd5 # CHECK: recip.d $f19, $f6 +0x46 0x00 0xf0 0xd5 # CHECK: recip.s $f3, $f30 +0x46 0x20 0xe0 0xd6 # CHECK: rsqrt.d $f3, $f28 +0x46 0x00 0x41 0x16 # CHECK: rsqrt.s $f4, $f8 0x46 0xda 0x71 0x41 # CHECK: sub.ps $f5, $f14, $f26 diff --git a/llvm/test/MC/Disassembler/Mips/mips64/valid-mips64.txt b/llvm/test/MC/Disassembler/Mips/mips64/valid-mips64.txt index 8a6bf0ce613..5b5427db1e1 100644 --- a/llvm/test/MC/Disassembler/Mips/mips64/valid-mips64.txt +++ b/llvm/test/MC/Disassembler/Mips/mips64/valid-mips64.txt @@ -331,10 +331,6 @@ 0x46 0x80 0x5e 0xa1 # CHECK: cvt.d.w $f26, $f11 0x46 0x80 0x73 0x21 # CHECK: cvt.d.w $f12, $f14 0x46 0x80 0x7d 0xa0 # CHECK: cvt.s.w $f22, $f15 -0x46 0x20 0x34 0xd5 # CHECK: recip.d $f19, $f6 -0x46 0x00 0xf0 0xd5 # CHECK: recip.s $f3, $f30 -0x46 0x20 0xe0 0xd6 # CHECK: rsqrt.d $f3, $f28 -0x46 0x00 0x41 0x16 # CHECK: rsqrt.s $f4, $f8 0x48 0x20 0x50 0x00 # CHECK: dmfc2 $zero, $10, 0 0x48 0xa4 0x50 0x00 # CHECK: dmtc2 $4, $10, 0 0x4d 0x0c 0xe0 0x21 # CHECK: madd.d $f0, $f8, $f28, $f12 diff --git a/llvm/test/MC/Disassembler/Mips/mips64r2/valid-mips64r2-el.txt b/llvm/test/MC/Disassembler/Mips/mips64r2/valid-mips64r2-el.txt index cc74ce95ae3..3f2b7615eb3 100644 --- a/llvm/test/MC/Disassembler/Mips/mips64r2/valid-mips64r2-el.txt +++ b/llvm/test/MC/Disassembler/Mips/mips64r2/valid-mips64r2-el.txt @@ -193,16 +193,12 @@ 0x78 0x98 0x04 0x4f # CHECK: nmsub.s $f1, $f24, $f19, $f4 0x25 0x18 0x65 0x00 # CHECK: or $3, $3, $5 0x67 0x45 0xc9 0x34 # CHECK: ori $9, $6, 17767 -0x95 0x34 0x20 0x46 # CHECK: recip.d $f18, $f6 -0xd5 0xf0 0x00 0x46 # CHECK: recip.s $f3, $f30 0xc2 0x49 0x26 0x00 # CHECK: rotr $9, $6, 7 0x46 0x48 0xe6 0x00 # CHECK: rotrv $9, $6, $7 0x08 0x0b 0x20 0x46 # CHECK: round.l.d $f12, $f1 0x48 0x2e 0x00 0x46 # CHECK: round.l.s $f25, $f5 0x0c 0x73 0x20 0x46 # CHECK: round.w.d $f12, $f14 0x8c 0x39 0x00 0x46 # CHECK: round.w.s $f6, $f7 -0x96 0xe0 0x20 0x46 # CHECK: rsqrt.d $f2, $f28 -0x16 0x41 0x00 0x46 # CHECK: rsqrt.s $f4, $f8 0xc6 0x23 0xa4 0xa0 # CHECK: sb $4, 9158($5) 0x06 0x00 0xa4 0xa0 # CHECK: sb $4, 6($5) 0xc6 0x23 0xe9 0xe0 # CHECK: sc $9, 9158($7) diff --git a/llvm/test/MC/Disassembler/Mips/mips64r2/valid-mips64r2.txt b/llvm/test/MC/Disassembler/Mips/mips64r2/valid-mips64r2.txt index ab857a55c7b..5de751234c8 100644 --- a/llvm/test/MC/Disassembler/Mips/mips64r2/valid-mips64r2.txt +++ b/llvm/test/MC/Disassembler/Mips/mips64r2/valid-mips64r2.txt @@ -363,10 +363,6 @@ 0x5d 0x40 0xfc 0x59 # CHECK: bgtzl $10, -3736 0x46 0xa0 0x81 0x21 # CHECK: cvt.d.l $f4, $f16 0x46 0xa0 0xf3 0xe0 # CHECK: cvt.s.l $f15, $f30 -0x46 0x20 0x34 0x95 # CHECK: recip.d $f18, $f6 -0x46 0x00 0xf0 0xd5 # CHECK: recip.s $f3, $f30 -0x46 0x20 0xe0 0x96 # CHECK: rsqrt.d $f2, $f28 -0x46 0x00 0x41 0x16 # CHECK: rsqrt.s $f4, $f8 0x4c 0xa6 0x00 0x05 # CHECK: luxc1 $f0, $6($5) 0x4c 0xac 0xc8 0x30 # CHECK: nmadd.s $f0, $f5, $f25, $f12 0x4c 0xb8 0x20 0x0d # CHECK: suxc1 $f4, $24($5) diff --git a/llvm/test/MC/Disassembler/Mips/mips64r2/valid-xfail-mips64r2.txt b/llvm/test/MC/Disassembler/Mips/mips64r2/valid-xfail-mips64r2.txt index 145dcacb1f5..cbc2eee3fe1 100644 --- a/llvm/test/MC/Disassembler/Mips/mips64r2/valid-xfail-mips64r2.txt +++ b/llvm/test/MC/Disassembler/Mips/mips64r2/valid-xfail-mips64r2.txt @@ -67,6 +67,10 @@ 0x46 0xda 0xf2 0x2e # CHECK: pul.ps $f8, $f30, $f26 0x46 0xc2 0x46 0x2f # CHECK: puu.ps $f24, $f8, $f2 0x41 0x49 0x98 0x00 # CHECK: rdpgpr s3, t1 +0x46 0x20 0x34 0x95 # CHECK: recip.d $f18, $f6 +0x46 0x00 0xf0 0xd5 # CHECK: recip.s $f3, $f30 0x02 0xa7 0x68 0x46 # CHECK: rorv t5, a3, s5 +0x46 0x20 0xe0 0x96 # CHECK: rsqrt.d $f2, $f28 +0x46 0x00 0x41 0x16 # CHECK: rsqrt.s $f4, $f8 0x46 0xda 0x71 0x01 # CHECK: sub.ps $f4, $f14, $f26 0x41 0xcd 0x00 0x00 # CHECK: wrpgpr zero, t5 diff --git a/llvm/test/MC/Disassembler/Mips/mips64r3/valid-mips64r3-el.txt b/llvm/test/MC/Disassembler/Mips/mips64r3/valid-mips64r3-el.txt index 31618400d93..7d59ef6d3e0 100644 --- a/llvm/test/MC/Disassembler/Mips/mips64r3/valid-mips64r3-el.txt +++ b/llvm/test/MC/Disassembler/Mips/mips64r3/valid-mips64r3-el.txt @@ -190,16 +190,12 @@ 0x78 0x98 0x04 0x4f # CHECK: nmsub.s $f1, $f24, $f19, $f4 0x25 0x18 0x65 0x00 # CHECK: or $3, $3, $5 0x67 0x45 0xc9 0x34 # CHECK: ori $9, $6, 17767 -0x95 0x34 0x20 0x46 # CHECK: recip.d $f18, $f6 -0xd5 0xf0 0x00 0x46 # CHECK: recip.s $f3, $f30 0xc2 0x49 0x26 0x00 # CHECK: rotr $9, $6, 7 0x46 0x48 0xe6 0x00 # CHECK: rotrv $9, $6, $7 0x08 0x0b 0x20 0x46 # CHECK: round.l.d $f12, $f1 0x48 0x2e 0x00 0x46 # CHECK: round.l.s $f25, $f5 0x0c 0x73 0x20 0x46 # CHECK: round.w.d $f12, $f14 0x8c 0x39 0x00 0x46 # CHECK: round.w.s $f6, $f7 -0x96 0xe0 0x20 0x46 # CHECK: rsqrt.d $f2, $f28 -0x16 0x41 0x00 0x46 # CHECK: rsqrt.s $f4, $f8 0xc6 0x23 0xa4 0xa0 # CHECK: sb $4, 9158($5) 0x06 0x00 0xa4 0xa0 # CHECK: sb $4, 6($5) 0xc6 0x23 0xe9 0xe0 # CHECK: sc $9, 9158($7) diff --git a/llvm/test/MC/Disassembler/Mips/mips64r3/valid-mips64r3.txt b/llvm/test/MC/Disassembler/Mips/mips64r3/valid-mips64r3.txt index 7dd8d64f5c0..01c02ad8222 100644 --- a/llvm/test/MC/Disassembler/Mips/mips64r3/valid-mips64r3.txt +++ b/llvm/test/MC/Disassembler/Mips/mips64r3/valid-mips64r3.txt @@ -351,12 +351,8 @@ 0x46 0x80 0x5e 0xa1 # CHECK: cvt.d.w $f26, $f11 0x46 0x80 0x73 0x21 # CHECK: cvt.d.w $f12, $f14 0x46 0x80 0x7d 0xa0 # CHECK: cvt.s.w $f22, $f15 -0x46 0x20 0x34 0x95 # CHECK: recip.d $f18, $f6 -0x46 0x00 0xf0 0xd5 # CHECK: recip.s $f3, $f30 -0x46 0x20 0xe0 0x96 # CHECK: rsqrt.d $f2, $f28 -0x46 0x00 0x41 0x16 # CHECK: rsqrt.s $f4, $f8 -0x48 0x20 0x50 0x00 # CHECK: dmfc2 $zero, $10, 0 -0x48 0xa4 0x50 0x00 # CHECK: dmtc2 $4, $10, 0 +0x48 0x20 0x50 0x00 # CHECK: dmfc2 $zero, $10, 0 +0x48 0xa4 0x50 0x00 # CHECK: dmtc2 $4, $10, 0 0x4d 0x0c 0xe0 0x21 # CHECK: madd.d $f0, $f8, $f28, $f12 0x4d 0xbb 0x0d 0xe0 # CHECK: madd.s $f23, $f13, $f1, $f27 0x51 0xd3 0x0c 0x40 # CHECK: beql $14, $19, 12548 diff --git a/llvm/test/MC/Disassembler/Mips/mips64r3/valid-xfail-mips64r3.txt b/llvm/test/MC/Disassembler/Mips/mips64r3/valid-xfail-mips64r3.txt index 74ae59669f5..8c58eb1c9e3 100644 --- a/llvm/test/MC/Disassembler/Mips/mips64r3/valid-xfail-mips64r3.txt +++ b/llvm/test/MC/Disassembler/Mips/mips64r3/valid-xfail-mips64r3.txt @@ -67,6 +67,10 @@ 0x46 0xda 0xf2 0x2e # CHECK: pul.ps $f8, $f30, $f26 0x46 0xc2 0x46 0x2f # CHECK: puu.ps $f24, $f8, $f2 0x41 0x49 0x98 0x00 # CHECK: rdpgpr s3, t1 +0x46 0x20 0x34 0x95 # CHECK: recip.d $f18, $f6 +0x46 0x00 0xf0 0xd5 # CHECK: recip.s $f3, $f30 0x02 0xa7 0x68 0x46 # CHECK: rorv t5, a3, s5 +0x46 0x20 0xe0 0x96 # CHECK: rsqrt.d $f2, $f28 +0x46 0x00 0x41 0x16 # CHECK: rsqrt.s $f4, $f8 0x46 0xda 0x71 0x01 # CHECK: sub.ps $f4, $f14, $f26 0x41 0xcd 0x00 0x00 # CHECK: wrpgpr zero, t5 diff --git a/llvm/test/MC/Disassembler/Mips/mips64r5/valid-mips64r5-el.txt b/llvm/test/MC/Disassembler/Mips/mips64r5/valid-mips64r5-el.txt index 5cc0aa6b716..ee6ad1c7194 100644 --- a/llvm/test/MC/Disassembler/Mips/mips64r5/valid-mips64r5-el.txt +++ b/llvm/test/MC/Disassembler/Mips/mips64r5/valid-mips64r5-el.txt @@ -190,16 +190,12 @@ 0x78 0x98 0x04 0x4f # CHECK: nmsub.s $f1, $f24, $f19, $f4 0x25 0x18 0x65 0x00 # CHECK: or $3, $3, $5 0x67 0x45 0xc9 0x34 # CHECK: ori $9, $6, 17767 -0x95 0x34 0x20 0x46 # CHECK: recip.d $f18, $f6 -0xd5 0xf0 0x00 0x46 # CHECK: recip.s $f3, $f30 0xc2 0x49 0x26 0x00 # CHECK: rotr $9, $6, 7 0x46 0x48 0xe6 0x00 # CHECK: rotrv $9, $6, $7 0x08 0x0b 0x20 0x46 # CHECK: round.l.d $f12, $f1 0x48 0x2e 0x00 0x46 # CHECK: round.l.s $f25, $f5 0x0c 0x73 0x20 0x46 # CHECK: round.w.d $f12, $f14 0x8c 0x39 0x00 0x46 # CHECK: round.w.s $f6, $f7 -0x96 0xe0 0x20 0x46 # CHECK: rsqrt.d $f2, $f28 -0x16 0x41 0x00 0x46 # CHECK: rsqrt.s $f4, $f8 0xc6 0x23 0xa4 0xa0 # CHECK: sb $4, 9158($5) 0x06 0x00 0xa4 0xa0 # CHECK: sb $4, 6($5) 0xc6 0x23 0xe9 0xe0 # CHECK: sc $9, 9158($7) diff --git a/llvm/test/MC/Disassembler/Mips/mips64r5/valid-mips64r5.txt b/llvm/test/MC/Disassembler/Mips/mips64r5/valid-mips64r5.txt index f2467e8e480..12e5294d36d 100644 --- a/llvm/test/MC/Disassembler/Mips/mips64r5/valid-mips64r5.txt +++ b/llvm/test/MC/Disassembler/Mips/mips64r5/valid-mips64r5.txt @@ -351,10 +351,6 @@ 0x46 0x80 0x5e 0xa1 # CHECK: cvt.d.w $f26, $f11 0x46 0x80 0x73 0x21 # CHECK: cvt.d.w $f12, $f14 0x46 0x80 0x7d 0xa0 # CHECK: cvt.s.w $f22, $f15 -0x46 0x20 0x34 0x95 # CHECK: recip.d $f18, $f6 -0x46 0x00 0xf0 0xd5 # CHECK: recip.s $f3, $f30 -0x46 0x20 0xe0 0x96 # CHECK: rsqrt.d $f2, $f28 -0x46 0x00 0x41 0x16 # CHECK: rsqrt.s $f4, $f8 0x48 0x20 0x50 0x00 # CHECK: dmfc2 $zero, $10, 0 0x48 0xa4 0x50 0x00 # CHECK: dmtc2 $4, $10, 0 0x4d 0x0c 0xe0 0x21 # CHECK: madd.d $f0, $f8, $f28, $f12 diff --git a/llvm/test/MC/Disassembler/Mips/mips64r5/valid-xfail-mips64r5.txt b/llvm/test/MC/Disassembler/Mips/mips64r5/valid-xfail-mips64r5.txt index 2d02fca4b7c..b8a98bdf73e 100644 --- a/llvm/test/MC/Disassembler/Mips/mips64r5/valid-xfail-mips64r5.txt +++ b/llvm/test/MC/Disassembler/Mips/mips64r5/valid-xfail-mips64r5.txt @@ -67,6 +67,10 @@ 0x46 0xda 0xf2 0x2e # CHECK: pul.ps $f8, $f30, $f26 0x46 0xc2 0x46 0x2f # CHECK: puu.ps $f24, $f8, $f2 0x41 0x49 0x98 0x00 # CHECK: rdpgpr s3, t1 +0x46 0x20 0x34 0x95 # CHECK: recip.d $f18, $f6 +0x46 0x00 0xf0 0xd5 # CHECK: recip.s $f3, $f30 0x02 0xa7 0x68 0x46 # CHECK: rorv t5, a3, s5 +0x46 0x20 0xe0 0x96 # CHECK: rsqrt.d $f2, $f28 +0x46 0x00 0x41 0x16 # CHECK: rsqrt.s $f4, $f8 0x46 0xda 0x71 0x01 # CHECK: sub.ps $f4, $f14, $f26 0x41 0xcd 0x00 0x00 # CHECK: wrpgpr zero, t5 diff --git a/llvm/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6-el.txt b/llvm/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6-el.txt index 15821640ff3..cda52962483 100644 --- a/llvm/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6-el.txt +++ b/llvm/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6-el.txt @@ -156,12 +156,8 @@ 0x99 0x10 0x64 0x00 # CHECK: mulu $2, $3, $4 0x04 0x00 0x42 0x34 # CHECK: ori $2, $2, 4 0x35 0x04 0xa1 0x7c # CHECK: pref 1, 8($5) -0x95 0x34 0x20 0x46 # CHECK: recip.d $f18, $f6 -0xd5 0xf0 0x00 0x46 # CHECK: recip.s $f3, $f30 0x9a 0x20 0x20 0x46 # CHECK: rint.d $f2, $f4 0x9a 0x20 0x00 0x46 # CHECK: rint.s $f2, $f4 -0x96 0xe0 0x20 0x46 # CHECK: rsqrt.d $f2, $f28 -0x16 0x41 0x00 0x46 # CHECK: rsqrt.s $f4, $f8 0x26 0xec 0x6f 0x7e # CHECK: sc $15, -40($19) 0xa7 0xe6 0xaf 0x7f # CHECK: scd $15, -51($sp) 0x0e 0x00 0x00 0x00 # CHECK: sdbbp diff --git a/llvm/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6.txt b/llvm/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6.txt index 066c3d4a273..7be3fa71b1e 100644 --- a/llvm/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6.txt +++ b/llvm/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6.txt @@ -153,10 +153,6 @@ 0x46 0xa4 0x18 0x8d # CHECK: cmp.sult.d $f2, $f3, $f4 0x46 0xa4 0x18 0x8e # CHECK: cmp.sle.d $f2, $f3, $f4 0x46 0xa4 0x18 0x8f # CHECK: cmp.sule.d $f2, $f3, $f4 -0x46 0x20 0x34 0x95 # CHECK: recip.d $f18, $f6 -0x46 0x00 0xf0 0xd5 # CHECK: recip.s $f3, $f30 -0x46 0x20 0xe0 0x96 # CHECK: rsqrt.d $f2, $f28 -0x46 0x00 0x41 0x16 # CHECK: rsqrt.s $f4, $f8 0x42 0x00 0x00 0x58 # CHECK: eretnc # FIXME: The encode/decode functions are not inverses of each other. # The immediate should be 8 but the disassembler currently emits 12 diff --git a/llvm/test/MC/Mips/macro-li-bad.s b/llvm/test/MC/Mips/macro-li-bad.s index 29eedce713a..8fe622066e9 100644 --- a/llvm/test/MC/Mips/macro-li-bad.s +++ b/llvm/test/MC/Mips/macro-li-bad.s @@ -7,5 +7,5 @@ .text li $5, 0x100000000 - # 32-BIT: :[[@LINE-1]]:10: error: expected 32-bit immediate - # 64-BIT: :[[@LINE-2]]:10: error: expected 32-bit immediate + # 32-BIT: :[[@LINE-1]]:3: error: instruction requires a 32-bit immediate + # 64-BIT: :[[@LINE-2]]:3: error: instruction requires a 32-bit immediate diff --git a/llvm/test/MC/Mips/macro-li.s b/llvm/test/MC/Mips/macro-li.s index 6cdc11d70d2..88e013a854e 100644 --- a/llvm/test/MC/Mips/macro-li.s +++ b/llvm/test/MC/Mips/macro-li.s @@ -65,11 +65,3 @@ li $5, 0xc0008000 # CHECK: lui $5, 49152 # encoding: [0x3c,0x05,0xc0,0x00 # CHECK: ori $5, $5, 32768 # encoding: [0x34,0xa5,0x80,0x00] li $5, 0x80008000 # CHECK: lui $5, 32768 # encoding: [0x3c,0x05,0x80,0x00] # CHECK: ori $5, $5, 32768 # encoding: [0x34,0xa5,0x80,0x00] -li $4, ~0xffffffff # CHECK; addiu $4, $zero, 0 # encoding: [0x24,0x04,0x00,0x00] -li $4, ~0x80000001 # CHECK: lui $4, 32767 # encoding: [0x3c,0x04,0x7f,0xff] - # CHECK: ori $4, $4, 65534 # encoding: [0x34,0x84,0xff,0xfe] -li $4, ~0x80000000 # CHECK: lui $4, 32767 # encoding: [0x3c,0x04,0x7f,0xff] - # CHECK: ori $4, $4, 65535 # encoding: [0x34,0x84,0xff,0xff] -li $4, ~0x7fffffff # CHECK: lui $4, 32768 # encoding: [0x3c,0x04,0x80,0x00] -li $4, ~0x00000001 # CHECK: addiu $4, $zero, -2 # encoding: [0x24,0x04,0xff,0xfe] -li $4, ~0x00000000 # CHECK: addiu $4, $zero, -1 # encoding: [0x24,0x04,0xff,0xff] diff --git a/llvm/test/MC/Mips/micromips/valid.s b/llvm/test/MC/Mips/micromips/valid.s index 2178faee6ce..c6e83c122ae 100644 --- a/llvm/test/MC/Mips/micromips/valid.s +++ b/llvm/test/MC/Mips/micromips/valid.s @@ -203,7 +203,3 @@ cfc1 $1, $2 # CHECK: cfc1 $1, $2 # encoding: [0x54,0x cfc2 $3, $4 # CHECK: cfc2 $3, $4 # encoding: [0x00,0x64,0xcd,0x3c] ctc1 $5, $6 # CHECK: ctc1 $5, $6 # encoding: [0x54,0xa6,0x18,0x3b] ctc2 $7, $8 # CHECK: ctc2 $7, $8 # encoding: [0x00,0xe8,0xdd,0x3c] -recip.s $f2, $f4 # CHECK: recip.s $f2, $f4 # encoding: [0x54,0x44,0x12,0x3b] -recip.d $f2, $f4 # CHECK: recip.d $f2, $f4 # encoding: [0x54,0x44,0x52,0x3b] -rsqrt.s $f3, $f5 # CHECK: rsqrt.s $f3, $f5 # encoding: [0x54,0x65,0x02,0x3b] -rsqrt.d $f2, $f4 # CHECK: rsqrt.d $f2, $f4 # encoding: [0x54,0x44,0x42,0x3b] diff --git a/llvm/test/MC/Mips/mips32r2/valid-xfail.s b/llvm/test/MC/Mips/mips32r2/valid-xfail.s index 6fab97f7a62..5a61eb6cbfb 100644 --- a/llvm/test/MC/Mips/mips32r2/valid-xfail.s +++ b/llvm/test/MC/Mips/mips32r2/valid-xfail.s @@ -102,9 +102,13 @@ pul.ps $f9,$f30,$f26 puu.ps $f24,$f9,$f2 rdpgpr $s3,$9 + recip.d $f19,$f6 + recip.s $f3,$f30 rorv $13,$a3,$s5 round.l.d $f12,$f1 round.l.s $f25,$f5 + rsqrt.d $f3,$f28 + rsqrt.s $f4,$f8 sbe $s7,33($s1) sce $sp,189($10) she $24,105($v0) diff --git a/llvm/test/MC/Mips/mips32r2/valid.s b/llvm/test/MC/Mips/mips32r2/valid.s index 0ffddb0cdfe..6a5c6a0a513 100644 --- a/llvm/test/MC/Mips/mips32r2/valid.s +++ b/llvm/test/MC/Mips/mips32r2/valid.s @@ -167,15 +167,11 @@ a: # CHECK-NEXT: .set mips32r2 # CHECK-NEXT: rdhwr $sp, $11 # CHECK-NEXT: .set pop # encoding: [0x7c,0x1d,0x58,0x3b] - recip.d $f19,$f6 # CHECK: recip.d $f19, $f6 # encoding: [0x46,0x20,0x34,0xd5] - recip.s $f3,$f30 # CHECK: recip.s $f3, $f30 # encoding: [0x46,0x00,0xf0,0xd5] rotr $1,15 # CHECK: rotr $1, $1, 15 # encoding: [0x00,0x21,0x0b,0xc2] rotr $1,$14,15 # CHECK: rotr $1, $14, 15 # encoding: [0x00,0x2e,0x0b,0xc2] rotrv $1,$14,$15 # CHECK: rotrv $1, $14, $15 # encoding: [0x01,0xee,0x08,0x46] round.w.d $f6,$f4 round.w.s $f27,$f28 - rsqrt.s $f0,$f4 # CHECK: rsqrt.s $f0, $f4 # encoding: [0x46,0x00,0x20,0x16] - rsqrt.d $f2,$f6 # CHECK: rsqrt.d $f2, $f6 # encoding: [0x46,0x20,0x30,0x96] s.s $f2, 8($3) # CHECK: swc1 $f2, 8($3) # encoding: [0xe4,0x62,0x00,0x08] s.d $f2, 8($3) # CHECK: sdc1 $f2, 8($3) # encoding: [0xf4,0x62,0x00,0x08] sb $s6,-19857($14) diff --git a/llvm/test/MC/Mips/mips32r3/valid-xfail.s b/llvm/test/MC/Mips/mips32r3/valid-xfail.s index a442beb6198..defa388c4df 100644 --- a/llvm/test/MC/Mips/mips32r3/valid-xfail.s +++ b/llvm/test/MC/Mips/mips32r3/valid-xfail.s @@ -102,9 +102,13 @@ pul.ps $f9,$f30,$f26 puu.ps $f24,$f9,$f2 rdpgpr $s3,$9 + recip.d $f19,$f6 + recip.s $f3,$f30 rorv $13,$a3,$s5 round.l.d $f12,$f1 round.l.s $f25,$f5 + rsqrt.d $f3,$f28 + rsqrt.s $f4,$f8 sbe $s7,33($s1) sce $sp,189($10) she $24,105($v0) diff --git a/llvm/test/MC/Mips/mips32r3/valid.s b/llvm/test/MC/Mips/mips32r3/valid.s index a05df83ac2d..1505ccb2244 100644 --- a/llvm/test/MC/Mips/mips32r3/valid.s +++ b/llvm/test/MC/Mips/mips32r3/valid.s @@ -167,15 +167,11 @@ a: # CHECK-NEXT: .set mips32r2 # CHECK-NEXT: rdhwr $sp, $11 # CHECK-NEXT: .set pop # encoding: [0x7c,0x1d,0x58,0x3b] - recip.d $f19,$f6 # CHECK: recip.d $f19, $f6 # encoding: [0x46,0x20,0x34,0xd5] - recip.s $f3,$f30 # CHECK: recip.s $f3, $f30 # encoding: [0x46,0x00,0xf0,0xd5] rotr $1,15 # CHECK: rotr $1, $1, 15 # encoding: [0x00,0x21,0x0b,0xc2] rotr $1,$14,15 # CHECK: rotr $1, $14, 15 # encoding: [0x00,0x2e,0x0b,0xc2] rotrv $1,$14,$15 # CHECK: rotrv $1, $14, $15 # encoding: [0x01,0xee,0x08,0x46] round.w.d $f6,$f4 round.w.s $f27,$f28 - rsqrt.s $f0,$f4 # CHECK: rsqrt.s $f0, $f4 # encoding: [0x46,0x00,0x20,0x16] - rsqrt.d $f2,$f6 # CHECK: rsqrt.d $f2, $f6 # encoding: [0x46,0x20,0x30,0x96] s.s $f2, 8($3) # CHECK: swc1 $f2, 8($3) # encoding: [0xe4,0x62,0x00,0x08] s.d $f2, 8($3) # CHECK: sdc1 $f2, 8($3) # encoding: [0xf4,0x62,0x00,0x08] sb $s6,-19857($14) diff --git a/llvm/test/MC/Mips/mips32r5/valid-xfail.s b/llvm/test/MC/Mips/mips32r5/valid-xfail.s index 33ea7c46358..c1bf7a4b3a2 100644 --- a/llvm/test/MC/Mips/mips32r5/valid-xfail.s +++ b/llvm/test/MC/Mips/mips32r5/valid-xfail.s @@ -102,9 +102,13 @@ pul.ps $f9,$f30,$f26 puu.ps $f24,$f9,$f2 rdpgpr $s3,$9 + recip.d $f19,$f6 + recip.s $f3,$f30 rorv $13,$a3,$s5 round.l.d $f12,$f1 round.l.s $f25,$f5 + rsqrt.d $f3,$f28 + rsqrt.s $f4,$f8 sbe $s7,33($s1) sce $sp,189($10) she $24,105($v0) diff --git a/llvm/test/MC/Mips/mips32r5/valid.s b/llvm/test/MC/Mips/mips32r5/valid.s index 3100dd401d7..b3dd775c538 100644 --- a/llvm/test/MC/Mips/mips32r5/valid.s +++ b/llvm/test/MC/Mips/mips32r5/valid.s @@ -168,15 +168,11 @@ a: # CHECK-NEXT: .set mips32r2 # CHECK-NEXT: rdhwr $sp, $11 # CHECK-NEXT: .set pop # encoding: [0x7c,0x1d,0x58,0x3b] - recip.d $f19,$f6 # CHECK: recip.d $f19, $f6 # encoding: [0x46,0x20,0x34,0xd5] - recip.s $f3,$f30 # CHECK: recip.s $f3, $f30 # encoding: [0x46,0x00,0xf0,0xd5] rotr $1,15 # CHECK: rotr $1, $1, 15 # encoding: [0x00,0x21,0x0b,0xc2] rotr $1,$14,15 # CHECK: rotr $1, $14, 15 # encoding: [0x00,0x2e,0x0b,0xc2] rotrv $1,$14,$15 # CHECK: rotrv $1, $14, $15 # encoding: [0x01,0xee,0x08,0x46] round.w.d $f6,$f4 round.w.s $f27,$f28 - rsqrt.s $f0,$f4 # CHECK: rsqrt.s $f0, $f4 # encoding: [0x46,0x00,0x20,0x16] - rsqrt.d $f2,$f6 # CHECK: rsqrt.d $f2, $f6 # encoding: [0x46,0x20,0x30,0x96] s.s $f2, 8($3) # CHECK: swc1 $f2, 8($3) # encoding: [0xe4,0x62,0x00,0x08] s.d $f2, 8($3) # CHECK: sdc1 $f2, 8($3) # encoding: [0xf4,0x62,0x00,0x08] sb $s6,-19857($14) diff --git a/llvm/test/MC/Mips/mips32r6/valid.s b/llvm/test/MC/Mips/mips32r6/valid.s index bb4c7c577f1..cd90fcd279b 100644 --- a/llvm/test/MC/Mips/mips32r6/valid.s +++ b/llvm/test/MC/Mips/mips32r6/valid.s @@ -139,8 +139,6 @@ a: # CHECK-NEXT: .set mips32r2 # CHECK-NEXT: rdhwr $sp, $11 # CHECK-NEXT: .set pop # encoding: [0x7c,0x1d,0x58,0x3b] - recip.d $f19,$f6 # CHECK: recip.d $f19, $f6 # encoding: [0x46,0x20,0x34,0xd5] - recip.s $f3,$f30 # CHECK: recip.s $f3, $f30 # encoding: [0x46,0x00,0xf0,0xd5] s.s $f2, 8($3) # CHECK: swc1 $f2, 8($3) # encoding: [0xe4,0x62,0x00,0x08] s.d $f2, 8($3) # CHECK: sdc1 $f2, 8($3) # encoding: [0xf4,0x62,0x00,0x08] sel.d $f0,$f1,$f2 # CHECK: sel.d $f0, $f1, $f2 # encoding: [0x46,0x22,0x08,0x10] @@ -187,8 +185,6 @@ a: sc $15,-40($s3) # CHECK: sc $15, -40($19) # encoding: [0x7e,0x6f,0xec,0x26] clo $11,$a1 # CHECK: clo $11, $5 # encoding: [0x00,0xa0,0x58,0x51] clz $sp,$gp # CHECK: clz $sp, $gp # encoding: [0x03,0x80,0xe8,0x50] - rsqrt.s $f0,$f4 # CHECK: rsqrt.s $f0, $f4 # encoding: [0x46,0x00,0x20,0x16] - rsqrt.d $f2,$f6 # CHECK: rsqrt.d $f2, $f6 # encoding: [0x46,0x20,0x30,0x96] sgt $4, $5 # CHECK: slt $4, $5, $4 # encoding: [0x00,0xa4,0x20,0x2a] sgt $4, $5, $6 # CHECK: slt $4, $6, $5 # encoding: [0x00,0xc5,0x20,0x2a] sgtu $4, $5 # CHECK: sltu $4, $5, $4 # encoding: [0x00,0xa4,0x20,0x2b] diff --git a/llvm/test/MC/Mips/mips4/valid-xfail.s b/llvm/test/MC/Mips/mips4/valid-xfail.s index 21129bb9dbc..9c647d15115 100644 --- a/llvm/test/MC/Mips/mips4/valid-xfail.s +++ b/llvm/test/MC/Mips/mips4/valid-xfail.s @@ -35,3 +35,7 @@ c.ult.s $fcc7,$f24,$f10 c.un.d $fcc6,$f23,$f24 c.un.s $fcc1,$f30,$f4 + recip.d $f19,$f6 + recip.s $f3,$f30 + rsqrt.d $f3,$f28 + rsqrt.s $f4,$f8 diff --git a/llvm/test/MC/Mips/mips4/valid.s b/llvm/test/MC/Mips/mips4/valid.s index e9a7ae90dd5..18b02234a71 100644 --- a/llvm/test/MC/Mips/mips4/valid.s +++ b/llvm/test/MC/Mips/mips4/valid.s @@ -196,14 +196,10 @@ a: or $12,$s0,$sp or $2, 4 # CHECK: ori $2, $2, 4 # encoding: [0x34,0x42,0x00,0x04] pref 1, 8($5) # CHECK: pref 1, 8($5) # encoding: [0xcc,0xa1,0x00,0x08] - recip.d $f19,$f6 # CHECK: recip.d $f19, $f6 # encoding: [0x46,0x20,0x34,0xd5] - recip.s $f3,$f30 # CHECK: recip.s $f3, $f30 # encoding: [0x46,0x00,0xf0,0xd5] round.l.d $f12,$f1 round.l.s $f25,$f5 round.w.d $f6,$f4 round.w.s $f27,$f28 - rsqrt.s $f0,$f4 # CHECK: rsqrt.s $f0, $f4 # encoding: [0x46,0x00,0x20,0x16] - rsqrt.d $f2,$f6 # CHECK: rsqrt.d $f2, $f6 # encoding: [0x46,0x20,0x30,0x96] s.s $f2, 8($3) # CHECK: swc1 $f2, 8($3) # encoding: [0xe4,0x62,0x00,0x08] s.d $f2, 8($3) # CHECK: sdc1 $f2, 8($3) # encoding: [0xf4,0x62,0x00,0x08] sb $s6,-19857($14) diff --git a/llvm/test/MC/Mips/mips5/valid-xfail.s b/llvm/test/MC/Mips/mips5/valid-xfail.s index 8517315780e..d76118950fc 100644 --- a/llvm/test/MC/Mips/mips5/valid-xfail.s +++ b/llvm/test/MC/Mips/mips5/valid-xfail.s @@ -72,4 +72,8 @@ plu.ps $f1,$f26,$f29 pul.ps $f9,$f30,$f26 puu.ps $f24,$f9,$f2 + recip.d $f19,$f6 + recip.s $f3,$f30 + rsqrt.d $f3,$f28 + rsqrt.s $f4,$f8 sub.ps $f5,$f14,$f26 diff --git a/llvm/test/MC/Mips/mips5/valid.s b/llvm/test/MC/Mips/mips5/valid.s index 62b1b48c767..0661a4d4f80 100644 --- a/llvm/test/MC/Mips/mips5/valid.s +++ b/llvm/test/MC/Mips/mips5/valid.s @@ -197,14 +197,10 @@ a: or $12,$s0,$sp or $2, 4 # CHECK: ori $2, $2, 4 # encoding: [0x34,0x42,0x00,0x04] pref 1, 8($5) # CHECK: pref 1, 8($5) # encoding: [0xcc,0xa1,0x00,0x08] - recip.d $f19,$f6 # CHECK: recip.d $f19, $f6 # encoding: [0x46,0x20,0x34,0xd5] - recip.s $f3,$f30 # CHECK: recip.s $f3, $f30 # encoding: [0x46,0x00,0xf0,0xd5] round.l.d $f12,$f1 round.l.s $f25,$f5 round.w.d $f6,$f4 round.w.s $f27,$f28 - rsqrt.s $f0,$f4 # CHECK: rsqrt.s $f0, $f4 # encoding: [0x46,0x00,0x20,0x16] - rsqrt.d $f2,$f6 # CHECK: rsqrt.d $f2, $f6 # encoding: [0x46,0x20,0x30,0x96] s.s $f2, 8($3) # CHECK: swc1 $f2, 8($3) # encoding: [0xe4,0x62,0x00,0x08] s.d $f2, 8($3) # CHECK: sdc1 $f2, 8($3) # encoding: [0xf4,0x62,0x00,0x08] sb $s6,-19857($14) diff --git a/llvm/test/MC/Mips/mips64/valid-xfail.s b/llvm/test/MC/Mips/mips64/valid-xfail.s index c7513bf5d7e..7d1eb9264e2 100644 --- a/llvm/test/MC/Mips/mips64/valid-xfail.s +++ b/llvm/test/MC/Mips/mips64/valid-xfail.s @@ -79,4 +79,8 @@ plu.ps $f1,$f26,$f29 pul.ps $f9,$f30,$f26 puu.ps $f24,$f9,$f2 + recip.d $f19,$f6 + recip.s $f3,$f30 + rsqrt.d $f3,$f28 + rsqrt.s $f4,$f8 sub.ps $f5,$f14,$f26 diff --git a/llvm/test/MC/Mips/mips64/valid.s b/llvm/test/MC/Mips/mips64/valid.s index 6235b89e182..dbcddda5556 100644 --- a/llvm/test/MC/Mips/mips64/valid.s +++ b/llvm/test/MC/Mips/mips64/valid.s @@ -213,14 +213,10 @@ a: or $12,$s0,$sp or $2, 4 # CHECK: ori $2, $2, 4 # encoding: [0x34,0x42,0x00,0x04] pref 1, 8($5) # CHECK: pref 1, 8($5) # encoding: [0xcc,0xa1,0x00,0x08] - recip.d $f19,$f6 # CHECK: recip.d $f19, $f6 # encoding: [0x46,0x20,0x34,0xd5] - recip.s $f3,$f30 # CHECK: recip.s $f3, $f30 # encoding: [0x46,0x00,0xf0,0xd5] round.l.d $f12,$f1 round.l.s $f25,$f5 round.w.d $f6,$f4 round.w.s $f27,$f28 - rsqrt.s $f0,$f4 # CHECK: rsqrt.s $f0, $f4 # encoding: [0x46,0x00,0x20,0x16] - rsqrt.d $f2,$f6 # CHECK: rsqrt.d $f2, $f6 # encoding: [0x46,0x20,0x30,0x96] s.s $f2, 8($3) # CHECK: swc1 $f2, 8($3) # encoding: [0xe4,0x62,0x00,0x08] s.d $f2, 8($3) # CHECK: sdc1 $f2, 8($3) # encoding: [0xf4,0x62,0x00,0x08] sb $s6,-19857($14) diff --git a/llvm/test/MC/Mips/mips64r2/valid-xfail.s b/llvm/test/MC/Mips/mips64r2/valid-xfail.s index d55d1fb9a19..bf17b35c446 100644 --- a/llvm/test/MC/Mips/mips64r2/valid-xfail.s +++ b/llvm/test/MC/Mips/mips64r2/valid-xfail.s @@ -101,7 +101,11 @@ pul.ps $f9,$f30,$f26 puu.ps $f24,$f9,$f2 rdpgpr $s3,$9 + recip.d $f19,$f6 + recip.s $f3,$f30 rorv $13,$a3,$s5 + rsqrt.d $f3,$f28 + rsqrt.s $f4,$f8 sbe $s7,33($s1) sce $sp,189($10) she $24,105($v0) diff --git a/llvm/test/MC/Mips/mips64r2/valid.s b/llvm/test/MC/Mips/mips64r2/valid.s index 43f6b73b68e..f5a7ca5a894 100644 --- a/llvm/test/MC/Mips/mips64r2/valid.s +++ b/llvm/test/MC/Mips/mips64r2/valid.s @@ -234,8 +234,6 @@ a: # CHECK-NEXT: .set mips32r2 # CHECK-NEXT: rdhwr $sp, $11 # CHECK-NEXT: .set pop # encoding: [0x7c,0x1d,0x58,0x3b] - recip.d $f19,$f6 # CHECK: recip.d $f19, $f6 # encoding: [0x46,0x20,0x34,0xd5] - recip.s $f3,$f30 # CHECK: recip.s $f3, $f30 # encoding: [0x46,0x00,0xf0,0xd5] rotr $1,15 # CHECK: rotr $1, $1, 15 # encoding: [0x00,0x21,0x0b,0xc2] rotr $1,$14,15 # CHECK: rotr $1, $14, 15 # encoding: [0x00,0x2e,0x0b,0xc2] rotrv $1,$14,$15 # CHECK: rotrv $1, $14, $15 # encoding: [0x01,0xee,0x08,0x46] @@ -243,8 +241,6 @@ a: round.l.s $f25,$f5 round.w.d $f6,$f4 round.w.s $f27,$f28 - rsqrt.s $f0,$f4 # CHECK: rsqrt.s $f0, $f4 # encoding: [0x46,0x00,0x20,0x16] - rsqrt.d $f2,$f6 # CHECK: rsqrt.d $f2, $f6 # encoding: [0x46,0x20,0x30,0x96] s.s $f2, 8($3) # CHECK: swc1 $f2, 8($3) # encoding: [0xe4,0x62,0x00,0x08] s.d $f2, 8($3) # CHECK: sdc1 $f2, 8($3) # encoding: [0xf4,0x62,0x00,0x08] sb $s6,-19857($14) diff --git a/llvm/test/MC/Mips/mips64r3/valid-xfail.s b/llvm/test/MC/Mips/mips64r3/valid-xfail.s index 2f38e73e442..7e94200dfd6 100644 --- a/llvm/test/MC/Mips/mips64r3/valid-xfail.s +++ b/llvm/test/MC/Mips/mips64r3/valid-xfail.s @@ -104,7 +104,11 @@ pul.ps $f9,$f30,$f26 puu.ps $f24,$f9,$f2 rdpgpr $s3,$9 + recip.d $f19,$f6 + recip.s $f3,$f30 rorv $13,$a3,$s5 + rsqrt.d $f3,$f28 + rsqrt.s $f4,$f8 sbe $s7,33($s1) sce $sp,189($10) she $24,105($v0) diff --git a/llvm/test/MC/Mips/mips64r3/valid.s b/llvm/test/MC/Mips/mips64r3/valid.s index e8a65abd976..0101b3a7fe2 100644 --- a/llvm/test/MC/Mips/mips64r3/valid.s +++ b/llvm/test/MC/Mips/mips64r3/valid.s @@ -234,8 +234,6 @@ a: # CHECK-NEXT: .set mips32r2 # CHECK-NEXT: rdhwr $sp, $11 # CHECK-NEXT: .set pop # encoding: [0x7c,0x1d,0x58,0x3b] - recip.d $f19,$f6 # CHECK: recip.d $f19, $f6 # encoding: [0x46,0x20,0x34,0xd5] - recip.s $f3,$f30 # CHECK: recip.s $f3, $f30 # encoding: [0x46,0x00,0xf0,0xd5] rotr $1,15 # CHECK: rotr $1, $1, 15 # encoding: [0x00,0x21,0x0b,0xc2] rotr $1,$14,15 # CHECK: rotr $1, $14, 15 # encoding: [0x00,0x2e,0x0b,0xc2] rotrv $1,$14,$15 # CHECK: rotrv $1, $14, $15 # encoding: [0x01,0xee,0x08,0x46] @@ -243,8 +241,6 @@ a: round.l.s $f25,$f5 round.w.d $f6,$f4 round.w.s $f27,$f28 - rsqrt.s $f0,$f4 # CHECK: rsqrt.s $f0, $f4 # encoding: [0x46,0x00,0x20,0x16] - rsqrt.d $f2,$f6 # CHECK: rsqrt.d $f2, $f6 # encoding: [0x46,0x20,0x30,0x96] s.s $f2, 8($3) # CHECK: swc1 $f2, 8($3) # encoding: [0xe4,0x62,0x00,0x08] s.d $f2, 8($3) # CHECK: sdc1 $f2, 8($3) # encoding: [0xf4,0x62,0x00,0x08] sb $s6,-19857($14) diff --git a/llvm/test/MC/Mips/mips64r5/valid-xfail.s b/llvm/test/MC/Mips/mips64r5/valid-xfail.s index 44ff4ee9fc0..b5ecdcbfb72 100644 --- a/llvm/test/MC/Mips/mips64r5/valid-xfail.s +++ b/llvm/test/MC/Mips/mips64r5/valid-xfail.s @@ -104,7 +104,11 @@ pul.ps $f9,$f30,$f26 puu.ps $f24,$f9,$f2 rdpgpr $s3,$9 + recip.d $f19,$f6 + recip.s $f3,$f30 rorv $13,$a3,$s5 + rsqrt.d $f3,$f28 + rsqrt.s $f4,$f8 sbe $s7,33($s1) sce $sp,189($10) she $24,105($v0) diff --git a/llvm/test/MC/Mips/mips64r5/valid.s b/llvm/test/MC/Mips/mips64r5/valid.s index 392fe3f6566..a11cee7e588 100644 --- a/llvm/test/MC/Mips/mips64r5/valid.s +++ b/llvm/test/MC/Mips/mips64r5/valid.s @@ -235,8 +235,6 @@ a: # CHECK-NEXT: .set mips32r2 # CHECK-NEXT: rdhwr $sp, $11 # CHECK-NEXT: .set pop # encoding: [0x7c,0x1d,0x58,0x3b] - recip.d $f19,$f6 # CHECK: recip.d $f19, $f6 # encoding: [0x46,0x20,0x34,0xd5] - recip.s $f3,$f30 # CHECK: recip.s $f3, $f30 # encoding: [0x46,0x00,0xf0,0xd5] rotr $1,15 # CHECK: rotr $1, $1, 15 # encoding: [0x00,0x21,0x0b,0xc2] rotr $1,$14,15 # CHECK: rotr $1, $14, 15 # encoding: [0x00,0x2e,0x0b,0xc2] rotrv $1,$14,$15 # CHECK: rotrv $1, $14, $15 # encoding: [0x01,0xee,0x08,0x46] @@ -244,8 +242,6 @@ a: round.l.s $f25,$f5 round.w.d $f6,$f4 round.w.s $f27,$f28 - rsqrt.s $f0,$f4 # CHECK: rsqrt.s $f0, $f4 # encoding: [0x46,0x00,0x20,0x16] - rsqrt.d $f2,$f6 # CHECK: rsqrt.d $f2, $f6 # encoding: [0x46,0x20,0x30,0x96] s.s $f2, 8($3) # CHECK: swc1 $f2, 8($3) # encoding: [0xe4,0x62,0x00,0x08] s.d $f2, 8($3) # CHECK: sdc1 $f2, 8($3) # encoding: [0xf4,0x62,0x00,0x08] sb $s6,-19857($14) diff --git a/llvm/test/MC/Mips/mips64r6/valid.s b/llvm/test/MC/Mips/mips64r6/valid.s index 7ad4dc3c3d2..b92fd09f310 100644 --- a/llvm/test/MC/Mips/mips64r6/valid.s +++ b/llvm/test/MC/Mips/mips64r6/valid.s @@ -194,12 +194,8 @@ a: # CHECK-NEXT: .set mips32r2 # CHECK-NEXT: rdhwr $sp, $11 # CHECK-NEXT: .set pop # encoding: [0x7c,0x1d,0x58,0x3b] - recip.d $f19,$f6 # CHECK: recip.d $f19, $f6 # encoding: [0x46,0x20,0x34,0xd5] - recip.s $f3,$f30 # CHECK: recip.s $f3, $f30 # encoding: [0x46,0x00,0xf0,0xd5] rint.d $f2, $f4 # CHECK: rint.d $f2, $f4 # encoding: [0x46,0x20,0x20,0x9a] rint.s $f2, $f4 # CHECK: rint.s $f2, $f4 # encoding: [0x46,0x00,0x20,0x9a] - rsqrt.s $f0,$f4 # CHECK: rsqrt.s $f0, $f4 # encoding: [0x46,0x00,0x20,0x16] - rsqrt.d $f2,$f6 # CHECK: rsqrt.d $f2, $f6 # encoding: [0x46,0x20,0x30,0x96] s.s $f2, 8($3) # CHECK: swc1 $f2, 8($3) # encoding: [0xe4,0x62,0x00,0x08] s.d $f2, 8($3) # CHECK: sdc1 $f2, 8($3) # encoding: [0xf4,0x62,0x00,0x08] sc $15,-40($s3) # CHECK: sc $15, -40($19) # encoding: [0x7e,0x6f,0xec,0x26] |
