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| author | Daniel Cederman <cederman@gaisler.com> | 2018-12-13 15:29:12 +0000 |
|---|---|---|
| committer | Daniel Cederman <cederman@gaisler.com> | 2018-12-13 15:29:12 +0000 |
| commit | 77611426e18e5f3cd17f0eb9acc28fd521cc5326 (patch) | |
| tree | 76273f1456e762df09eb7fca1bfe962e47f41c94 /llvm/test/MC | |
| parent | ba91ff4a8634172416c936712d0705b7eeb59bc8 (diff) | |
| download | bcm5719-llvm-77611426e18e5f3cd17f0eb9acc28fd521cc5326.tar.gz bcm5719-llvm-77611426e18e5f3cd17f0eb9acc28fd521cc5326.zip | |
[Sparc] Add membar assembler tags
Summary: The Sparc V9 membar instruction can enforce different types of
memory orderings depending on the value in its immediate field. In the
architectural manual the type is selected by combining different assembler
tags into a mask. This patch adds support for these tags.
Reviewers: jyknight, venkatra, brad
Reviewed By: jyknight
Subscribers: fedor.sergeev, jrtc27, jfb, llvm-commits
Differential Revision: https://reviews.llvm.org/D53491
llvm-svn: 349048
Diffstat (limited to 'llvm/test/MC')
| -rw-r--r-- | llvm/test/MC/Disassembler/Sparc/sparc-v9.txt | 17 | ||||
| -rw-r--r-- | llvm/test/MC/Sparc/sparc-asm-errors.s | 12 | ||||
| -rw-r--r-- | llvm/test/MC/Sparc/sparcv9-atomic-instructions.s | 11 |
3 files changed, 36 insertions, 4 deletions
diff --git a/llvm/test/MC/Disassembler/Sparc/sparc-v9.txt b/llvm/test/MC/Disassembler/Sparc/sparc-v9.txt index 0a81b8df4cd..8f68513387e 100644 --- a/llvm/test/MC/Disassembler/Sparc/sparc-v9.txt +++ b/llvm/test/MC/Disassembler/Sparc/sparc-v9.txt @@ -115,4 +115,19 @@ 0x9f 0xd0 0x30 0x52 # CHECK: tvs %xcc, %g1 + %i2 -0x8f 0xd0 0x50 0x1a
\ No newline at end of file +0x8f 0xd0 0x50 0x1a + +# CHECK: membar 5000 +0x81 0x43 0xf3 0x88 + +# CHECK: membar #LoadLoad | #StoreLoad | #LoadStore | #StoreStore +0x81 0x43 0xe0 0x0f + +# CHECK: membar #LoadLoad +0x81 0x43 0xe0 0x01 + +# CHECK: membar #LoadLoad | #StoreStore +0x81 0x43 0xe0 0x09 + +# CHECK: membar #LoadLoad | #StoreLoad | #LoadStore | #StoreStore | #Lookaside | #MemIssue | #Sync +0x81 0x43 0xe0 0x7f diff --git a/llvm/test/MC/Sparc/sparc-asm-errors.s b/llvm/test/MC/Sparc/sparc-asm-errors.s index 6a4128f683f..4af723ed788 100644 --- a/llvm/test/MC/Sparc/sparc-asm-errors.s +++ b/llvm/test/MC/Sparc/sparc-asm-errors.s @@ -1,8 +1,16 @@ -! RUN: not llvm-mc %s -arch=sparc -show-encoding 2>&1 | FileCheck %s -! RUN: not llvm-mc %s -arch=sparcv9 -show-encoding 2>&1 | FileCheck %s +! RUN: not llvm-mc %s -arch=sparc -show-encoding 2>&1 | FileCheck %s --check-prefix=CHECK --check-prefix=V8 +! RUN: not llvm-mc %s -arch=sparcv9 -show-encoding 2>&1 | FileCheck %s --check-prefix=CHECK --check-prefix=V9 ! Test the lower and upper bounds of 'set' ! CHECK: argument must be between set -2147483649, %o1 ! CHECK: argument must be between set 4294967296, %o1 + + ! V8: unexpected token + ! V9: unknown membar tag + membar #BadTag + + ! V8: instruction requires a CPU feature not currently enabled + ! V9: invalid membar mask number + membar -127 diff --git a/llvm/test/MC/Sparc/sparcv9-atomic-instructions.s b/llvm/test/MC/Sparc/sparcv9-atomic-instructions.s index 40619a75548..449450f70f6 100644 --- a/llvm/test/MC/Sparc/sparcv9-atomic-instructions.s +++ b/llvm/test/MC/Sparc/sparcv9-atomic-instructions.s @@ -1,8 +1,17 @@ ! RUN: llvm-mc %s -arch=sparcv9 -show-encoding | FileCheck %s - ! CHECK: membar 15 ! encoding: [0x81,0x43,0xe0,0x0f] + ! CHECK: membar #LoadLoad | #StoreLoad | #LoadStore | #StoreStore ! encoding: [0x81,0x43,0xe0,0x0f] membar 15 + ! CHECK: membar #LoadLoad ! encoding: [0x81,0x43,0xe0,0x01] + membar #LoadLoad + + ! CHECK: membar #LoadLoad | #StoreStore ! encoding: [0x81,0x43,0xe0,0x09] + membar #LoadLoad | #StoreStore + + ! CHECK: membar #LoadLoad | #StoreLoad | #LoadStore | #StoreStore | #Lookaside | #MemIssue | #Sync ! encoding: [0x81,0x43,0xe0,0x7f] + membar #LoadLoad | #StoreLoad | #LoadStore | #StoreStore | #Lookaside | #MemIssue | #Sync + ! CHECK: cas [%i0], %l6, %o2 ! encoding: [0xd5,0xe6,0x10,0x16] cas [%i0], %l6, %o2 |
