Add retw and lretw instructions. Also, fix Intel syntax parsing for all

ret instructions.

llvm-svn: 154468

4 files changed, 31 insertions, 0 deletions

diff --git a/llvm/test/MC/Disassembler/X86/intel-syntax.txt b/llvm/test/MC/Disassembler/X86/intel-syntax.txt
index e2883c767f1..3391e45cc00 100644
--- a/llvm/test/MC/Disassembler/X86/intel-syntax.txt
+++ b/llvm/test/MC/Disassembler/X86/intel-syntax.txt
@@ -99,3 +99,9 @@
 # CHECK: iretq
 0x48 0xcf
 
+# CHECK: ret
+0x66 0xc3
+
+# CHECK: retf
+0x66 0xcb
+
diff --git a/llvm/test/MC/X86/intel-syntax-encoding.s b/llvm/test/MC/X86/intel-syntax-encoding.s
index 8891126475b..03b05511649 100644
--- a/llvm/test/MC/X86/intel-syntax-encoding.s
+++ b/llvm/test/MC/X86/intel-syntax-encoding.s
@@ -42,3 +42,16 @@ LBB0_3:
 
 // CHECK: encoding: [0x0f,0xc2,0xd1,0x01]
 	cmpltps XMM2, XMM1
+
+// CHECK: encoding: [0xc3]
+    ret
+
+// CHECK: encoding: [0xcb]
+    retf
+
+// CHECK: encoding: [0xc2,0x08,0x00]
+    ret 8
+
+// CHECK: encoding: [0xca,0x08,0x00]
+    retf 8
+
diff --git a/llvm/test/MC/X86/x86-32.s b/llvm/test/MC/X86/x86-32.s
index 8e11aec5c59..57a00378d31 100644
--- a/llvm/test/MC/X86/x86-32.s
+++ b/llvm/test/MC/X86/x86-32.s
@@ -990,3 +990,11 @@ xchgl %ecx, %eax
 // CHECK: xchgl %ecx, %eax
 // CHECK: encoding: [0x91]
 xchgl %eax, %ecx
+
+// CHECK: retw
+// CHECK: encoding: [0x66,0xc3]
+retw
+
+// CHECK: lretw
+// CHECK: encoding: [0x66,0xcb]
+lretw
diff --git a/llvm/test/MC/X86/x86-64.s b/llvm/test/MC/X86/x86-64.s
index f53b6726f4e..6a2d5bba6b7 100644
--- a/llvm/test/MC/X86/x86-64.s
+++ b/llvm/test/MC/X86/x86-64.s
@@ -50,6 +50,9 @@
 // CHECK: ret
         ret
         
+// CHECK: retw
+        retw
+        
 // FIXME: Check that this matches SUB32ri8
 // CHECK: subl $1, %eax
         subl $1, %eax
@@ -841,6 +844,7 @@ iretq
 lretq  // CHECK: lretq # encoding: [0x48,0xcb]
 lretl  // CHECK: lretl # encoding: [0xcb]
 lret   // CHECK: lretl # encoding: [0xcb]
+lretw  // CHECK: lretw # encoding: [0x66,0xcb]
 
 // rdar://8403907
 sysret