[mips] Correct predicates for loads, bit manipulation instructions and some pseudos

Additionally, correct the definition of the rdhwr instruction.

Reviewers: atanasyan, abeserminji, smaksimovic

Differential Revision: https://reviews.llvm.org/D48216

llvm-svn: 335162

8 files changed, 40 insertions, 0 deletions

diff --git a/llvm/test/MC/Mips/micromips/valid.s b/llvm/test/MC/Mips/micromips/valid.s
index 9d94426f8a5..a995c37b15c 100644
--- a/llvm/test/MC/Mips/micromips/valid.s
+++ b/llvm/test/MC/Mips/micromips/valid.s
@@ -131,6 +131,7 @@ ori $9, $6, 17767           # CHECK: ori $9, $6, 17767      # encoding: [0x51,0x
 xor $3, $3, $5              # CHECK: xor $3, $3, $5         # encoding: [0x00,0xa3,0x1b,0x10]
 xori $9, $6, 17767          # CHECK: xori $9, $6, 17767     # encoding: [0x71,0x26,0x45,0x67]
 nor $9, $6, $7              # CHECK: nor $9, $6, $7         # encoding: [0x00,0xe6,0x4a,0xd0]
+                            # CHECK-NEXT:                   # <MCInst #{{[0-9]+}} NOR_MM
 not $7, $8                  # CHECK: not $7, $8             # encoding: [0x00,0x08,0x3a,0xd0]
 not $7                      # CHECK: not $7, $7             # encoding: [0x00,0x07,0x3a,0xd0]
 mul $9, $6, $7              # CHECK: mul $9, $6, $7         # encoding: [0x00,0xe6,0x4a,0x10]
@@ -142,6 +143,12 @@ div $zero, $9, $7           # CHECK: div $zero, $9, $7      # encoding: [0x00,0x
 div.d $f0, $f2, $f4         # CHECK: div.d $f0, $f2, $f4    # encoding: [0x54,0x82,0x01,0xf0]
                             # CHECK-NEXT:                   # <MCInst #{{[0-9]+}} FDIV_D32_MM
 divu $zero, $9, $7          # CHECK: divu $zero, $9, $7     # encoding: [0x00,0xe9,0xbb,0x3c]
+rdhwr $5, $29, 2            # CHECK: rdhwr $5, $29, 2       # encoding: [0x00,0xbd,0x6b,0x3c]
+                            # CHECK-NEXT:                   # <MCInst #{{[0-9]+}} RDHWR_MM
+rdhwr $5, $29, 0            # CHECK: rdhwr $5, $29          # encoding: [0x00,0xbd,0x6b,0x3c]
+                            # CHECK-NEXT:                   # <MCInst #{{[0-9]+}} RDHWR_MM
+rdhwr $5, $29               # CHECK: rdhwr $5, $29          # encoding: [0x00,0xbd,0x6b,0x3c]
+                            # CHECK-NEXT:                   # <MCInst #{{[0-9]+}} RDHWR_MM
 sll $4, $3, 7               # CHECK: sll $4, $3, 7          # encoding: [0x00,0x83,0x38,0x00]
                             # CHECK-NEXT:                   # <MCInst #{{[0-9]+}} SLL_MM
 sllv $2, $3, $5             # CHECK: sllv $2, $3, $5        # encoding: [0x00,0x65,0x10,0x10]
@@ -157,15 +164,25 @@ srlv $2, $3, $5             # CHECK: srlv $2, $3, $5        # encoding: [0x00,0x
 rotr $9, $6, 7              # CHECK: rotr $9, $6, 7         # encoding: [0x01,0x26,0x38,0xc0]
 rotrv $9, $6, $7            # CHECK: rotrv $9, $6, $7       # encoding: [0x00,0xc7,0x48,0xd0]
 lb $5, 8($4)                # CHECK: lb $5, 8($4)           # encoding: [0x1c,0xa4,0x00,0x08]
+                            # CHECK-NEXT:                   # <MCInst #{{[0-9]+}} LB_MM
 lbu $6, 8($4)               # CHECK: lbu $6, 8($4)          # encoding: [0x14,0xc4,0x00,0x08]
+                            # CHECK-NEXT:                   # <MCInst #{{[0-9]+}} LBu_MM
 lh $2, 8($4)                # CHECK: lh $2, 8($4)           # encoding: [0x3c,0x44,0x00,0x08]
+                            # CHECK-NEXT:                   # <MCInst #{{[0-9]+}} LH_MM
 lhu $4, 8($2)               # CHECK: lhu $4, 8($2)          # encoding: [0x34,0x82,0x00,0x08]
+                            # CHECK-NEXT:                   # <MCInst #{{[0-9]+}} LHu_MM
 lw  $6, 4($5)               # CHECK: lw  $6, 4($5)          # encoding: [0xfc,0xc5,0x00,0x04]
+                            # CHECK-NEXT:                   # <MCInst #{{[0-9]+}} LW_MM
 lw $6, 123($sp)             # CHECK: lw $6, 123($sp)        # encoding: [0xfc,0xdd,0x00,0x7b]
+                            # CHECK-NEXT:                   # <MCInst #{{[0-9]+}} LW_MM
 sb $5, 8($4)                # CHECK: sb $5, 8($4)           # encoding: [0x18,0xa4,0x00,0x08]
+                            # CHECK-NEXT:                   # <MCInst #{{[0-9]+}} SB_MM
 sh  $2, 8($4)               # CHECK: sh  $2, 8($4)          # encoding: [0x38,0x44,0x00,0x08]
+                            # CHECK-NEXT:                   # <MCInst #{{[0-9]+}} SH_MM
 sw  $5, 4($6)               # CHECK: sw  $5, 4($6)          # encoding: [0xf8,0xa6,0x00,0x04]
+                            # CHECK-NEXT:                   # <MCInst #{{[0-9]+}} SW_MM
 sw $5, 123($sp)             # CHECK: sw $5, 123($sp)        # encoding: [0xf8,0xbd,0x00,0x7b]
+                            # CHECK-NEXT:                   # <MCInst #{{[0-9]+}} SW_MM
 lwu $2, 8($4)               # CHECK: lwu $2, 8($4)          # encoding: [0x60,0x44,0xe0,0x08]
 lwl $4, 16($5)              # CHECK: lwl $4, 16($5)         # encoding: [0x60,0x85,0x00,0x10]
 lwr $4, 16($5)              # CHECK: lwr $4, 16($5)         # encoding: [0x60,0x85,0x10,0x10]
diff --git a/llvm/test/MC/Mips/micromips32r6/valid.s b/llvm/test/MC/Mips/micromips32r6/valid.s
index b48e3559c9b..6b2aec9d5aa 100644
--- a/llvm/test/MC/Mips/micromips32r6/valid.s
+++ b/llvm/test/MC/Mips/micromips32r6/valid.s
@@ -82,7 +82,9 @@
   lapc $7, 1048572         # CHECK: lapc $7, 1048572    # encoding: [0x78,0xe3,0xff,0xff]
   lapc $7, -1048576        # CHECK: lapc $7, -1048576   # encoding: [0x78,0xe4,0x00,0x00]
   lh $2, 8($4)             # CHECK: lh $2, 8($4)        # encoding: [0x3c,0x44,0x00,0x08]
+                           # CHECK-NEXT:                # <MCInst #{{.*}} LH_MM
   lhu $4, 8($2)            # CHECK: lhu $4, 8($2)       # encoding: [0x34,0x82,0x00,0x08]
+                           # CHECK-NEXT:                # <MCInst #{{.*}} LHu_MM
   lsa $2, $3, $4, 3        # CHECK: lsa  $2, $3, $4, 3  # encoding: [0x00,0x43,0x24,0x0f]
   lwpc    $2,268           # CHECK: lwpc $2, 268        # encoding: [0x78,0x48,0x00,0x43]
   lwm $16, $17, $ra, 8($sp)   # CHECK: lwm16 $16, $17, $ra, 8($sp) # encoding: [0x45,0x22]
@@ -124,6 +126,7 @@
   muhu $3, $4, $5          # CHECK: muhu $3, $4, $5      # encoding: [0x00,0xa4,0x18,0xd8]
   nop                      # CHECK: nop                 # encoding: [0x00,0x00,0x00,0x00]
   nor $3, $4, $5           # CHECK: nor $3, $4, $5      # encoding: [0x00,0xa4,0x1a,0xd0]
+                           # CHECK-NEXT:                # <MCInst #{{.*}} NOR_MMR6
   or $3, $4, $5            # CHECK: or $3, $4, $5       # encoding: [0x00,0xa4,0x1a,0x90]
   ori $3, $4, 1234         # CHECK: ori $3, $4, 1234    # encoding: [0x50,0x64,0x04,0xd2]
   pref 1, 8($5)            # CHECK: pref 1, 8($5)       # encoding: [0x60,0x25,0x20,0x08]
@@ -143,6 +146,7 @@
   subu $3, $4, $5          # CHECK: subu $3, $4, $5     # encoding: [0x00,0xa4,0x19,0xd0]
   sw $4, 124($sp)          # CHECK: sw $4, 124($sp)     # encoding: [0xc8,0x9f]
   sw $4, 128($sp)          # CHECK: sw $4, 128($sp)     # encoding: [0xf8,0x9d,0x00,0x80]
+                           # CHECK-NEXT:                # <MCInst #{{[0-9]+}} SW_MMR6
   sw16 $4, 4($17)          # CHECK: sw16 $4, 4($17)     # encoding: [0xea,0x11]
   sw16 $0, 4($17)          # CHECK: sw16 $zero, 4($17)  # encoding: [0xe8,0x11]
   swm $16, $17, $ra, 8($sp)   # CHECK: swm16 $16, $17, $ra, 8($sp) # encoding: [0x45,0x2a]
@@ -151,8 +155,11 @@
   wsbh $3, $4              # CHECK: wsbh $3, $4         # encoding: [0x00,0x64,0x7b,0x3c]
   pause                    # CHECK: pause               # encoding: [0x00,0x00,0x28,0x00]
   rdhwr $5, $29, 2         # CHECK: rdhwr $5, $29, 2    # encoding: [0x00,0xbd,0x11,0xc0]
+                           # CHECK-NEXT:                # <MCInst #{{[0-9]+}} RDHWR_MMR6
   rdhwr $5, $29, 0         # CHECK: rdhwr $5, $29       # encoding: [0x00,0xbd,0x01,0xc0]
+                           # CHECK-NEXT:                # <MCInst #{{[0-9]+}} RDHWR_MMR6
   rdhwr $5, $29            # CHECK: rdhwr $5, $29       # encoding: [0x00,0xbd,0x01,0xc0]
+                           # CHECK-NEXT:                # <MCInst #{{[0-9]+}} RDHWR_MMR6
   wait                     # CHECK: wait                # encoding: [0x00,0x00,0x93,0x7c]
   wait 17                  # CHECK: wait 17             # encoding: [0x00,0x11,0x93,0x7c]
   ssnop                    # CHECK: ssnop               # encoding: [0x00,0x00,0x08,0x00]
@@ -276,7 +283,9 @@
   lbu16 $3, 4($17)         # CHECK: lbu16 $3, 4($17)    # encoding: [0x09,0x94]
   lbu16 $3, -1($17)        # CHECK: lbu16 $3, -1($17)   # encoding: [0x09,0x9f]
   sb  $4, 6($5)            # CHECK: sb  $4, 6($5)       # encoding: [0x18,0x85,0x00,0x06]
+                           # CHECK-NEXT:                # <MCInst #{{[0-9]+}} SB_MMR6
   sh $4, 6($5)             # CHECK: sh $4, 6($5)        # encoding: [0x38,0x85,0x00,0x06]
+                           # CHECK-NEXT:                # <MCInst #{{[0-9]+}} SH_MMR6
   lw $4, 6($5)             # CHECK: lw $4, 6($5)        # encoding: [0xfc,0x85,0x00,0x06]
   lui $6, 17767            # CHECK: lui $6, 17767       # encoding: [0x10,0xc0,0x45,0x67]
   addu16 $6, $17, $4       # CHECK: addu16 $6, $17, $4  # encoding: [0x04,0xcc]
@@ -305,7 +314,9 @@
   subu16 $5, $16, $3       # CHECK: subu16 $5, $16, $3  # encoding: [0x04,0x3b]
   xor16 $17, $5            # CHECK: xor16 $17, $5       # encoding: [0x44,0xd8]
   lb $4, 8($5)             # CHECK: lb $4, 8($5)        # encoding: [0x1c,0x85,0x00,0x08]
+                           # CHECK-NEXT:                # <MCInst #{{[0-9]+}} LB_MMR6
   lbu $4, 8($5)            # CHECK: lbu $4, 8($5)       # encoding: [0x14,0x85,0x00,0x08]
+                           # CHECK-NEXT:                # <MCInst #{{[0-9]+}} LBU_MMR6
   recip.s $f2, $f4         # CHECK: recip.s $f2, $f4    # encoding: [0x54,0x44,0x12,0x3b]
   recip.d $f2, $f4         # CHECK: recip.d $f2, $f4    # encoding: [0x54,0x44,0x52,0x3b]
   rint.s $f2, $f4          # CHECK: rint.s $f2, $f4     # encoding: [0x54,0x82,0x00,0x20]
diff --git a/llvm/test/MC/Mips/mips1/invalid-mips32r2.s b/llvm/test/MC/Mips/mips1/invalid-mips32r2.s
index 679f21fef6d..cc2c2950336 100644
--- a/llvm/test/MC/Mips/mips1/invalid-mips32r2.s
+++ b/llvm/test/MC/Mips/mips1/invalid-mips32r2.s
@@ -9,3 +9,5 @@
         di                          # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
         ei      $t6                 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
         ei                          # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+        ext     $1, $2, 4, 5        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+        ins     $1, $2, 4, 5        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
diff --git a/llvm/test/MC/Mips/mips2/invalid-mips32r2.s b/llvm/test/MC/Mips/mips2/invalid-mips32r2.s
index 1ac95b2eb0b..ba5e6c4431c 100644
--- a/llvm/test/MC/Mips/mips2/invalid-mips32r2.s
+++ b/llvm/test/MC/Mips/mips2/invalid-mips32r2.s
@@ -98,3 +98,5 @@
         suxc1   $f12,$k1($t5)       # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
         swxc1   $f19,$t4($k0)       # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
         wsbh    $k1,$t1             # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+        ext     $1, $2, 4, 5        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+        ins     $1, $2, 4, 5        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
diff --git a/llvm/test/MC/Mips/mips3/invalid-mips32r2.s b/llvm/test/MC/Mips/mips3/invalid-mips32r2.s
index 178e0f02a58..539203f6120 100644
--- a/llvm/test/MC/Mips/mips3/invalid-mips32r2.s
+++ b/llvm/test/MC/Mips/mips3/invalid-mips32r2.s
@@ -9,3 +9,5 @@
         di                          # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
         ei      $t6                 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
         ei                          # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+        ext     $1, $2, 4, 5        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+        ins     $1, $2, 4, 5        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
diff --git a/llvm/test/MC/Mips/mips32/invalid-mips32r2.s b/llvm/test/MC/Mips/mips32/invalid-mips32r2.s
index 07a1e8f53a1..64a00809953 100644
--- a/llvm/test/MC/Mips/mips32/invalid-mips32r2.s
+++ b/llvm/test/MC/Mips/mips32/invalid-mips32r2.s
@@ -34,3 +34,5 @@
         suxc1   $f12,$k1($t5)       # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
         swxc1   $f19,$t4($k0)       # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
         wsbh    $k1,$t1             # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+        ext     $1, $2, 4, 5        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+        ins     $1, $2, 4, 5        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
diff --git a/llvm/test/MC/Mips/mips4/invalid-mips32r2.s b/llvm/test/MC/Mips/mips4/invalid-mips32r2.s
index 3e787585744..18dfc8a19a3 100644
--- a/llvm/test/MC/Mips/mips4/invalid-mips32r2.s
+++ b/llvm/test/MC/Mips/mips4/invalid-mips32r2.s
@@ -9,3 +9,5 @@
         di                          # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
         ei      $t6                 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
         ei                          # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+        ext     $1, $2, 4, 5        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+        ins     $1, $2, 4, 5        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
diff --git a/llvm/test/MC/Mips/mips5/invalid-mips32r2.s b/llvm/test/MC/Mips/mips5/invalid-mips32r2.s
index a369efa5a65..7d501e50cb4 100644
--- a/llvm/test/MC/Mips/mips5/invalid-mips32r2.s
+++ b/llvm/test/MC/Mips/mips5/invalid-mips32r2.s
@@ -9,3 +9,5 @@
         di                          # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
         ei      $t6                 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
         ei                          # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+        ext     $1, $2, 4, 5        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+        ins     $1, $2, 4, 5        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled