[ARM][v8.5A] Add speculation barrier to ARM & Thumb instruction sets

This is a new barrier which limits speculative execution of the
instructions following it.

Patch by Pablo Barrio!

Differential revision: https://reviews.llvm.org/D52477

llvm-svn: 343213

5 files changed, 44 insertions, 0 deletions

diff --git a/llvm/test/MC/ARM/armv8.5a-specctrl-error-thumb.s b/llvm/test/MC/ARM/armv8.5a-specctrl-error-thumb.s
new file mode 100644
index 00000000000..359aec96014
--- /dev/null
+++ b/llvm/test/MC/ARM/armv8.5a-specctrl-error-thumb.s
@@ -0,0 +1,6 @@
+// RUN: not llvm-mc -triple thumbv8 -show-encoding -mattr=+specctrl < %s 2>&1 | FileCheck %s
+
+it eq
+sbeq
+
+// CHECK: instruction 'sb' is not predicable, but condition code specified
diff --git a/llvm/test/MC/ARM/armv8.5a-specctrl-error.s b/llvm/test/MC/ARM/armv8.5a-specctrl-error.s
new file mode 100644
index 00000000000..5a018df6b0f
--- /dev/null
+++ b/llvm/test/MC/ARM/armv8.5a-specctrl-error.s
@@ -0,0 +1,5 @@
+// RUN: not llvm-mc -triple armv8 -show-encoding -mattr=+specctrl < %s 2>&1 | FileCheck %s
+
+sbeq
+
+// CHECK: instruction 'sb' is not predicable
diff --git a/llvm/test/MC/ARM/armv8.5a-specctrl.s b/llvm/test/MC/ARM/armv8.5a-specctrl.s
new file mode 100644
index 00000000000..2d799e680ed
--- /dev/null
+++ b/llvm/test/MC/ARM/armv8.5a-specctrl.s
@@ -0,0 +1,15 @@
+// RUN:     llvm-mc -triple armv8   -show-encoding -mattr=+specctrl < %s      | FileCheck %s
+// RUN:     llvm-mc -triple armv8   -show-encoding -mattr=+v8.5a    < %s      | FileCheck %s
+// RUN: not llvm-mc -triple armv8   -show-encoding -mattr=-specctrl < %s 2>&1 | FileCheck %s --check-prefix=NOSB
+// RUN:     llvm-mc -triple thumbv8 -show-encoding -mattr=+specctrl < %s      | FileCheck %s --check-prefix=THUMB
+// RUN:     llvm-mc -triple thumbv8 -show-encoding -mattr=+v8.5a    < %s      | FileCheck %s --check-prefix=THUMB
+// RUN: not llvm-mc -triple thumbv8 -show-encoding -mattr=-specctrl < %s 2>&1 | FileCheck %s --check-prefix=NOSB
+
+// Flag manipulation
+sb
+
+// CHECK: sb    @ encoding: [0x70,0xf0,0x7f,0xf5]
+// THUMB: sb    @ encoding: [0xbf,0xf3,0x70,0x8f]
+
+// NOSB: instruction requires: specctrl
+// NOSB-NEXT: sb
diff --git a/llvm/test/MC/Disassembler/ARM/armv8.5a-specctrl-thumb.txt b/llvm/test/MC/Disassembler/ARM/armv8.5a-specctrl-thumb.txt
new file mode 100644
index 00000000000..5703408b130
--- /dev/null
+++ b/llvm/test/MC/Disassembler/ARM/armv8.5a-specctrl-thumb.txt
@@ -0,0 +1,9 @@
+# RUN: llvm-mc -triple=thumbv8 -mattr=+specctrl -disassemble < %s      | FileCheck %s
+# RUN: llvm-mc -triple=thumbv8 -mattr=+v8.5a    -disassemble < %s      | FileCheck %s
+# RUN: llvm-mc -triple=thumbv8 -mattr=-specctrl -disassemble < %s 2>&1 | FileCheck %s --check-prefix=NOSB
+
+0xbf 0xf3 0x70 0x8f
+
+# CHECK: sb
+# NOSB: invalid instruction encoding
+# NOSB-NEXT: 0xbf 0xf3 0x70 0x8f
diff --git a/llvm/test/MC/Disassembler/ARM/armv8.5a-specctrl.txt b/llvm/test/MC/Disassembler/ARM/armv8.5a-specctrl.txt
new file mode 100644
index 00000000000..f9d8b5397ad
--- /dev/null
+++ b/llvm/test/MC/Disassembler/ARM/armv8.5a-specctrl.txt
@@ -0,0 +1,9 @@
+# RUN: llvm-mc -triple=armv8 -mattr=+specctrl -disassemble < %s      | FileCheck %s
+# RUN: llvm-mc -triple=armv8 -mattr=+v8.5a    -disassemble < %s      | FileCheck %s
+# RUN: llvm-mc -triple=armv8 -mattr=-specctrl -disassemble < %s 2>&1 | FileCheck %s --check-prefix=NOSB
+
+0x70 0xf0 0x7f 0xf5
+
+# CHECK:    sb
+# NOSB: invalid instruction encoding
+# NOSB-NEXT: 0x70 0xf0 0x7f 0xf5