summaryrefslogtreecommitdiffstats
path: root/llvm/test/MC/Mips/mips64-alu-instructions.s
diff options
context:
space:
mode:
authorJack Carter <jcarter@mips.com>2013-02-05 08:32:10 +0000
committerJack Carter <jcarter@mips.com>2013-02-05 08:32:10 +0000
commit9c1a027fe884c11f0302534edbc6320f8c83999d (patch)
tree875eaf2b1374f0a3404479b6444f9ae0b31d5fd8 /llvm/test/MC/Mips/mips64-alu-instructions.s
parent31876b4efd5efcd8517d57fb998aed915bfdd6d4 (diff)
downloadbcm5719-llvm-9c1a027fe884c11f0302534edbc6320f8c83999d.tar.gz
bcm5719-llvm-9c1a027fe884c11f0302534edbc6320f8c83999d.zip
This patch that sets the EmitAlias flag in td files
and enables the instruction printer to print aliased instructions. Due to usage of RegisterOperands a change in common code (utils/TableGen/AsmWriterEmitter.cpp) is required to get the correct register value if it is a RegisterOperand. Contributer: Vladimir Medic llvm-svn: 174358
Diffstat (limited to 'llvm/test/MC/Mips/mips64-alu-instructions.s')
-rw-r--r--llvm/test/MC/Mips/mips64-alu-instructions.s12
1 files changed, 6 insertions, 6 deletions
diff --git a/llvm/test/MC/Mips/mips64-alu-instructions.s b/llvm/test/MC/Mips/mips64-alu-instructions.s
index d30ddeee717..1b4ebdfbbd4 100644
--- a/llvm/test/MC/Mips/mips64-alu-instructions.s
+++ b/llvm/test/MC/Mips/mips64-alu-instructions.s
@@ -31,7 +31,7 @@
# CHECK: xori $9, $6, 17767 # encoding: [0x67,0x45,0xc9,0x38]
# CHECK: xori $9, $6, 17767 # encoding: [0x67,0x45,0xc9,0x38]
# CHECK: wsbh $6, $7 # encoding: [0xa0,0x30,0x07,0x7c]
-# CHECK: nor $7, $8, $zero # encoding: [0x27,0x38,0x00,0x01]
+# CHECK: not $7, $8 # encoding: [0x27,0x38,0x00,0x01]
and $9, $6, $7
and $9, $6, 17767
andi $9, $6, 17767
@@ -76,11 +76,11 @@
# CHECK: msubu $6, $7 # encoding: [0x05,0x00,0xc7,0x70]
# CHECK: mult $3, $5 # encoding: [0x18,0x00,0x65,0x00]
# CHECK: multu $3, $5 # encoding: [0x19,0x00,0x65,0x00]
-# CHECK: dsubu $4, $3, $5 # encoding: [0x2f,0x20,0x65,0x00]
-# CHECK: daddu $7, $8, $zero # encoding: [0x2d,0x38,0x00,0x01]
-# CHECK: .set push
-# CHECK: .set mips32r2
-# CHECK: rdhwr $5, $29
+# CHECK: dsubu $4, $3, $5 # encoding: [0x2f,0x20,0x65,0x00]
+# CHECK: move $7, $8 # encoding: [0x2d,0x38,0x00,0x01]
+# CHECK: .set push
+# CHECK: .set mips32r2
+# CHECK: rdhwr $5, $29
# CHECK: .set pop # encoding: [0x3b,0xe8,0x05,0x7c]
dadd $9,$6,$7
OpenPOWER on IntegriCloud