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| author | Daniel Sanders <daniel.sanders@imgtec.com> | 2014-06-13 13:15:59 +0000 |
|---|---|---|
| committer | Daniel Sanders <daniel.sanders@imgtec.com> | 2014-06-13 13:15:59 +0000 |
| commit | c171f65a87782f7db101285b9e9905e25abe0d82 (patch) | |
| tree | ab16efdc054c90545d407447c743621d0d0f3e08 /llvm/test/MC/Mips/mips4 | |
| parent | af8b32e1766e9731027d9adb7a9195d356258704 (diff) | |
| download | bcm5719-llvm-c171f65a87782f7db101285b9e9905e25abe0d82.tar.gz bcm5719-llvm-c171f65a87782f7db101285b9e9905e25abe0d82.zip | |
[mips] Add cache and pref instructions
Summary:
cache and pref were added in MIPS-III, and MIPS32 but were re-encoded in
MIPS32r6/MIPS64r6 to use a 9-bit offset rather than the 16-bit offset
available to earlier cores.
Resolved the decoding conflict between pref and lwc3.
Depends on D4115
Reviewers: zoran.jovanovic, jkolek, vmedic
Reviewed By: vmedic
Differential Revision: http://reviews.llvm.org/D4116
llvm-svn: 210900
Diffstat (limited to 'llvm/test/MC/Mips/mips4')
| -rw-r--r-- | llvm/test/MC/Mips/mips4/valid.s | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/llvm/test/MC/Mips/mips4/valid.s b/llvm/test/MC/Mips/mips4/valid.s index b6a89fff6ea..4b328814e1f 100644 --- a/llvm/test/MC/Mips/mips4/valid.s +++ b/llvm/test/MC/Mips/mips4/valid.s @@ -21,6 +21,7 @@ bgezal $0, 21100 # CHECK: bal 21100 # encoding: [0x04,0x11,0x14,0x9b] bgezal $6, 21100 # CHECK: bgezal $6, 21100 # encoding: [0x04,0xd1,0x14,0x9b] bltzal $6, 21100 # CHECK: bltzal $6, 21100 # encoding: [0x04,0xd0,0x14,0x9b] + cache 1, 8($5) # CHECK: cache 1, 8($5) # encoding: [0xbc,0xa1,0x00,0x08] c.ngl.d $f29,$f29 c.ngle.d $f0,$f16 c.sf.d $f30,$f0 @@ -149,6 +150,7 @@ nop nor $a3,$zero,$a3 or $12,$s0,$sp + pref 1, 8($5) # CHECK: pref 1, 8($5) # encoding: [0xcc,0xa1,0x00,0x08] round.l.d $f12,$f1 round.l.s $f25,$f5 round.w.d $f6,$f4 |
