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| author | Vladimir Medic <Vladimir.Medic@imgtec.com> | 2015-02-25 15:24:37 +0000 |
|---|---|---|
| committer | Vladimir Medic <Vladimir.Medic@imgtec.com> | 2015-02-25 15:24:37 +0000 |
| commit | bcb7467540f6bb497c3b268070cd747ca2687480 (patch) | |
| tree | 4467589df27cbfebb4ebb723ff83326f7fd79480 /llvm/test/MC/Mips/mips4 | |
| parent | ab7afa9144107ddd7164ac411f215d1627532f2a (diff) | |
| download | bcm5719-llvm-bcb7467540f6bb497c3b268070cd747ca2687480.tar.gz bcm5719-llvm-bcb7467540f6bb497c3b268070cd747ca2687480.zip | |
[MIPS]Multiple and add instructions for Mips are currently available in mips32r2/mips64r2 and later but should also be available in mips4, mips5, and mips64. This patch fixes the requested features and updates the corresponding test files.
llvm-svn: 230500
Diffstat (limited to 'llvm/test/MC/Mips/mips4')
| -rw-r--r-- | llvm/test/MC/Mips/mips4/invalid-mips64r2.s | 4 | ||||
| -rw-r--r-- | llvm/test/MC/Mips/mips4/valid-xfail.s | 8 | ||||
| -rw-r--r-- | llvm/test/MC/Mips/mips4/valid.s | 8 |
3 files changed, 8 insertions, 12 deletions
diff --git a/llvm/test/MC/Mips/mips4/invalid-mips64r2.s b/llvm/test/MC/Mips/mips4/invalid-mips64r2.s index b259706265a..70a8261d764 100644 --- a/llvm/test/MC/Mips/mips4/invalid-mips64r2.s +++ b/llvm/test/MC/Mips/mips4/invalid-mips64r2.s @@ -17,19 +17,15 @@ luxc1 $f19,$s6($s5) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled madd $s6,$t5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled madd $zero,$t1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled - madd.s $f1,$f31,$f19,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled maddu $s3,$gp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled maddu $t8,$s2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled mfc0 $a2,$14,1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled mfhc1 $s8,$f24 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled msub $s7,$k1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled - msub.s $f12,$f19,$f10,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled msubu $t7,$a1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled mtc0 $t1,$29,3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled mthc1 $zero,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled mul $s0,$s4,$at # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled - nmadd.s $f0,$f5,$f25,$f12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled - nmsub.s $f1,$f24,$f19,$f4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled pause # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled seb $t9,$t7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled seh $v1,$t4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled diff --git a/llvm/test/MC/Mips/mips4/valid-xfail.s b/llvm/test/MC/Mips/mips4/valid-xfail.s index ff6f457ca83..9c647d15115 100644 --- a/llvm/test/MC/Mips/mips4/valid-xfail.s +++ b/llvm/test/MC/Mips/mips4/valid-xfail.s @@ -35,14 +35,6 @@ c.ult.s $fcc7,$f24,$f10 c.un.d $fcc6,$f23,$f24 c.un.s $fcc1,$f30,$f4 - madd.d $f18,$f19,$f26,$f20 - madd.s $f1,$f31,$f19,$f25 - msub.d $f10,$f1,$f31,$f18 - msub.s $f12,$f19,$f10,$f16 - nmadd.d $f18,$f9,$f14,$f19 - nmadd.s $f0,$f5,$f25,$f12 - nmsub.d $f30,$f8,$f16,$f30 - nmsub.s $f1,$f24,$f19,$f4 recip.d $f19,$f6 recip.s $f3,$f30 rsqrt.d $f3,$f28 diff --git a/llvm/test/MC/Mips/mips4/valid.s b/llvm/test/MC/Mips/mips4/valid.s index c221b764b16..fc747a58ce8 100644 --- a/llvm/test/MC/Mips/mips4/valid.s +++ b/llvm/test/MC/Mips/mips4/valid.s @@ -134,6 +134,8 @@ lwr $zero,-19147($gp) lwu $s3,-24086($v1) lwxc1 $f12,$s1($s8) + madd.d $f18, $f22, $f26, $f20 # encoding: [0x4e,0xd4,0xd4,0xa1] + madd.s $f2, $f30, $f18, $f24 # encoding: [0x4f,0xd8,0x90,0xa0] mfc1 $a3,$f27 mfhi $s3 mfhi $sp @@ -156,6 +158,8 @@ movz $a1,$s6,$9 movz.d $f12,$f29,$9 movz.s $f25,$f7,$v1 + msub.d $f10, $f2, $f30, $f18 # encoding: [0x4c,0x52,0xf2,0xa9] + msub.s $f12, $f18, $f10, $f16 # encoding: [0x4e,0x50,0x53,0x28] mtc1 $s8,$f9 mthi $s1 mtlo $sp @@ -170,6 +174,10 @@ negu $2,$3 # CHECK: negu $2, $3 # encoding: [0x00,0x03,0x10,0x23] neg.d $f27,$f18 neg.s $f1,$f15 + nmadd.d $f18, $f8, $f14, $f20 # encoding: [0x4d,0x14,0x74,0xb1] + nmadd.s $f0, $f4, $f24, $f12 # encoding: [0x4c,0x8c,0xc0,0x30] + nmsub.d $f30, $f8, $f16, $f30 # encoding: [0x4d,0x1e,0x87,0xb9] + nmsub.s $f0, $f24, $f20, $f4 # encoding: [0x4f,0x04,0xa0,0x38] nop nor $a3,$zero,$a3 or $12,$s0,$sp |
