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author | Matheus Almeida <matheus.almeida@imgtec.com> | 2014-06-18 17:10:30 +0000 |
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committer | Matheus Almeida <matheus.almeida@imgtec.com> | 2014-06-18 17:10:30 +0000 |
commit | 784f797d4c723010702d9dec7ae7fb120f7190f2 (patch) | |
tree | f61d8123f139cb89797109ec0e4d04f930507da5 /llvm/test/MC/Mips/mips4 | |
parent | 24d8b848385e3dbfda4c8d629f40b0a7ea335dc0 (diff) | |
download | bcm5719-llvm-784f797d4c723010702d9dec7ae7fb120f7190f2.tar.gz bcm5719-llvm-784f797d4c723010702d9dec7ae7fb120f7190f2.zip |
[mips] SYNC $stype instruction was added in Mips32
but SYNC with an implied operand ($stype = 0) is valid since Mips2.
llvm-svn: 211185
Diffstat (limited to 'llvm/test/MC/Mips/mips4')
-rw-r--r-- | llvm/test/MC/Mips/mips4/invalid-mips32.s | 10 | ||||
-rw-r--r-- | llvm/test/MC/Mips/mips4/valid.s | 1 |
2 files changed, 11 insertions, 0 deletions
diff --git a/llvm/test/MC/Mips/mips4/invalid-mips32.s b/llvm/test/MC/Mips/mips4/invalid-mips32.s new file mode 100644 index 00000000000..52dea02d10c --- /dev/null +++ b/llvm/test/MC/Mips/mips4/invalid-mips32.s @@ -0,0 +1,10 @@ +# Instructions that are invalid +# +# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips4 \ +# RUN: 2>%t1 +# RUN: FileCheck %s < %t1 + + .set noat + + sync 0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + sync 1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled diff --git a/llvm/test/MC/Mips/mips4/valid.s b/llvm/test/MC/Mips/mips4/valid.s index 2086a12602a..949b91da922 100644 --- a/llvm/test/MC/Mips/mips4/valid.s +++ b/llvm/test/MC/Mips/mips4/valid.s @@ -198,6 +198,7 @@ swl $15,13694($s3) swr $s1,-26590($14) swxc1 $f19,$12($k0) + sync # CHECK: sync # encoding: [0x00,0x00,0x00,0x0f] teqi $s5,-17504 tgei $s1,5025 tgeiu $sp,-28621 |