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| author | Simon Dardis <simon.dardis@mips.com> | 2018-03-07 11:39:48 +0000 |
|---|---|---|
| committer | Simon Dardis <simon.dardis@mips.com> | 2018-03-07 11:39:48 +0000 |
| commit | 52ae4f078e0c14e51ef4e7f8734b935c8a7aebd2 (patch) | |
| tree | fe8f1d300ba8a2ff5c6d80f9ead2e3f448ef068b /llvm/test/MC/Mips/mips4 | |
| parent | ba900ab93d8542f83e74ab4986d089b7704acc8d (diff) | |
| download | bcm5719-llvm-52ae4f078e0c14e51ef4e7f8734b935c8a7aebd2.tar.gz bcm5719-llvm-52ae4f078e0c14e51ef4e7f8734b935c8a7aebd2.zip | |
[mips] Correct the definition of m(f|t)c(0|2)
These instructions are defined as taking a GPR register and a
coprocessor register for ISAs up to MIPS32. MIPS32 extended the
definition to allow a selector--a value from 0 to 32--to access
another register.
These instructions are now internally defined as being MIPS-I
instructions, but are rejected for pre-MIPS32 ISA's if they have
an explicit selector which is non-zero. This deviates slightly from
GAS's behaviour which rejects assembly instructions with an
explicit selector for pre-MIPS32 ISAs.
E.g:
mfc0 $4, $5, 0
is rejected by GAS for MIPS-I to MIPS-V but will be accepted
with this patch for MIPS-I to MIPS-V.
Reviewers: atanasyan
Differential Revision: https://reviews.llvm.org/D41662
llvm-svn: 326890
Diffstat (limited to 'llvm/test/MC/Mips/mips4')
| -rw-r--r-- | llvm/test/MC/Mips/mips4/invalid-mips32.s | 5 | ||||
| -rw-r--r-- | llvm/test/MC/Mips/mips4/invalid-mips64.s | 4 | ||||
| -rw-r--r-- | llvm/test/MC/Mips/mips4/invalid-mips64r2.s | 4 |
3 files changed, 9 insertions, 4 deletions
diff --git a/llvm/test/MC/Mips/mips4/invalid-mips32.s b/llvm/test/MC/Mips/mips4/invalid-mips32.s index 6d7366dcc31..0bb0bda50b5 100644 --- a/llvm/test/MC/Mips/mips4/invalid-mips32.s +++ b/llvm/test/MC/Mips/mips4/invalid-mips32.s @@ -7,3 +7,8 @@ .set noat sync 1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: s-type must be zero or unspecified for pre-MIPS32 ISAs + mtc0 $4, $5, 1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: selector must be zero for pre-MIPS32 ISAs + mfc0 $4, $5, 1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: selector must be zero for pre-MIPS32 ISAs + mtc2 $4, $5, 1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: selector must be zero for pre-MIPS32 ISAs + mfc2 $4, $5, 1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: selector must be zero for pre-MIPS32 ISAs + diff --git a/llvm/test/MC/Mips/mips4/invalid-mips64.s b/llvm/test/MC/Mips/mips4/invalid-mips64.s index c6245ccd106..ec4146995a7 100644 --- a/llvm/test/MC/Mips/mips4/invalid-mips64.s +++ b/llvm/test/MC/Mips/mips4/invalid-mips64.s @@ -16,9 +16,9 @@ madd $zero,$t1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled maddu $s3,$gp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled maddu $t8,$s2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled - mfc0 $a2,$14,1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + mfc0 $a2,$14,1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: selector must be zero for pre-MIPS32 ISAs msub $s7,$k1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled msubu $t7,$a1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled - mtc0 $t1,$29,3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + mtc0 $t1,$29,3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: selector must be zero for pre-MIPS32 ISAs mul $s0,$s4,$at # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled suxc1 $f12,$k1($t5) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled diff --git a/llvm/test/MC/Mips/mips4/invalid-mips64r2.s b/llvm/test/MC/Mips/mips4/invalid-mips64r2.s index 70a8261d764..d4a8ae1672c 100644 --- a/llvm/test/MC/Mips/mips4/invalid-mips64r2.s +++ b/llvm/test/MC/Mips/mips4/invalid-mips64r2.s @@ -19,11 +19,11 @@ madd $zero,$t1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled maddu $s3,$gp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled maddu $t8,$s2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled - mfc0 $a2,$14,1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + mfc0 $a2,$14,1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: selector must be zero for pre-MIPS32 ISAs mfhc1 $s8,$f24 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled msub $s7,$k1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled msubu $t7,$a1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled - mtc0 $t1,$29,3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + mtc0 $t1,$29,3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: selector must be zero for pre-MIPS32 ISAs mthc1 $zero,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled mul $s0,$s4,$at # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled pause # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled |
