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| author | Simon Dardis <simon.dardis@imgtec.com> | 2016-07-26 09:13:46 +0000 |
|---|---|---|
| committer | Simon Dardis <simon.dardis@imgtec.com> | 2016-07-26 09:13:46 +0000 |
| commit | 273fc26b792884088407a1eb665aff0ec4204af8 (patch) | |
| tree | 52bc942360e6daff1bde9134d89432a31d587a4c /llvm/test/MC/Mips/mips4 | |
| parent | 57d053511fbd1f2dd30f6d5cc729846f0e0aa3e3 (diff) | |
| download | bcm5719-llvm-273fc26b792884088407a1eb665aff0ec4204af8.tar.gz bcm5719-llvm-273fc26b792884088407a1eb665aff0ec4204af8.zip | |
[mips] sgtu, s[rl]l, sra, dnegu, neg instruction aliases
Add the instruction alias sgtu (register form only), two operand forms of
s[rl]l and sra, and missing single/two operand forms of dnegu/neg.
Reviewers: dsanders
Differential Revision: https://reviews.llvm.org/D22752
llvm-svn: 276736
Diffstat (limited to 'llvm/test/MC/Mips/mips4')
| -rw-r--r-- | llvm/test/MC/Mips/mips4/valid.s | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/llvm/test/MC/Mips/mips4/valid.s b/llvm/test/MC/Mips/mips4/valid.s index 500560e99da..7a7259e8aea 100644 --- a/llvm/test/MC/Mips/mips4/valid.s +++ b/llvm/test/MC/Mips/mips4/valid.s @@ -179,6 +179,8 @@ a: mult $sp,$v0 multu $gp,$k0 multu $9,$s2 + neg $2 # CHECK: neg $2, $2 # encoding: [0x00,0x02,0x10,0x22] + neg $2, $3 # CHECK: neg $2, $3 # encoding: [0x00,0x03,0x10,0x22] negu $2 # CHECK: negu $2, $2 # encoding: [0x00,0x02,0x10,0x23] negu $2,$3 # CHECK: negu $2, $3 # encoding: [0x00,0x03,0x10,0x23] neg.d $f27,$f18 @@ -205,7 +207,12 @@ a: sdl $a3,-20961($s8) sdr $11,-20423($12) sdxc1 $f11,$10($14) + sgt $4, $5 # CHECK: slt $4, $5, $4 # encoding: [0x00,0xa4,0x20,0x2a] + sgt $4, $5, $6 # CHECK: slt $4, $6, $5 # encoding: [0x00,0xc5,0x20,0x2a] + sgtu $4, $5 # CHECK: sltu $4, $5, $4 # encoding: [0x00,0xa4,0x20,0x2b] + sgtu $4, $5, $6 # CHECK: sltu $4, $6, $5 # encoding: [0x00,0xc5,0x20,0x2b] sh $14,-6704($15) + sll $4, $5 # CHECK: sllv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x04] sll $a3,18 # CHECK: sll $7, $7, 18 # encoding: [0x00,0x07,0x3c,0x80] sll $a3,$zero,18 # CHECK: sll $7, $zero, 18 # encoding: [0x00,0x00,0x3c,0x80] sll $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04] @@ -217,10 +224,12 @@ a: sltu $24,$25,-15531 # CHECK: sltiu $24, $25, -15531 # encoding: [0x2f,0x38,0xc3,0x55] sqrt.d $f17,$f22 sqrt.s $f0,$f1 + sra $4, $5 # CHECK: srav $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x07] sra $s1,15 # CHECK: sra $17, $17, 15 # encoding: [0x00,0x11,0x8b,0xc3] sra $s1,$s7,15 # CHECK: sra $17, $23, 15 # encoding: [0x00,0x17,0x8b,0xc3] sra $s1,$s7,$sp # CHECK: srav $17, $23, $sp # encoding: [0x03,0xb7,0x88,0x07] srav $s1,$s7,$sp # CHECK: srav $17, $23, $sp # encoding: [0x03,0xb7,0x88,0x07] + srl $4, $5 # CHECK: srlv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x06] srl $2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2] srl $2,$2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2] srl $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06] |
