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| author | Zoran Jovanovic <zoran.jovanovic@imgtec.com> | 2015-09-15 15:06:26 +0000 |
|---|---|---|
| committer | Zoran Jovanovic <zoran.jovanovic@imgtec.com> | 2015-09-15 15:06:26 +0000 |
| commit | 8eb8c9861d4bfc6ccbd050c4bf8fc0fce4bfdc8f (patch) | |
| tree | 8e22ca144124b04835a20cdf4aa29f7635927c29 /llvm/test/MC/Mips/mips32r6/invalid.s | |
| parent | daace1bb6b5e5275d3014c1614035a36e1ee9a84 (diff) | |
| download | bcm5719-llvm-8eb8c9861d4bfc6ccbd050c4bf8fc0fce4bfdc8f.tar.gz bcm5719-llvm-8eb8c9861d4bfc6ccbd050c4bf8fc0fce4bfdc8f.zip | |
[mips] Add support for branch-likely pseudo-instructions
Differential Revision: http://reviews.llvm.org/D10537
llvm-svn: 247697
Diffstat (limited to 'llvm/test/MC/Mips/mips32r6/invalid.s')
| -rw-r--r-- | llvm/test/MC/Mips/mips32r6/invalid.s | 22 |
1 files changed, 16 insertions, 6 deletions
diff --git a/llvm/test/MC/Mips/mips32r6/invalid.s b/llvm/test/MC/Mips/mips32r6/invalid.s index 0ce75e6143c..d10a945e3ba 100644 --- a/llvm/test/MC/Mips/mips32r6/invalid.s +++ b/llvm/test/MC/Mips/mips32r6/invalid.s @@ -2,17 +2,27 @@ # the assembler (e.g. invalid set of operands or operand's restrictions not met). # RUN: not llvm-mc %s -triple=mips-unknown-linux -mcpu=mips32r6 2>%t1 -# RUN: FileCheck %s < %t1 -check-prefix=ASM +# RUN: FileCheck %s < %t1 .text +local_label: .set noreorder .set noat - jalr.hb $31 # ASM: :[[@LINE]]:9: error: source and destination must be different - jalr.hb $31, $31 # ASM: :[[@LINE]]:9: error: source and destination must be different - ldc2 $8,-21181($at) # ASM: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled - sdc2 $20,23157($s2) # ASM: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled - swc2 $25,24880($s0) # ASM: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + jalr.hb $31 # CHECK: :[[@LINE]]:9: error: source and destination must be different + jalr.hb $31, $31 # CHECK: :[[@LINE]]:9: error: source and destination must be different + ldc2 $8,-21181($at) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + sdc2 $20,23157($s2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + swc2 $25,24880($s0) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled break 1024 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction break 1024, 5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction break 7, 1024 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction break 1024, 1024 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + // FIXME: Following tests are temporarely disabled, until "PredicateControl not in hierarchy" problem is resolved + bltl $7, $8, local_label # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + bltul $7, $8, local_label # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + blel $7, $8, local_label # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + bleul $7, $8, local_label # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + bgel $7, $8, local_label # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + bgeul $7, $8, local_label # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + bgtl $7, $8, local_label # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + bgtul $7, $8, local_label # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled |
