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authorDaniel Sanders <daniel.sanders@imgtec.com>2014-08-17 19:47:47 +0000
committerDaniel Sanders <daniel.sanders@imgtec.com>2014-08-17 19:47:47 +0000
commitf28bf76d8875c44b0e3608b8e2421fe3556fbcd4 (patch)
tree31227136a7c6dd34a9d83dc51bf2dc05a14b4fc0 /llvm/test/MC/Mips/mips32/valid.s
parent78c44725f8f57beb35e2756e1c9e983de0a30041 (diff)
downloadbcm5719-llvm-f28bf76d8875c44b0e3608b8e2421fe3556fbcd4.tar.gz
bcm5719-llvm-f28bf76d8875c44b0e3608b8e2421fe3556fbcd4.zip
Revert: r215698 - Current implementation of c.cond.fmt instructions only accept default cc0 register...
It causes a number of regressions when -fintegrated-as is enabled. This happens because there are codegen-only instructions that incorrectly uses the first operand as the encoding for the $fcc register. The regressions do not occur when -via-file-asm is also given. llvm-svn: 215847
Diffstat (limited to 'llvm/test/MC/Mips/mips32/valid.s')
-rw-r--r--llvm/test/MC/Mips/mips32/valid.s28
1 files changed, 0 insertions, 28 deletions
diff --git a/llvm/test/MC/Mips/mips32/valid.s b/llvm/test/MC/Mips/mips32/valid.s
index 5a94a30130e..d330905ae29 100644
--- a/llvm/test/MC/Mips/mips32/valid.s
+++ b/llvm/test/MC/Mips/mips32/valid.s
@@ -28,34 +28,6 @@
c.ngle.d $f0,$f16
c.sf.d $f30,$f0
c.sf.s $f14,$f22
- c.eq.d $fcc1,$f15,$f15
- c.eq.s $fcc5,$f24,$f17
- c.f.d $fcc4,$f11,$f21
- c.f.s $fcc4,$f30,$f7
- c.le.d $fcc4,$f18,$f1
- c.le.s $fcc6,$f24,$f4
- c.lt.d $fcc3,$f9,$f3
- c.lt.s $fcc2,$f17,$f14
- c.nge.d $fcc5,$f21,$f16
- c.nge.s $fcc3,$f11,$f8
- c.ngl.s $fcc2,$f31,$f23
- c.ngle.s $fcc2,$f18,$f23
- c.ngt.d $fcc4,$f24,$f7
- c.ngt.s $fcc5,$f8,$f13
- c.ole.d $fcc2,$f16,$f31
- c.ole.s $fcc3,$f7,$f20
- c.olt.d $fcc4,$f19,$f28
- c.olt.s $fcc6,$f20,$f7
- c.seq.d $fcc4,$f31,$f7
- c.seq.s $fcc7,$f1,$f25
- c.ueq.d $fcc4,$f13,$f25
- c.ueq.s $fcc6,$f3,$f30
- c.ule.d $fcc7,$f25,$f18
- c.ule.s $fcc7,$f21,$f30
- c.ult.d $fcc6,$f6,$f17
- c.ult.s $fcc7,$f24,$f10
- c.un.d $fcc6,$f23,$f24
- c.un.s $fcc1,$f30,$f4
ceil.w.d $f11,$f25
ceil.w.s $f6,$f20
cfc1 $s1,$21
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