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| author | Daniel Sanders <daniel.sanders@imgtec.com> | 2014-06-12 15:00:17 +0000 |
|---|---|---|
| committer | Daniel Sanders <daniel.sanders@imgtec.com> | 2014-06-12 15:00:17 +0000 |
| commit | 3d3ea53f32c0638ccd643af3e67807e0a8b325ab (patch) | |
| tree | 3f06c555eab0e72dbf11480bd3eae484a397b9ab /llvm/test/MC/Mips/mips32/valid.s | |
| parent | 39a1ca75ba586a10f0aab3679255428c43c41909 (diff) | |
| download | bcm5719-llvm-3d3ea53f32c0638ccd643af3e67807e0a8b325ab.tar.gz bcm5719-llvm-3d3ea53f32c0638ccd643af3e67807e0a8b325ab.zip | |
[mips][mips64r6] bc1[tf] are not available on MIPS32r6/MIPS64r6
Summary:
Also tightened up the acceptable condition operand for these instructions
on MIPS-I to MIPS-III. Support for $fcc[1-7] was added in MIPS-IV. Prior
to that only $fcc0 is acceptable.
We currently don't optimize (BEQZ (NOT $a), $target) and similar. It's
probably best to do this in InstCombine.
Depends on D4111
Reviewers: jkolek, zoran.jovanovic, vmedic
Reviewed By: vmedic
Differential Revision: http://reviews.llvm.org/D4112
llvm-svn: 210787
Diffstat (limited to 'llvm/test/MC/Mips/mips32/valid.s')
| -rw-r--r-- | llvm/test/MC/Mips/mips32/valid.s | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/llvm/test/MC/Mips/mips32/valid.s b/llvm/test/MC/Mips/mips32/valid.s index bc29bdcebf9..2c410c68475 100644 --- a/llvm/test/MC/Mips/mips32/valid.s +++ b/llvm/test/MC/Mips/mips32/valid.s @@ -11,6 +11,12 @@ addi $13,$9,26322 addu $9,$a0,$a2 and $s7,$v0,$12 + bc1f $fcc0, 4 # CHECK: bc1f 4 # encoding: [0x45,0x00,0x00,0x01] + bc1f $fcc1, 4 # CHECK: bc1f $fcc1, 4 # encoding: [0x45,0x04,0x00,0x01] + bc1f 4 # CHECK: bc1f 4 # encoding: [0x45,0x00,0x00,0x01] + bc1t $fcc0, 4 # CHECK: bc1t 4 # encoding: [0x45,0x01,0x00,0x01] + bc1t $fcc1, 4 # CHECK: bc1t $fcc1, 4 # encoding: [0x45,0x05,0x00,0x01] + bc1t 4 # CHECK: bc1t 4 # encoding: [0x45,0x01,0x00,0x01] c.ngl.d $f29,$f29 c.ngle.d $f0,$f16 c.sf.d $f30,$f0 |
