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| author | Daniel Sanders <daniel.sanders@imgtec.com> | 2014-05-09 13:02:27 +0000 |
|---|---|---|
| committer | Daniel Sanders <daniel.sanders@imgtec.com> | 2014-05-09 13:02:27 +0000 |
| commit | f2056bef3246f93ae272cb7322da9618b08f7e05 (patch) | |
| tree | 06b4abc424c4511eca652b8da3b972925ec6cafb /llvm/test/MC/Mips/mips2/invalid-mips3-wrong-error.s | |
| parent | 826b5adb6c21ebfded6fa67211d66a6257d3edfd (diff) | |
| download | bcm5719-llvm-f2056bef3246f93ae272cb7322da9618b08f7e05.tar.gz bcm5719-llvm-f2056bef3246f93ae272cb7322da9618b08f7e05.zip | |
[mips] Marked up instructions added in MIPS-III and tested that IAS for -mcpu=mips[12] does not accept them
Summary:
This required a new instruction group representing the 32-bit subset of
MIPS-III that was available in MIPS32
A small number of instructions are correctly rejected but with the wrong error
message. These have been placed in a separate test for now.
There's some obvious InstAlias's that ought to be marked MIPS-III but arent.
This is because they are not currently tested. I intend to catch these with
a final pass through the tablegen records to find tablegen records without
ISA annotations.
Depends on D3674
Reviewers: vmedic
Reviewed By: vmedic
Differential Revision: http://reviews.llvm.org/D3675
llvm-svn: 208408
Diffstat (limited to 'llvm/test/MC/Mips/mips2/invalid-mips3-wrong-error.s')
| -rw-r--r-- | llvm/test/MC/Mips/mips2/invalid-mips3-wrong-error.s | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/llvm/test/MC/Mips/mips2/invalid-mips3-wrong-error.s b/llvm/test/MC/Mips/mips2/invalid-mips3-wrong-error.s new file mode 100644 index 00000000000..a3f829b77c3 --- /dev/null +++ b/llvm/test/MC/Mips/mips2/invalid-mips3-wrong-error.s @@ -0,0 +1,19 @@ +# Instructions that are invalid and are correctly rejected but use the wrong +# error message at the moment. +# +# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips2 \ +# RUN: 2>%t1 +# RUN: FileCheck %s < %t1 + + .set noat + dmult $s7,$a5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + dsub $a3,$s6,$a4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + ld $sp,-28645($s1) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + ldl $t8,-4167($t8) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + ldr $t2,-30358($s4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + lld $zero,-14736($ra) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + lwu $s3,-24086($v1) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + scd $t3,-8243($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + sd $t0,5835($a6) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + sdl $a3,-20961($s8) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + sdr $a7,-20423($t0) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction |
