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| author | Sander de Smalen <sander.desmalen@arm.com> | 2017-12-18 14:34:24 +0000 |
|---|---|---|
| committer | Sander de Smalen <sander.desmalen@arm.com> | 2017-12-18 14:34:24 +0000 |
| commit | 190979189a9aca2d9475caed279e1d29b15329b5 (patch) | |
| tree | 844d7326db5a227f84493ab04c0d298d16f5af5a /llvm/test/MC/Mips/mips1/invalid-mips3.s | |
| parent | 8c92c899c6f4a895d3ebe990b684e1c30df12bc7 (diff) | |
| download | bcm5719-llvm-190979189a9aca2d9475caed279e1d29b15329b5.tar.gz bcm5719-llvm-190979189a9aca2d9475caed279e1d29b15329b5.zip | |
[TableGen][AsmMatcherEmitter] Only choose specific diagnostic for enabled instruction
Summary:
When emitting a diagnostic for an invalid operand, a specific diagnostic
should only be reported when the instruction being matched is actually
enabled by the feature flags.
Patch [3/4] in a series to add parsing of predicates and properly parse SVE
ZIP1/ZIP2 instructions. This patch fixes bogus diagnostic messages for when
the SVE feature is not specified.
Reviewers: rengolin, craig.topper, olista01, sdardis, stoklund
Reviewed By: olista01, sdardis
Subscribers: fhahn, javed.absar, llvm-commits
Differential Revision: https://reviews.llvm.org/D40362
llvm-svn: 320986
Diffstat (limited to 'llvm/test/MC/Mips/mips1/invalid-mips3.s')
| -rw-r--r-- | llvm/test/MC/Mips/mips1/invalid-mips3.s | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/llvm/test/MC/Mips/mips1/invalid-mips3.s b/llvm/test/MC/Mips/mips1/invalid-mips3.s index 42e390df470..6a2543424b8 100644 --- a/llvm/test/MC/Mips/mips1/invalid-mips3.s +++ b/llvm/test/MC/Mips/mips1/invalid-mips3.s @@ -54,8 +54,8 @@ floor.l.s $f12,$f5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled floor.w.d $f14,$f11 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled floor.w.s $f8,$f9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled - lld $zero,-14736($ra) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset - lwu $s3,-24086($v1) # CHECK: :[[@LINE]]:23: error: expected memory with 12-bit signed offset + lld $zero,-14736($ra) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + lwu $s3,-24086($v1) # CHECK: :[[@LINE]]:23: error: invalid operand for instruction round.l.d $f12,$f1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled round.l.s $f25,$f5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled round.w.d $f6,$f4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled |
