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| author | Craig Topper <craig.topper@intel.com> | 2018-06-01 05:12:44 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2018-06-01 05:12:44 +0000 |
| commit | 74a61b02e05dc8433a9e05487ab75697a95d1163 (patch) | |
| tree | 1568486bed6afed8cda749b451bbb46612273506 /llvm/test/MC/Disassembler/X86 | |
| parent | 1a00b0ac27321d69cfe30e708d0059bb43841d70 (diff) | |
| download | bcm5719-llvm-74a61b02e05dc8433a9e05487ab75697a95d1163.tar.gz bcm5719-llvm-74a61b02e05dc8433a9e05487ab75697a95d1163.zip | |
[X86][Disassembler] Clamp index to 4-bits when decoding GPR registers.
A 5-bit value can occur when EVEX.X is 0 due to it being used to extend modrm.rm to encode XMM16-31. But if modrm.rm instead encodes a GPR, the Intel documentation says EVEX.X should be ignored so just mask it to 4 bits once we know its a GPR.
llvm-svn: 333725
Diffstat (limited to 'llvm/test/MC/Disassembler/X86')
| -rw-r--r-- | llvm/test/MC/Disassembler/X86/x86-64.txt | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/test/MC/Disassembler/X86/x86-64.txt b/llvm/test/MC/Disassembler/X86/x86-64.txt index 2bbd3f72b3c..566a69e1007 100644 --- a/llvm/test/MC/Disassembler/X86/x86-64.txt +++ b/llvm/test/MC/Disassembler/X86/x86-64.txt @@ -581,5 +581,5 @@ #CHECK: vaddps (%rax), %xmm16, %xmm1 0x62 0xb1 0x7c 0x00 0x58 0x08 -#CHECK: vcvtusi2sdq %mm0, %xmm1, %xmm1 +#CHECK: vcvtusi2sdq %rax, %xmm1, %xmm1 0x62 0xb1 0xf7 0x08 0x7b 0xc8 |
