[SystemZ] Add missing classes and instructions

Summary:
Add instruction formats E, RSI, SSd, SSE, and SSF.

Added BRXH, BRXLE, PR, MVCK, STRAG, and ECTG instructions to test out
those formats.

Reviewers: uweigand

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D23179

llvm-svn: 277822

2 files changed, 111 insertions, 0 deletions

diff --git a/llvm/test/MC/Disassembler/SystemZ/insns-pcrel.txt b/llvm/test/MC/Disassembler/SystemZ/insns-pcrel.txt
index d3579481e1f..d6ef5ac1698 100644
--- a/llvm/test/MC/Disassembler/SystemZ/insns-pcrel.txt
+++ b/llvm/test/MC/Disassembler/SystemZ/insns-pcrel.txt
@@ -1762,3 +1762,51 @@
 # 0x00000a02:
 # CHECK: exrl %r15, 0x100000a00
 0xc6 0xf0 0x7f 0xff 0xff 0xff
+
+# 0x00000a08:
+# CHECK: brxh %r0, %r1, 0xa08
+0x84 0x01 0x00 0x00
+
+# 0x00000a0c:
+# CHECK: brxh %r14, %r1, 0xa0c
+0x84 0xe1 0x00 0x00
+
+# 0x00000a10:
+# CHECK: brxh %r15, %r1, 0xa10
+0x84 0xf1 0x00 0x00
+
+# 0x00000a14:
+# CHECK: brxh %r0, %r1, 0xa12
+0x84 0x01 0xff 0xff
+
+# 0x00000a18:
+# CHECK: brxh %r14, %r1, 0xffffffffffff0a18
+0x84 0xe1 0x80 0x00
+
+# 0x00000a1c:
+# CHECK: brxh %r15, %r1, 0x10a1a
+0x84 0xf1 0x7f 0xff
+
+# 0x00000a20:
+# CHECK: brxle %r0, %r1, 0xa20
+0x85 0x01 0x00 0x00
+
+# 0x00000a24:
+# CHECK: brxle %r14, %r1, 0xa24
+0x85 0xe1 0x00 0x00
+
+# 0x00000a28:
+# CHECK: brxle %r15, %r1, 0xa28
+0x85 0xf1 0x00 0x00
+
+# 0x00000a2c:
+# CHECK: brxle %r0, %r1, 0xa2a
+0x85 0x01 0xff 0xff
+
+# 0x00000a30:
+# CHECK: brxle %r14, %r1, 0xffffffffffff0a30
+0x85 0xe1 0x80 0x00
+
+# 0x00000a34:
+# CHECK: brxle %r15, %r1, 0x10a32
+0x85 0xf1 0x7f 0xff
diff --git a/llvm/test/MC/Disassembler/SystemZ/insns.txt b/llvm/test/MC/Disassembler/SystemZ/insns.txt
index 80756baed6b..20bf52a455b 100644
--- a/llvm/test/MC/Disassembler/SystemZ/insns.txt
+++ b/llvm/test/MC/Disassembler/SystemZ/insns.txt
@@ -3199,6 +3199,27 @@
 # CHECK: ear %r15, %a15
 0xb2 0x4f 0x00 0xff
 
+# CHECK: ectg 0, 0, %r0
+0xc8 0x01 0x00 0x00 0x00 0x00
+
+# CHECK: ectg 0, 4095, %r2
+0xc8 0x21 0x00 0x00 0x0f 0xff
+
+# CHECK: ectg 0, 0(%r1), %r2
+0xc8 0x21 0x00 0x00 0x10 0x00
+
+# CHECK: ectg 0, 0(%r15), %r2
+0xc8 0x21 0x00 0x00 0xf0 0x00
+
+# CHECK: ectg 0(%r1), 4095(%r15), %r2
+0xc8 0x21 0x10 0x00 0xff 0xff
+
+# CHECK: ectg 0(%r1), 0(%r15), %r2
+0xc8 0x21 0x10 0x00 0xf0 0x00
+
+# CHECK: ectg 4095(%r1), 0(%r15), %r2
+0xc8 0x21 0x1f 0xff 0xf0 0x00
+
 # CHECK: etnd %r0
 0xb2 0xec 0x00 0x00
 
@@ -6502,6 +6523,27 @@
 # CHECK: mvc 0(256,%r15), 0
 0xd2 0xff 0xf0 0x00 0x00 0x00
 
+# CHECK: mvck 0, 0, %r0
+0xd9 0x00 0x00 0x00 0x00 0x00
+
+# CHECK: mvck 0, 4095, %r2
+0xd9 0x02 0x00 0x00 0x0f 0xff
+
+# CHECK: mvck 0, 0(%r1), %r2
+0xd9 0x02 0x00 0x00 0x10 0x00
+
+# CHECK: mvck 0, 0(%r15), %r2
+0xd9 0x02 0x00 0x00 0xf0 0x00
+
+# CHECK: mvck 0(%r1), 4095(%r15), %r2
+0xd9 0x02 0x10 0x00 0xff 0xff
+
+# CHECK: mvck 0(%r1), 0(%r15), %r2
+0xd9 0x02 0x10 0x00 0xf0 0x00
+
+# CHECK: mvck 4095(%r15,%r1), 0(%r15), %r2
+0xd9 0xf2 0x1f 0xff 0xf0 0x00
+
 # CHECK: mvghi 0, 0
 0xe5 0x48 0x00 0x00 0x00 0x00
 
@@ -7309,6 +7351,9 @@
 # CHECK: pfd 15, 0
 0xe3 0xf0 0x00 0x00 0x00 0x36
 
+# CHECK: pr
+0x01 0x01
+
 # CHECK: popcnt %r0, %r0
 0xb9 0xe1 0x00 0x00
 
@@ -9022,6 +9067,24 @@
 # CHECK: stmy %r0, %r0, 524287(%r15)
 0xeb 0x00 0xff 0xff 0x7f 0x90
 
+# CHECK: strag 0, 0
+0xe5 0x02 0x00 0x00 0x00 0x00
+
+# CHECK: strag 0, 4095
+0xe5 0x02 0x00 0x00 0x0f 0xff
+
+# CHECK: strag 0, 0(%r1)
+0xe5 0x02 0x00 0x00 0x10 0x00
+
+# CHECK: strag 0, 0(%r15)
+0xe5 0x02 0x00 0x00 0xf0 0x00
+
+# CHECK: strag 0(%r1), 4095(%r15)
+0xe5 0x02 0x10 0x00 0xff 0xff
+
+# CHECK: strag 4095(%r1), 0(%r15)
+0xe5 0x02 0x1f 0xff 0xf0 0x00
+
 # CHECK: strvg %r0, -524288
 0xe3 0x00 0x00 0x00 0x80 0x2f