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| author | Petar Jovanovic <petar.jovanovic@imgtec.com> | 2017-06-23 12:47:18 +0000 |
|---|---|---|
| committer | Petar Jovanovic <petar.jovanovic@imgtec.com> | 2017-06-23 12:47:18 +0000 |
| commit | d5f7711ebb1a6b4df4704693f17a376f76137381 (patch) | |
| tree | 30322fcd97ff94e2ba152512f7990e17694050bb /llvm/test/MC/Disassembler/Mips/mips64r6 | |
| parent | ac16a201a66b036646c9d26c396ffb7bae45aa75 (diff) | |
| download | bcm5719-llvm-d5f7711ebb1a6b4df4704693f17a376f76137381.tar.gz bcm5719-llvm-d5f7711ebb1a6b4df4704693f17a376f76137381.zip | |
[mips] Fix register positions in the aui/daui instructions
Swapped the position of the rt and rs register in the aut/daui instructions
for mips32r6 and mips64r6. With this change, the format of the generated
instructions complies with specifications and GCC.
Patch by Milos Stojanovic.
Differential Revision: https://reviews.llvm.org/D33988
llvm-svn: 306095
Diffstat (limited to 'llvm/test/MC/Disassembler/Mips/mips64r6')
| -rw-r--r-- | llvm/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6-el.txt | 4 | ||||
| -rw-r--r-- | llvm/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6.txt | 4 |
2 files changed, 4 insertions, 4 deletions
diff --git a/llvm/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6-el.txt b/llvm/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6-el.txt index f436b873aa1..eefd8c6e761 100644 --- a/llvm/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6-el.txt +++ b/llvm/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6-el.txt @@ -4,7 +4,7 @@ 0xa0 0x22 0x43 0x7c # CHECK: align $4, $2, $3, 2 0x38 0x00 0x7f 0xec # CHECK: aluipc $3, 56 0x04 0x00 0x42 0x30 # CHECK: andi $2, $2, 4 -0xe9 0xff 0x62 0x3c # CHECK: aui $3, $2, 65513 +0xe9 0xff 0x43 0x3c # CHECK: aui $3, $2, 65513 0xff 0xff 0x7e 0xec # CHECK: auipc $3, -1 0x9b 0x14 0x11 0x04 # CHECK: bal 21104 0xb8 0x96 0x37 0xe8 # CHECK: balc 14572260 @@ -97,7 +97,7 @@ 0x78 0x56 0x66 0x04 # CHECK: dahi $3, $3, 22136 0xcd 0xab 0x7e 0x04 # CHECK: dati $3, $3, 43981 0x64 0x23 0x43 0x7c # CHECK: dalign $4, $2, $3, 5 -0x34 0x12 0x62 0x74 # CHECK: daui $3, $2, 4660 +0x34 0x12 0x43 0x74 # CHECK: daui $3, $2, 4660 0x24 0x20 0x02 0x7c # CHECK: dbitswap $4, $2 0x53 0x90 0xc0 0x00 # CHECK: dclo $18, $6 0x52 0x80 0x20 0x03 # CHECK: dclz $16, $25 diff --git a/llvm/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6.txt b/llvm/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6.txt index 15c9ca1082e..89c49e28dc6 100644 --- a/llvm/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6.txt +++ b/llvm/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6.txt @@ -77,7 +77,7 @@ 0x25 0x29 0x00 0x0a # CHECK: addiu $9, $9, 10 0x30 0x42 0x00 0x04 # CHECK: andi $2, $2, 4 0x34 0x42 0x00 0x04 # CHECK: ori $2, $2, 4 -0x3c 0x62 0xff 0xe9 # CHECK: aui $3, $2, 65513 +0x3c 0x43 0xff 0xe9 # CHECK: aui $3, $2, 65513 0x40 0x08 0x78 0x01 # CHECK: mfc0 $8, $15, 1 0x40 0x08 0x80 0x03 # CHECK: mfc0 $8, $16, 3 0x40 0x38 0x50 0x00 # CHECK: dmfc0 $24, $10, 0 @@ -197,7 +197,7 @@ 0x60 0x82 0x00 0x01 # CHECK: bnvc $4, $2, 8 0x60 0xa6 0x00 0x40 # CHECK: bnec $5, $6, 260 0x60 0x43 0xff 0xfa # CHECK: bnec $2, $3, -20 -0x74 0x62 0x12 0x34 # CHECK: daui $3, $2, 4660 +0x74 0x43 0x12 0x34 # CHECK: daui $3, $2, 4660 0x7c 0x02 0x20 0x20 # CHECK: bitswap $4, $2 0x7c 0x02 0x20 0x24 # CHECK: dbitswap $4, $2 0x7c 0x43 0x22 0xa0 # CHECK: align $4, $2, $3, 2 |
