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| author | Jim Grosbach <grosbach@apple.com> | 2014-04-17 20:47:31 +0000 |
|---|---|---|
| committer | Jim Grosbach <grosbach@apple.com> | 2014-04-17 20:47:31 +0000 |
| commit | 0fba6d98fcb0438f1fc4f0c67e989f49843762ec (patch) | |
| tree | fe3f261810f1755fc830e8cc945b5219e0dd5cc2 /llvm/test/MC/ARM64 | |
| parent | 4b600d3f0b923b5f8c1d39bb944e12e370c10013 (diff) | |
| download | bcm5719-llvm-0fba6d98fcb0438f1fc4f0c67e989f49843762ec.tar.gz bcm5719-llvm-0fba6d98fcb0438f1fc4f0c67e989f49843762ec.zip | |
ARM64: [su]xtw use W regs as inputs, not X regs.
Update the SXT[BHW]/UXTW instruction aliases and the shifted reg addressing
mode handling.
PR19455 and rdar://16650642
llvm-svn: 206495
Diffstat (limited to 'llvm/test/MC/ARM64')
| -rw-r--r-- | llvm/test/MC/ARM64/aliases.s | 26 | ||||
| -rw-r--r-- | llvm/test/MC/ARM64/memory.s | 8 |
2 files changed, 17 insertions, 17 deletions
diff --git a/llvm/test/MC/ARM64/aliases.s b/llvm/test/MC/ARM64/aliases.s index f0d1d5d76a5..4fe4b93d4fc 100644 --- a/llvm/test/MC/ARM64/aliases.s +++ b/llvm/test/MC/ARM64/aliases.s @@ -239,19 +239,19 @@ foo: ; CHECK: uxtb w1, w2 ; CHECK: uxth w1, w2 - sxtb x1, x2 - sxth x1, x2 - sxtw x1, x2 - uxtb x1, x2 - uxth x1, x2 - uxtw x1, x2 - -; CHECK: sxtb x1, x2 -; CHECK: sxth x1, x2 -; CHECK: sxtw x1, x2 -; CHECK: uxtb x1, x2 -; CHECK: uxth x1, x2 -; CHECK: uxtw x1, x2 + sxtb x1, w2 + sxth x1, w2 + sxtw x1, w2 + uxtb x1, w2 + uxth x1, w2 + uxtw x1, w2 + +; CHECK: sxtb x1, w2 +; CHECK: sxth x1, w2 +; CHECK: sxtw x1, w2 +; CHECK: uxtb x1, w2 +; CHECK: uxth x1, w2 +; CHECK: uxtw x1, w2 ;----------------------------------------------------------------------------- ; Negate with carry diff --git a/llvm/test/MC/ARM64/memory.s b/llvm/test/MC/ARM64/memory.s index 47188c6b67a..579859660f9 100644 --- a/llvm/test/MC/ARM64/memory.s +++ b/llvm/test/MC/ARM64/memory.s @@ -426,14 +426,14 @@ foo: ; CHECK: ldr q1, [x1, x2, lsl #4] ; encoding: [0x21,0x78,0xe2,0x3c] str d1, [sp, x3] - str d1, [sp, x3, uxtw #3] + str d1, [sp, w3, uxtw #3] str q1, [sp, x3] - str q1, [sp, x3, uxtw #4] + str q1, [sp, w3, uxtw #4] ; CHECK: str d1, [sp, x3] ; encoding: [0xe1,0x6b,0x23,0xfc] -; CHECK: str d1, [sp, x3, uxtw #3] ; encoding: [0xe1,0x5b,0x23,0xfc] +; CHECK: str d1, [sp, w3, uxtw #3] ; encoding: [0xe1,0x5b,0x23,0xfc] ; CHECK: str q1, [sp, x3] ; encoding: [0xe1,0x6b,0xa3,0x3c] -; CHECK: str q1, [sp, x3, uxtw #4] ; encoding: [0xe1,0x5b,0xa3,0x3c] +; CHECK: str q1, [sp, w3, uxtw #4] ; encoding: [0xe1,0x5b,0xa3,0x3c] ;----------------------------------------------------------------------------- ; Load literal |
