diff options
| author | Tom Stellard <thomas.stellard@amd.com> | 2016-02-11 18:25:26 +0000 |
|---|---|---|
| committer | Tom Stellard <thomas.stellard@amd.com> | 2016-02-11 18:25:26 +0000 |
| commit | e993451f5c5a15ff14b8b7d2da228e300da44579 (patch) | |
| tree | 92a34c1488bbc9ad94ca1615cecd48abee0d4e32 /llvm/test/MC/AMDGPU | |
| parent | 6fadea62b5d2c6544539af61d95f023f9e699f89 (diff) | |
| download | bcm5719-llvm-e993451f5c5a15ff14b8b7d2da228e300da44579.tar.gz bcm5719-llvm-e993451f5c5a15ff14b8b7d2da228e300da44579.zip | |
[AMDGPU] Fix for "v_div_scale_f64 reg, vcc, ..." parsing
Summary:
Added support for "VOP3Only" attribute in VOP3bInst encoding.
Set VOP3Only=1 for V_DIV_SCALE_F64/32 insns.
Added support for multi-dest instructions in AMDGPUAs::cvt*().
Added lit test for "V_DIV_SCALE_F64|F32 vreg,vcc|sreg,vreg,vreg,vreg".
Reviewers: tstellarAMD, arsenm
Subscribers: arsenm, SamWot, nhaustov, vpykhtin
Differential Revision: http://reviews.llvm.org/D16995
Patch By: Artem Tamazov
llvm-svn: 260560
Diffstat (limited to 'llvm/test/MC/AMDGPU')
| -rw-r--r-- | llvm/test/MC/AMDGPU/vop3.s | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/llvm/test/MC/AMDGPU/vop3.s b/llvm/test/MC/AMDGPU/vop3.s index 0161e33a12c..6e8c01dc460 100644 --- a/llvm/test/MC/AMDGPU/vop3.s +++ b/llvm/test/MC/AMDGPU/vop3.s @@ -270,3 +270,22 @@ v_add_f64_e64 v[0:1], -v[2:3], |v[5:6]| clamp mul:4 // SICI: v_add_f64 v[0:1], -v[2:3], |v[5:6]| clamp mul:4 ; encoding: [0x00,0x0a,0xc8,0xd2,0x02,0x0b,0x02,0x30] // VI: v_add_f64 v[0:1], -v[2:3], |v[5:6]| clamp mul:4 ; encoding: [0x00,0x82,0x80,0xd2,0x02,0x0b,0x02,0x30] +v_div_scale_f64 v[24:25], vcc, v[22:23], v[22:23], v[20:21] +// SICI: v_div_scale_f64 v[24:25], vcc, v[22:23], v[22:23], v[20:21] ; encoding: [0x18,0x6a,0xdc,0xd2,0x16,0x2d,0x52,0x04] +// VI: v_div_scale_f64 v[24:25], vcc, v[22:23], v[22:23], v[20:21] ; encoding: [0x18,0x6a,0xe1,0xd1,0x16,0x2d,0x52,0x04] + +v_div_scale_f64 v[24:25], s[10:11], v[22:23], v[20:21], v[20:21] +// SICI: v_div_scale_f64 v[24:25], s[10:11], v[22:23], v[20:21], v[20:21] ; encoding: [0x18,0x0a,0xdc,0xd2,0x16,0x29,0x52,0x04] +// VI: v_div_scale_f64 v[24:25], s[10:11], v[22:23], v[20:21], v[20:21] ; encoding: [0x18,0x0a,0xe1,0xd1,0x16,0x29,0x52,0x04] + +v_div_scale_f32 v24, vcc, v22, v22, v20 +// SICI: v_div_scale_f32 v24, vcc, v22, v22, v20 ; encoding: [0x18,0x6a,0xda,0xd2,0x16,0x2d,0x52,0x04] +// VI: v_div_scale_f32 v24, vcc, v22, v22, v20 ; encoding: [0x18,0x6a,0xe0,0xd1,0x16,0x2d,0x52,0x04] + +v_div_scale_f32 v24, vcc, s[10:11], v22, v20 +// SICI: v_div_scale_f32 v24, vcc, s[10:11], v22, v20 ; encoding: [0x18,0x6a,0xda,0xd2,0x0a,0x2c,0x52,0x04] +// VI: v_div_scale_f32 v24, vcc, s[10:11], v22, v20 ; encoding: [0x18,0x6a,0xe0,0xd1,0x0a,0x2c,0x52,0x04] + +v_div_scale_f32 v24, s[10:11], v22, v22, v20 +// SICI: v_div_scale_f32 v24, s[10:11], v22, v22, v20 ; encoding: [0x18,0x0a,0xda,0xd2,0x16,0x2d,0x52,0x04] +// VI: v_div_scale_f32 v24, s[10:11], v22, v22, v20 ; encoding: [0x18,0x0a,0xe0,0xd1,0x16,0x2d,0x52,0x04] |
